Data storage unit, memory and memory manufacturing method thereof

Abstract

A data storage unit, a memory and a memory fabrication method are disclosed. The memory fabrication method includes forming a plurality of gate electrode lines to form gates of a plurality of data storage units, respectively, and forming a plurality of conductive lines. The plurality of data storage units are arranged in an array. Each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines, and each of the plurality of conductive lines at least partially overlaps the two of the plurality of gate electrode lines.

Description

TECHNICAL FIELD

[0001] The present application relates to a data storage unit, a memory and a memory manufacturing method thereof, and more particularly, to a data storage unit with higher reliability, a memory and a memory manufacturing method thereof. BACKGROUND

[0002] The field of semiconductor memory has received much attention in recent years. Semiconductor memory can be volatile or non-volatile. Non-volatile semiconductor memory is capable of retaining data even when unpowered and is thus widely used in electronic devices such as cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and the like.

[0003] In a memory, the length of a word line can cause non-negligible power loss, which affects the voltage provided by the word line to data storage units of the memory, and further causes instability in write or read operations. In addition, multiple film layers can be provided between the gate of a data storage unit and a word line, which can cause the potential of the gate to be different. Moreover, when the manufacturing process of a gate electrode line is defective, signal transmission can be abnormal. Therefore, how to optimize the design of the configuration of a word line has become an important issue. SUMMARY

[0004] Therefore, the present application mainly provides a data storage unit, a memory and a memory manufacturing method thereof to improve reliability.

[0005] A memory manufacturing method is disclosed. The memory forming method includes forming a plurality of gate electrode lines to form gates of a plurality of data storage units, respectively, wherein the plurality of data storage units are arranged in an array; and forming a plurality of conductive lines, wherein each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines, and each of the plurality of conductive lines at least partially overlaps the two of the plurality of gate electrode lines.

[0006] A memory is also disclosed. The memory includes a plurality of data storage units arranged in an array, wherein gates of the plurality of data storage units are formed by a plurality of gate electrode lines, respectively; and a plurality of conductive lines, wherein each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines, and each of the plurality of conductive lines at least partially overlaps the two of the plurality of gate electrode lines.

[0007] The application also discloses a data storage unit. The data storage unit comprises a storage structure, a first transistor and a second transistor. The first end of the storage structure is electrically connected to a bit line. The first transistor comprises a first gate, a first drain and a first source. The second transistor comprises a second gate, a second drain and a second source. The first gate is electrically connected to the second gate. The second end of the storage structure is electrically connected to the first drain and the second drain. The first source and the second source are electrically connected to a source line. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 Equivalent circuit schematic diagram of a memory of an embodiment of the application;

[0009] Figure 2 Equivalent circuit schematic diagram of a memory of an embodiment of the application;

[0010] Figure 3 Partial schematic diagram of a memory of an embodiment of the application; Figure 2

[0011] Figures 4 to 21 Schematic diagram of a manufacturing method of a memory of an embodiment of the application;

[0012] Figure 22 Figure 23 Partial schematic diagram of a memory of an embodiment of the application.

[0013] Explanation of main element symbols

[0014]

[0015] DETAILED DESCRIPTION

[0016] For the convenience of explanation, the drawings of the application are only schematic so as to more easily understand the application, and the detailed proportions can be adjusted according to the design requirements. The relative positions of the elements in the drawings described in the text are understood by those skilled in the art to refer to the relative positions of the objects, so that the same components can be reversed and included in the embodiments of the objects in direct contact or not in direct contact, which should be included in the scope disclosed in the specification, and this is stated herein.

[0017] Throughout the specification and the appended claims, the term "comprising" is an open term, which should be interpreted as "including, but not limited to". Throughout the specification and the subsequent claims, the terms "first", "second", etc. are used only to distinguish different elements, and do not limit the order. The embodiments can be combined in various ways without contradiction. ​​

[0018] Reference is made to Figure 1 , Figure 1 Figure 1 shows a schematic diagram of an equivalent circuit of a memory 10 according to an embodiment of the present application. The memory 10 can include a data storage cell DSC, a source line SL, a bit line BL, a conductive line M0 (also referred to as a first conductive line), and a conductive line (e.g. Figure 3 a conductive line M5 (also referred to as a second conductive line)) corresponding to a resistance Rm5. The data storage cell DSC can include a storage structure Rt, transistors TT1, TT2, and resistances Rpl1, Rpl2. The transistor TT1 (also referred to as a first transistor) includes a gate G1 (also referred to as a first gate), a drain D1 (also referred to as a first drain), and a source S1 (also referred to as a first source). The transistor TT2 (also referred to as a second transistor) includes a gate G2 (also referred to as a second gate), a drain D2 (also referred to as a second drain), and a source S2 (also referred to as a second source).

[0019] In brief, the second conductive line corresponding to the resistance Rm5 can serve as a word line, which can cause power loss. Therefore, the resistance value of the resistance Rm5 is reduced to decrease the cross voltage consumed by the resistance Rm5. In addition, a plurality of film layers (e.g. Figure 19 conducting layers M2, M4) can be disposed between the gates (e.g. the gate G1 of the transistor TT1 or the gate G2 of the transistor TT2) of the transistors TT1, TT2 and the word line, which can cause the potentials of the gates G1, G2 of the transistors TT1, TT2 to be different. The present application can ensure equipotential by directly connecting the conductive line M0 to the gates G1, G2, thereby improving reliability.

[0020] In detail, the word line can have a word line voltage input terminal Pnt for receiving a word line voltage (e.g. from a control circuit). The gate G1 is electrically connected to the gate G2, e.g. the gate G1 is electrically connected (directly connected and in contact with) to the gate G2 via the conductive line M0. Accordingly, a first potential difference dV1 between the gate G1 and the word line voltage input terminal Pnt is equal to a second potential difference dV2 between the gate G2 and the word line voltage input terminal Pnt. The gates G1, G2 substantially have the same potential, i.e. the potential Vg1 of the gate G1 is equal to the potential Vg2 of the gate G2.

[0021] The gate G1, G2 of the transistor TT1, TT2 can be electrically connected (directly connected and contacted) to a first end of the resistance Rpl1 (may also be referred to as a first resistance), and the gate G1, G2 of the transistor TT1, TT2 can be electrically connected (directly connected and contacted) to a first end of the resistance Rpl2 (may also be referred to as a second resistance) through the conductive wire M0. A second end of the resistance Rpl1 and a second end of the resistance Rpl2 are electrically connected to the word line voltage input end Pnt through the resistance Rm5 corresponding to the second conductive wire. In this way, the gate G1, G2 of the transistor TT1, TT2 is coupled to the same word line. In some embodiments, the transistor TT1, TT2 can be connected in parallel. The source S1, S2 of the transistor TT1, TT2 can be electrically connected to the source line SL, and the drain D1, D2 can be electrically connected to a second end of the storage structure Rt.

[0022] In some embodiments, the resistance Rm5 is a resistance formed by part of the second conductive wire. In some embodiments, the resistance value of the resistance Rm5 corresponding to the second conductive wire can be one fifth of the conventional technology, for example, the resistance value of the resistance Rm5 can be between 10 Ohm and 1280 Ohm. For a 28 nanometer process technology, the resistance value of the resistance Rm5 can be between 10 Ohm and 640 Ohm. For example, when there are 64 bit lines BL between two adjacent word line voltage input ends Pnt, the resistance value of the resistance Rm5 can be 10 Ohm; when there are 4096 bit lines BL between two adjacent word line voltage input ends Pnt, the resistance value of the resistance Rm5 can be 640 Ohm. For a 14 nanometer process technology, the resistance value of the resistance Rm5 can be between 20 Ohm and 1280 Ohm. For example, when there are 64 bit lines BL between two adjacent word line voltage input ends Pnt, the resistance value of the resistance Rm5 can be 20 Ohm; when there are 4096 bit lines BL between two adjacent word line voltage input ends Pnt, the resistance value of the resistance Rm5 can be 1280 Ohm. In some embodiments, the resistance value of the resistance Rm5 can be reduced by increasing the cross-sectional area (or thickness, width) of the second conductive wire or changing the material or wiring method of the second conductive wire. The increased cross-sectional area (or thickness, width) can reduce the load of the second conductive wire, thereby reducing the voltage drop of the second conductive wire (or between the gate G1 or G2 and the word line voltage input end Pnt).

[0023] A first end of the storage structure Rt is electrically connected to the bit line BL. In some embodiments, the storage structure Rt is used to store a data bit. In some embodiments, the storage structure Rt can be a variable resistance to define an internal data state. By applying different voltages or currents to the storage structure Rt, the resistance value of the storage structure Rt can be changed. By determining the resistance value of the storage structure Rt, the bit value can be read. For example, when the resistance value of the storage structure Rt is in a low resistance state or a high resistance state, the value stored by the state can be represented as "0" or "1", but the application is not limited thereto. In some embodiments, the storage structure Rt can include a magnetic storage element, such as a magnetic tunnel junction (MTJ) element. In some embodiments, the memory 10 can be a resistive random-access memory (RRAM), a magnetic random access memory (MRAM), a ferroelectric random-access memory (FeRAM), a phase-change memory (PRAM), but the application is not limited thereto. In some embodiments, the memory 10 can be a non-volatile memory (NVM).

[0024] In the present embodiment, the data storage unit DSC can be a two-transistor one-resistor (2T1R) bit cell, for example, to increase the drive current value and thus speed up the write or read operation; in other embodiments, the data storage unit DSC can be a one-transistor two-resistor (1T1R) bit cell, a one-transistor one-capacitor (1T1C) bit cell, a two-transistor one-capacitor (2T1C) bit cell, but the application is not limited thereto. In some embodiments, the transistors TT1, TT2 of the data storage unit DSC can be a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate field effect transistor (IGFET), or a bipolar transistor, but the application is not limited thereto.

[0025] More specifically, please refer to Figure 2and Figure 3 , Figure 2 This is a schematic diagram of the equivalent circuit of the memory 20 in Embodiment 1 of the present invention. Figure 3 Embodiments of the present invention Figure 2 A partial schematic diagram of the memory 20 shown. Figure 2 The architecture of the memory 20 shown is similar to Figure 1 The memory 10 shown uses the same symbols for the same components. The memory 20 may include multiple data storage units (DSC) and source lines SL1 to SLn (corresponding to...). Figure 1 The source line SL and bit lines BL1 to BL2n (corresponding to...) are shown. Figure 1 The diagram shows bit lines BL, gate electrode lines PL1 to PL2m, and multiple conductive lines M0 and M5. Conductive line M5 (also known as the second conductive line) can be used as word lines WL1 to WLm.

[0026] like Figure 2 As shown, the data storage cells (DSCs) are arranged in an array. The gates G1 and G2 of the DSCs form gate electrode lines PL1 to PL2m, respectively. For example, the gates G1 and G2 of the DSCs form gate electrode lines PL(2m-1) and PL2m, respectively. The gate electrode lines PL1 to PL2m extend vertically along the columns of the array. Similarly, the word lines WL1 to WLm formed by the conductive lines M5 extend vertically along the columns of the array and are electrically connected to the corresponding column of the DSCs. The gate electrode lines PL1 to PL2m are parallel to the conductive lines M5 that serve as word lines WL1 to WLm. The source lines SL1 to SLn and the bit lines BL1 to BL2n extend horizontally along the rows of the array and are electrically connected to the corresponding row of the DSCs. In some embodiments, word lines WL1 to WLm are used to select data storage cells DSC column by column, and source lines SL1 to SLn and bit lines BL1 to BL2n are used to perform writing or reading operations on the selected data storage cells DSC row by row, but are not limited thereto.

[0027] In some embodiments, two of the gate electrode lines PL1~PL2m are grouped into a set, and the intersection of any two sets is an empty set, that is, a gate electrode line does not belong to different sets at the same time. One conductive line M5 is coupled to the gate electrode lines in the same set, for example, one word line WLm is coupled to the adjacent gate electrode lines PL(2m-1), PL2m. That is, each of the conductive lines M5 is coupled to two of the gate electrode lines PL1~PL2m. In some embodiments, each of the conductive lines M5 that can be a word line WL1~WLm at least partially overlaps with two of the gate electrode lines PL1~PL2m, for example, one conductive line M5 partially overlaps with the adjacent gate electrode lines PL(2m-1), PL2m. As shown in FIG. 9, the conductive line M5 exposes, for example, the left side of the gate electrode line PL(2m-1) and the right side of the gate electrode line PL2m, so each of the conductive lines M5 does not completely overlap with two of the gate electrode lines PL1~PL2m. In some embodiments, a second pitch PTH3 between two adjacent ones of the conductive lines M5 is greater than or equal to twice a first pitch PTH1 between two adjacent ones of the gate electrode lines PL1~PL2m, and a gap width GTH1 between two adjacent ones of the gate electrode lines PL1~PL2m is less than or equal to the second width WD3 of the conductive line M5. In some embodiments, the second pitch PTH3 between two adjacent ones of the conductive lines M5 can be 260 nanometers (nm), and the gap width GTH3 between two adjacent ones of the conductive lines M5 can be 120 nanometers. Figure 3

[0028] Since the memory 20 can include a large number of data storage units DSC, the length of the word lines WL1~WLm can cause a high load, which cannot be ignored, and affect the voltage provided by the word lines WL1~WLm to the data storage units DSC, thereby causing instability of the write or read operation. By increasing the width of the conductive line M5, the resistance value of the conductive line M5 can be reduced, and by reducing the resistance value of the conductive line M5, the cross voltage consumed by the conductive line M5 can be reduced, thereby reducing the line load. In some embodiments, the first width WD1 of the gate electrode lines PL1~PL2m is 0.2 to 0.5 times the second width WD3 of the conductive line M5, but is not limited thereto. In some embodiments, the second width WD3 of the conductive line M5 can be 140 nanometers. In some embodiments, the gate electrode lines PL1~PL2m can have different thicknesses or widths, and the plurality of conductive lines M5 can have different thicknesses or widths.

[0029] ​In some embodiments, the conductive lines M0 are evenly spaced and laterally elongated parallel along the rows of the array. The source lines SL1~SLn and the bit lines BL1~BL2n are parallel to the conductive lines M0. In some embodiments, at least one conductive line M0 is electrically connected (e.g., directly connected and in contact with) or electrically shorted to the gate electrode lines of the same set of the gate electrode lines PL1~PL2m, for example, at least one conductive line M0 is electrically connected to the adjacent gate electrode lines PL(2m-1), PL2m. That is, each of the conductive lines M0 is coupled to two of the gate electrode lines PL1~PL2m. In some embodiments, one conductive line M0 is coupled to only one word line, for example, the conductive line M0k1 is coupled to only the word line WL1. The gate (e.g., the gates G1, G2) of the data storage cell DSC or its corresponding gate electrode line to word line (e.g., the word line WLm) can be provided with multiple film layers (e.g., the conductive layers M2, M4) shown, which can cause the potential of the gate (i.e., the gates G1, G2) or its corresponding gate electrode line to be different. Directly connecting the conductive line M0 to the gates G1, G2 or its corresponding gate electrode lines PL(2m-1), PL2m can ensure the same potential. In addition, when the conductive line M0 is directly connected to the gate electrode line (e.g., the gate electrode lines PL(2m-1), PL2m), the conductive line M0 can further avoid the manufacturing process defects (e.g., the gate electrode line PL2m is broken) of the gate electrode lines PL1~PL2m from causing abnormal signal transmission (e.g., the gate G1 located at the gate electrode line PL2m cannot change with the word line WLm). Figure 19 The conductive layers M2, M4 shown, which can cause the potential of the gate (i.e., the gates G1, G2) or its corresponding gate electrode line to be different. Directly connecting the conductive line M0 to the gates G1, G2 or its corresponding gate electrode lines PL(2m-1), PL2m can ensure the same potential. In addition, when the conductive line M0 is directly connected to the gate electrode line (e.g., the gate electrode lines PL(2m-1), PL2m), the conductive line M0 can further avoid the manufacturing process defects (e.g., the gate electrode line PL2m is broken) of the gate electrode lines PL1~PL2m from causing abnormal signal transmission (e.g., the gate G1 located at the gate electrode line PL2m cannot change with the word line WLm).

[0030] In some embodiments, each of the conductive lines M0 at least partially overlaps with two of the gate electrode lines PL1~PL2m to electrically connect and contact the gate electrode lines, for example, at least one of the conductive lines M0 partially overlaps with adjacent gate electrode lines PL(2m-1), PL2m. In some embodiments, a first width WD1 of the gate electrode lines PL1~PL2m is 0.5 to 1 times a second width WD2 of the conductive lines M0, and the first width WD1 of the gate electrode lines PL1~PL2m is 0.1 to 0.2 times a length LTH of the conductive lines M0, but the present disclosure is not limited thereto. In some embodiments, the plurality of conductive lines M0 can have different lengths or widths, and the gate electrode lines PL1~PL2m can have different lengths or widths. In some embodiments, the conductive lines M0 coupled to adjacent sets of the gate electrode lines are arranged alternately and misaligned, for example, the conductive line M0k1 is coupled to the gate electrode lines PL1, PL2 in one set, the conductive line M0(k+1)2 is coupled to the gate electrode lines PL3, PL4 in another adjacent set, and the conductive lines M0k1, M0(k+1)2 are arranged alternately and misaligned. In some embodiments, the alternately arranged conductive lines M0 are electrically isolated from each other without being coupled, for example, the conductive lines M0k1, M0(k+1)2 are electrically isolated from each other without being coupled.

[0031] In some embodiments, two adjacent conductive lines M0 in the same column can be separated by one column (or more columns) of data storage units DSC, for example, two adjacent conductive lines M0(k-1)1, M0k1 in the same column can be separated by one data storage unit DSC(k-1)1, or two adjacent conductive lines M0k1, M0(k+2)1 in the same column can be separated by two data storage units DSCk1, DSC(k+1)1. In some embodiments, the width of one data storage unit DSC can be 260 nanometers, and the height can be 420 nanometers, in which case the spacing between the two conductive lines M0k1, M0(k+2)1 can be 840 nanometers. In some embodiments, at least two adjacent bit lines BL1-BL2n are located between two adjacent and aligned conductive lines M0, for example, two bit lines BL(2k-3), BL(2k-2) are located between two adjacent and aligned conductive lines M0(k-1)1, M0k1, or four bit lines BL(2k-1)-BL(2k+2) are located between two adjacent and aligned conductive lines M0k1, M0(k+2)1. In some embodiments, the two adjacent conductive lines M0 on either side of each of the source lines SL1-SLn are staggered and not aligned with each other, for example, the two adjacent conductive lines M0k1, M0(k+1)2 on either side of the source line SLk are staggered and not aligned with each other. In some embodiments, the conductive lines M0 are perpendicular to or cross the conductive lines M5. In some embodiments, one conductive line M0 that overlaps one conductive line M5 is staggered and not aligned with another conductive line M0 that overlaps another conductive line M5, for example, the conductive line M0k1 that overlaps the word line WL1 is staggered and not aligned with the conductive line M0(k+1)2 that overlaps the word line WL2.

[0032] In some embodiments, multiple word line voltage inputs Pnt can be configured on a word line (e.g., word line WLm), and word line voltages are received (e.g., from control circuitry using multiple word line voltage inputs Pnt). In some embodiments, word line voltage inputs Pnt in the same row constitute a logic region, and data storage cells DSC are absent from the logic region. Multiple bit lines (i.e., multiple data storage cells DSC) are provided between two adjacent logic regions; for example, 64 bit lines can be provided between two adjacent logic regions. The more bit lines between two adjacent logic regions, the smaller the area of ​​memory 20 can be, but the voltage drop of conductive lines M5 may increase. In some embodiments, the word line voltage inputs Pnt on word lines WL1 to WLm are evenly spaced and arranged in an array, meaning that different logic regions are evenly spaced. In some embodiments, word lines WL1 to WLm extend continuously without breaking at the word line voltage inputs Pnt (or logic regions) of word lines WL1 to WLm. In some embodiments, a word line voltage input terminal Pnt is separated from its adjacent conductive lines M0 on both sides by different distances. For example, the word line voltage input terminal Pntk1 is separated from the adjacent conductive line M0(k-1)1 by a distance Dt(k-1) (also referred to as the first distance), and the word line voltage input terminal Pntk1 is separated from the adjacent conductive line M0k1 by a distance Dtk (also referred to as the second distance). The distance Dt(k-1) is not equal to the distance Dtk. In some embodiments, a data storage unit DSC is provided between a word line voltage input terminal Pnt and the conductive line M0 on one side, but no data storage unit DSC is provided between it and the conductive line M0 on the other side.

[0033] Please refer to Figures 4 to 21 , Figures 4 to 21 A schematic diagram illustrating a memory fabrication method according to an embodiment of the present invention is shown. This memory fabrication method can be used to fabricate... Figure 1 The memory 10 shown or Figure 2 The memory 20 shown. Wherein Figure 4 , Figure 10 and Figure 16 This is a top-view illustration, and Figure 5 , Figure 11 and Figure 17 For along Figure 4 , Figure 10 and Figure 16 A schematic diagram of the cross section drawn along section line A-A'. Figure 6 , Figure 12 and Figure 18 For along Figure 4 , Figure 10 and Figure 16 A schematic diagram of the cross-section drawn along line B-B'. Figure 7 , Figure 13 and Figure 19For along Figure 4 , Figure 10 and Figure 16 A schematic diagram of the cross-section drawn along the C-C' section line. Figure 8 , Figure 14 and Figure 20 For along Figure 4 , Figure 10 and Figure 16 A schematic diagram of the cross section drawn along the D-D' section line. Figure 9 , Figure 15 and Figure 21 For along Figure 4 , Figure 10 and Figure 16 A schematic diagram of the cross section drawn along the E-E' section line.

[0034] like Figure 5 As shown, a substrate PW is first provided. In some embodiments, the substrate PW may be, for example, a P-type semiconductor substrate or an N-type semiconductor substrate. In some embodiments, the material of the substrate PW may include, for example, silicon, silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), or other semiconductor materials, or compounds or mixtures thereof, but is not limited thereto. In some embodiments, the substrate PW may be, for example, a semiconductor-on-insulator (SOI). In some embodiments, the substrate PW may include, for example, doped regions (DF) of P-wells (p-wells) or n-wells (n-wells).

[0035] Next, as Figure 5 and Figure 17 As shown, a transistor TT is formed on a substrate PW. Transistor TT is located within the active region of the substrate PW and approximately within the inter-layer dielectric (ILD). A transistor TT may include a gate G, a gate insulating layer (not shown), a source S, and a drain D. The source S and drain D are formed within the doped region DF. Figure 17As shown, the drain D is electrically connected to the memory structure Rt. Between the drain D and the memory structure Rt, there are sequentially included a contact structure CT, a conductive layer M1, a conductive via V1, a conductive layer M2, and a carrier layer W. Furthermore, the memory structure Rt is electrically connected to the conductive layer M4, which serves as a bit line (e.g., bit line BL4), via the conductive via V3. In some embodiments, the memory structure Rt may include a lower electrode, a fixed layer, an insulating layer, a free layer, or an upper electrode, but is not limited thereto.

[0036] like Figure 17 and Figure 20 As shown, the source S is electrically connected to the conductive layer M1 via the contact structure CT, and is also electrically connected to the conductive layer M2, which serves as the source line (e.g., source line SL1), via the conductive layer M1. Figure 20 As shown, the conductive layer M2, which serves as the source line (e.g., source line SL1), and the conductive layer M4, which serves as the bit line (e.g., bit line BL2, BL3), are located in different layers. Therefore, the source line (e.g., source line SL1) and the bit line (e.g., bit line BL2, BL3) are electrically isolated from each other. In some embodiments, the width WDsl of the source line (e.g., source line SL1) and the width WDbl of the bit line (e.g., bit line BL2, BL3) can be adjusted according to different needs. For example, the widths WDsl and WDbl can be increased to make the source line (e.g., source line SL1) overlap with the bit line (e.g., bit line BL2, BL3).

[0037] The gate electrode G forms a gate electrode line (e.g., gate electrode line PL4). In some embodiments, the material of the gate electrode G may include, for example, polysilicon or a metal, but is not limited thereto. In some embodiments, the sidewalls of the gate electrode G may be covered by spacers. Figure 19 As shown, the gate electrode lines (e.g., gate electrode lines PL3, PL4) formed by the gate G are electrically connected to the conductive line M5, which serves as a word line (e.g., word line WL2). Between the gate electrode lines (e.g., gate electrode lines PL3, PL4) and the conductive line M5, there are sequentially included contact structure CT, conductive layer M1, conductive via V1, conductive layer M2, conductive via V2, conductive layer M3, conductive via V3, conductive layer M4, and conductive via V4. Therefore, it can be seen that multiple layers (i.e., contact structure CT, conductive layer M1, conductive via V1, conductive layer M2, conductive via V2, conductive layer M3, conductive via V3, conductive layer M4, and conductive via V4) are disposed between the gate G of transistor TT and the conductive line M5, which serves as a word line (e.g., word line WL2). These layers may cause the potential of the gate G or its corresponding gate electrode lines to differ, such as... Figure 18 and Figure 19As shown, by directly connecting and contacting the gate electrode lines (e.g., gate electrode lines PL3 and PL4) with the conductive line M0, it can be ensured that the gate G corresponding to the gate electrode line PL3 is at the same potential as the gate G corresponding to the gate electrode line PL4. In addition, the conductive line M0 can further avoid signal transmission abnormalities caused by manufacturing defects of the gate electrode lines (e.g., broken or even multiple broken gate electrode lines PL3 or PL4) or the lines connected to the word line voltage input terminal Pnt (e.g., broken conductive via V1 or conductive layer M2). For example, the gate G located on the gate electrode line PL3 cannot change with the word line WL2. This is because even if some gate electrode lines or lines connected to the word line voltage input terminal Pnt are open-circuited, the gate G can be connected to other word line voltage input terminals Pnt through the network formed by the conductive line M0 and receive the word line voltage (e.g., from the control circuit).

[0038] In some embodiments, the conductive lines M0 and the gate electrode lines PL1-PL2m are located on different layers, or are fabricated from different unpatterned material layers by different fabrication processes; in some embodiments, the conductive lines M0 and the gate electrode lines PL1-PL2m are located on the same layer and are fabricated from the same unpatterned material layer by the same fabrication process. In some embodiments, the first thickness TK1 of the gate electrode lines PL1-PL2m is 0.5 to 2 times the second thickness TK2 of the conductive lines M0. In some embodiments, the multiple conductive lines M0 may have different thicknesses, and the gate electrode lines PL1-PL2m may have different thicknesses.

[0039] like Figure 19 As shown, each conductive line M5 is electrically connected to at least one of the gate electrode lines PL1 to PL2m, and no other conductive film layer is disposed between two adjacent conductive lines M5. Figure 19 As shown, the cross-sectional area (or thickness, width) of the conductive line M5, which serves as a word line (e.g., word lines WL2, WL3), can be appropriately increased to reduce its resistance value. The increased cross-sectional area (or thickness, width) reduces the load on the conductive line M5, thereby resulting in a lower voltage drop across the conductive line M5 and reducing power loss. In some embodiments, the first thickness TK1 of the gate electrode line (e.g., gate electrode line PL3) is 0.1 to 0.5 times the second thickness TK3 of the conductive line M5, but is not limited thereto. In some embodiments, the first width WD1 of the gate electrode line (e.g., gate electrode line PL3) is smaller than the second width WD3 of the conductive line M5, but is not limited thereto. In some embodiments, multiple conductive lines M5 may have different thicknesses or widths. Figure 17 As shown, the conductive line M5, which serves as a word line (e.g., word line WL2), and the conductive layer M4, which serves as a bit line (e.g., bit line BL4), are located on different layers, so the word line (e.g., word line WL2) and the bit line (e.g., bit line BL4) are electrically isolated from each other.

[0040] like Figures 17 to 21 As shown, the dielectric layer ILD also includes other inter-metallic dielectric layers IMD1, IMD2, IMD3a, IMD3b, IMD4, and IMD5 stacked on the dielectric layer ILD. Furthermore, conductive layer M1 is located in dielectric layer IMD1, conductive layer M2 and conductive via V1 are located in dielectric layer IMD2, the carrier layer W and the storage structure Rt are located in dielectric layer IMD3a, conductive layer M3 and conductive via V2 are located in dielectric layer IMD3b, conductive layer M4 and conductive via V3 are located in dielectric layer IMD4, and conductive line M5 and conductive via V4 are located in dielectric layer IMD5. Figure 21 As shown, the dielectric layer ILD can be a multi-layer stacked structure, with the conductive line M0 located within the multi-layer stack of dielectric layers ILD. For example, the conductive line M0 is located within dielectric layer ILD2 and sandwiched between dielectric layers ILD1 and ILD3. Figure 21 As shown, both the conductive line M0 and the contact structure CT are located within the dielectric layer ILD, but the conductive line M0 and the contact structure CT are electrically isolated by a gap. Similarly, the conductive line M0 and the conductive layer M1 are located in different layers, and the conductive line M0 and the conductive layer M1 are electrically isolated by a gap. For example, as... Figure 21 As shown, conductive line M0 is separated from conductive layer M1 by a distance through dielectric layer ILD3 and is electrically isolated. Figure 16 As shown, the conductive line M0 does not overlap with the contact structure CT, the metal layer M1, or the source lines (e.g., source lines SL1, SL2). Since the conductive line M0 does not overlap with the conductive layer M1, coupling capacitance is avoided. To further prevent the conductive line M0 from overlapping with the conductive layer M1, the conductive line M0 does not overlap with bit lines BL1 to BL2n, nor is it placed within any data storage unit (DSC).

[0041] like Figure 21 As shown, the center of conductor M0 is aligned with the center of the shallow trench isolation (STI) layer. Figure 19 and Figure 20As shown, the contact structure CT is disposed on the doped region DF or the gate electrode line PL1-PL2m, and the shallow trench isolation layer STI is formed on the substrate PW and located between the doped regions DF. The shallow trench isolation layer STI is used to define and electrically isolate adjacent transistors TT. In some embodiments, the material of the shallow trench isolation layer STI can have a high dielectric constant or be a High-K dielectric, where High-K dielectric refers to a material having a high dielectric constant compared to silicon dioxide, and K can be greater than or equal to 8. In some embodiments, the material of the shallow trench isolation layer STI can have a low dielectric constant or be a Low-K dielectric, where K can be less than or equal to 4. In some embodiments, the material of the shallow trench isolation layer STI can include, for example, a dielectric material such as an oxide (e.g., an oxide of Germanium (Ge), titanium oxide (TiO2), tantalum oxide (Ta2O5), or silicon dioxide (SiO2)), an oxynitride (e.g., an oxynitride of Gallium phosphide (GaP) or silicon oxynitride (SiON)), barium strontium titanate (BST, BaTiO3 / SrTiO3), etc., but is not limited thereto. x O y x O y x O y N z

[0042] ​​​In some embodiments, the materials of the contact structure CT, the conductive layers M1, M2, M3, M4, the conductive vias V1, V2, V3, and the conductive lines M0, M5 can include, but are not limited to, conductive materials such as copper, aluminum copper, aluminum, gold, other metals or alloys, and the like. In some embodiments, the material of the contact structure CT can include, but is not limited to, conductive materials such as nickel silicide (NiSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), erbium silicide (ErSi), cobalt silicide (CoSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), or other silicides, and the like. In some embodiments, the materials of the conductive layers M1-M4 can include, but are not limited to, Single Poly. In some embodiments, the contact structure CT, the conductive layers M1-M4, the conductive vias V1-V3, and the conductive lines M0, M5 can be formed using techniques such as single damascene operation, dual damascene operation, electroplating, low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), sputtering, evaporation, high-density inductively coupled plasma (ICP) deposition, high-density ionized metal plasma (IMP) deposition, and the like, but are not limited thereto.In some embodiments, the carrier layer W can be formed using the material or fabrication technique of the conductive vias V1-V3, but not limited thereto.

[0043] In some embodiments, the material of the dielectric layer ILD can include, for example, dielectric materials such as oxide (e.g., oxide of Germanium (Ge), titanium oxide (Ti x O y ), tantalum oxide (Ta x O y ), or Silicon dioxide (SiO2)), oxynitride (e.g., oxynitride of Gallium phosphide (GaP) or Silicon Oxynitride (Si x O y N z ), barium strontium titanate (BST, BaTiO3 / SrTiO3), etc., but not limited thereto. In some embodiments, the dielectric layer ILD can be formed using, for example, chemical vapor deposition (CVD) such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) such as Sputtering, Evaporation, etc., but not limited thereto. In some embodiments, the material of the dielectric layers IMD1, IMD2, IMD3a, IMD3b, IMD4, IMD5 can have a low dielectric constant or be a low-K dielectric, and K can be less than or equal to 3.8. In some embodiments, the material of the dielectric layers IMD1-IMD5 can include, for example, dielectric materials such as Silicate Glass (USG), Fluorinated Silicate Glass (FSG), etc., but not limited thereto. In some embodiments, the memory fabrication method can moderately employ planarization operations such as Chemical-Mechanical Planarization (CMP) operations, etc.

[0044] It is noted that, Figure 1 the memory 10 or Figure 2The memory 20 shown is an embodiment of the present invention, and those skilled in the art can make different changes and modifications accordingly. For example, please refer to... Figure 22 , Figure 22 This is a partial schematic diagram of the memory 80 according to Embodiment 1 of the present invention. Figure 22 The architecture of the memory 80 shown is similar to Figure 2 The memory 20 shown uses the same symbols for identical components. Unlike... Figure 2 The memory 20 shown, Figure 22 The memory 80 shown has a greater number of conductive lines M0, which are more densely arranged within the memory 80, thus potentially requiring more refined patterning. In some embodiments, conductive lines M0 coupled to adjacent sets of gate electrode lines are aligned and not separated. For example, conductive line M0i1 is coupled to gate electrode lines PL1 and PL2 in one set, and conductive line M0i2 is coupled to gate electrode lines PL3 and PL4 in another adjacent set, with conductive lines M0i1 and M0i2 aligned and not separated. In some embodiments, the conductive lines M0 adjacent to each of the source lines SL1 to SLn are aligned and not separated. For example, the conductive lines M0i1 and M0(i+1)1 adjacent to each other on both sides of the source line SL1 are aligned and not separated. In some embodiments, a conductive line M0 overlapping a conductive line M5 is aligned with another conductive line M0 overlapping another conductive line M5. For example, a conductive line M0i1 overlapping a word line WL1 is aligned with a conductive line M0i2 overlapping a word line WL2.

[0045] In some embodiments, different conductive lines M0 are electrically isolated from each other without being coupled, for example, conductive lines M0i1, M0i2 are electrically isolated from each other without being coupled. In some embodiments, two adjacent conductive lines M0 in the same column can be separated by a column (or multiple columns) of data storage units DSC, for example, two adjacent conductive lines M0i1, M0(i+1)1 in the same column can be separated by data storage unit DSCil, or two adjacent conductive lines M0i1, M0(i+1)1 in the same column can be separated by more than one data storage unit. In some embodiments, at least two adjacent bit lines BL1~BL2n are located between two adjacent and aligned conductive lines M0, for example, bit lines BL(2i-1), BL2i are located between two adjacent and aligned conductive lines M0i1, M0(i+1)1, or more than two bit lines are located between two adjacent and aligned conductive lines M0i1, M0(i+1)1. In some embodiments, one word line voltage input end Pnt is separated from two adjacent conductive lines M0 on its two sides by the same distance, for example, word line voltage input end Pnti1 is separated from adjacent conductive line M0(i-1)1 by distance Dt(i-1), word line voltage input end Pnti1 is separated from adjacent conductive line M0i1 by distance Dti, distance Dt(i-1) is equal to distance Dti. In some embodiments, no data storage unit DSC is arranged between one word line voltage input end Pnt and two adjacent conductive lines M0 on its two sides.

[0046] In addition, please refer to Figure 23 , Figure 23 Figure 1 is a partial schematic diagram of a memory 90 according to an embodiment of the present application. Figure 23 The architecture of the memory 90 shown is similar to that of the memory 20 shown in Figure 2 Therefore, the same elements are denoted by the same reference numerals. Unlike the memory 20 shown in Figure 2 , Figure 23 The distribution of the contact structures CT of the memory 90 shown can be adjusted adaptively corresponding to the conductive lines M0. As shown in Figure 23 The contact structures CT are not all aligned laterally along the rows of the array. For example, when two adjacent contact structures CT are arranged with a conductive line M0 therebetween, the distance between the two adjacent contact structures CT is Dt2, for example, the distance between contact structure CT22 and adjacent contact structure CT32 is Dt2. When two adjacent contact structures CT are arranged without a conductive line M0 therebetween, the distance between the two adjacent contact structures CT is Dt1, for example, the distance between contact structure CT21 and adjacent contact structure CT31 is Dt1. Distance Dt2 is greater than distance Dt1. In this way, it can be ensured that the conductive lines M0 are electrically isolated from the contact structures CT with sufficient spacing.

[0047] In addition, each of the conductive lines M5 completely overlaps two of the gate electrode lines PL1~PL2m, for example, one conductive line M5 can completely overlap the adjacent gate electrode lines PL1, PL2 to completely cover the gate electrode lines PL1, PL2. Unlike the storage device 20 shown in the prior art, the conductive lines M5 do not expose, for example, the left side of the gate electrode line PL1 or the right side of the gate electrode line PL2, and therefore, each of the conductive lines M5 completely overlaps two of the gate electrode lines PL1~PL2m. Figure 2 In addition, each of the conductive lines M5 completely overlaps two of the gate electrode lines PL1~PL2m, for example, one conductive line M5 can completely overlap the adjacent gate electrode lines PL1, PL2 to completely cover the gate electrode lines PL1, PL2. Unlike the storage device 20 shown in the prior art, the conductive lines M5 do not expose, for example, the left side of the gate electrode line PL1 or the right side of the gate electrode line PL2, and therefore, each of the conductive lines M5 completely overlaps two of the gate electrode lines PL1~PL2m.

[0048] In summary, the present application optimizes the configuration design of the word line. The present application reduces the resistance value of the word line by increasing the cross-sectional area of the word line to reduce the line load. In addition, the present application directly connects the conductive line to the gate electrode line, so that even if multiple film layers are provided between the gate of the transistor and the word line, the equipotential between the gates can be ensured. Furthermore, the present application directly connects the conductive line to the gate electrode line, which can further avoid signal transmission abnormalities caused by manufacturing process defects of the gate electrode line.

[0049] The above description is only the preferred embodiment of the present application, and any equivalent changes and modifications made according to the claims of the present application shall be within the scope of the present application.

Claims

1. A memory fabrication method, comprising: The memory manufacturing method comprises: forming a plurality of gate electrode lines to form gates of a plurality of data storage units respectively, wherein the plurality of data storage units are arranged in an array; and forming a plurality of conductive lines, wherein each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines, each of the plurality of conductive lines at least partially overlaps the two of the plurality of gate electrode lines, wherein the plurality of conductive lines comprises a plurality of first conductive lines and a plurality of second conductive lines, the plurality of first conductive lines is perpendicular to the plurality of second conductive lines, a first conductive line of the plurality of first conductive lines that overlaps one of the plurality of second conductive lines is staggered and misaligned to another first conductive line of the plurality of first conductive lines that overlaps another of the plurality of second conductive lines.

2. The memory fabrication method of claim 1, wherein, The memory manufacturing method further comprises: forming a plurality of bit lines, wherein the plurality of bit lines is parallel to the plurality of first conductive lines, at least four of the plurality of bit lines that are adjacent to each other are located between two of the plurality of first conductive lines that are adjacent and aligned.

3. The memory fabrication method of claim 1, wherein, The memory manufacturing method further comprises: forming a plurality of source lines, wherein the plurality of source lines is parallel to the plurality of first conductive lines, two of the plurality of first conductive lines that are adjacent to each other on two sides of each of the plurality of source lines are staggered and misaligned to each other.

4. The memory fabrication method of claim 1, wherein, Each of the plurality of first conductive lines is electrically connected to and contacts two of the plurality of gate electrode lines.

5. The memory fabrication method of claim 1, wherein, A first thickness of each of the plurality of gate electrode lines is 0.5 times to 2 times a second thickness of each of the plurality of first conductive lines, a first width of each of the plurality of gate electrode lines is 0.5 times to 1 times a second width of each of the plurality of first conductive lines, the first width of each of the plurality of gate electrode lines is 0.1 times to 0.2 times a length of each of the plurality of first conductive lines.

6. The memory fabrication method of claim 1, wherein, The plurality of second conductive lines are word lines respectively, the plurality of second conductive lines is parallel to the plurality of gate electrode lines.

7. The memory fabrication method of claim 1, wherein, A second spacing between two adjacent of the plurality of second conductive lines is greater than or equal to twice a first spacing between two adjacent of the plurality of gate electrode lines, a gap width between the two adjacent of the plurality of gate electrode lines is less than or equal to a second width of each of the plurality of second conductive lines.

8. The memory fabrication method of claim 1, wherein, A first thickness of each of the plurality of gate electrode lines is 0.1 times to 0.5 times a second thickness of each of the plurality of second conductive lines, a first width of each of the plurality of gate electrode lines is 0.2 times to 0.5 times a second width of each of the plurality of second conductive lines.

9. The memory fabrication method of claim 1, wherein, Each of the plurality of second conductive lines completely overlaps the two of the plurality of gate electrode lines.

10. A memory, comprising: The memory comprises: a plurality of data storage units arranged in an array, wherein gates of the plurality of data storage units form a plurality of gate electrode lines respectively; and a plurality of conductive lines, wherein each of the plurality of conductive lines is coupled to two of the plurality of gate electrode lines, each of the plurality of conductive lines at least partially overlaps the two of the plurality of gate electrode lines, wherein the plurality of conductive lines comprises a plurality of first conductive lines and a plurality of second conductive lines, the plurality of first conductive lines is perpendicular to the plurality of second conductive lines, a first conductive line of the plurality of first conductive lines that overlaps one of the plurality of second conductive lines is staggered and misaligned to another first conductive line of the plurality of first conductive lines that overlaps another of the plurality of second conductive lines.

11. The memory of claim 10, wherein, The memory further comprises: a plurality of bit lines, wherein the plurality of bit lines is parallel to the plurality of first conductive lines, at least four adjacent bit lines of the plurality of bit lines are located between two adjacent and aligned first conductive lines of the plurality of first conductive lines.

12. The memory of claim 10, wherein, The memory further comprises: a plurality of source lines, wherein the plurality of source lines is parallel to the plurality of first conductive lines, two adjacent first conductive lines on two sides of each of the plurality of source lines are staggered and misaligned to each other.

13. The memory of claim 10, wherein, Each of the plurality of first conductive lines is electrically connected to and contacts two of the plurality of gate electrode lines.

14. The memory of claim 10, wherein, A first thickness of each of the plurality of gate electrode lines is 0.5 times to 2 times a second thickness of each of the plurality of first conductive lines, a first width of each of the plurality of gate electrode lines is 0.5 times to 1 times a second width of each of the plurality of first conductive lines, the first width of each of the plurality of gate electrode lines is 0.1 times to 0.2 times a length of each of the plurality of first conductive lines.

15. The memory of claim 10, wherein, The plurality of second conductive lines are word lines respectively, the plurality of second conductive lines is parallel to the plurality of gate electrode lines.

16. The memory of claim 10, wherein, A second spacing between two adjacent ones of the plurality of second conductive lines is greater than or equal to twice a first spacing between two adjacent ones of the plurality of gate electrode lines, a gap width between the two adjacent ones of the plurality of gate electrode lines is less than or equal to a second width of each of the plurality of second conductive lines.

17. The memory of claim 10, wherein, A first thickness of each of the plurality of gate electrode lines is 0.1 times to 0.5 times a second thickness of each of the plurality of second conductive lines, a first width of each of the plurality of gate electrode lines is 0.2 times to 0.5 times a second width of each of the plurality of second conductive lines.

18. The memory of claim 10, wherein, Each of the plurality of second conductive lines completely overlaps the two of the plurality of gate electrode lines.

19. A data storage unit, characterized by The data storage unit comprises: a storage structure, wherein a first end of the storage structure is electrically connected to a bit line; a first transistor comprising a first gate, a first drain and a first source; a second transistor comprising a second gate, a second drain and a second source, wherein the first gate is electrically connected to the second gate, a second end of the storage structure is electrically connected to the first drain and the second drain, the first source and the second source are electrically connected to a source line, a first resistor, wherein a first end of the first resistor is electrically connected to the first gate and the second gate; and a second resistor, wherein a second end of the second resistor is electrically connected to the first drain and the second drain. a second resistor, wherein a first end of the second resistor is electrically connected to the first gate and the second gate, and a second end of the first resistor and a second end of the second resistor are electrically connected to a word line voltage input terminal via a second conductive line.

20. The data storage unit of claim 19, wherein, The first gate is electrically connected to the second gate via a first conductive line.

21. The data storage unit of claim 19, wherein, The first gate and the second gate substantially have the same electric potential, and a first electric potential difference between the first gate and a word line voltage input terminal is equal to a second electric potential difference between the second gate and the word line voltage input terminal.

22. The data storage unit of claim 19, wherein, The first gate and the second gate are coupled to the same word line.

23. The data storage unit of claim 19, wherein, The storage structure is a variable resistor to define an internal data state, wherein a resistance value of the storage structure changes according to an applied voltage or current.

24. The data storage unit of claim 19, wherein, A resistance value of the second conductive line can be between 10 ohms and 1280 ohms.

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