Delay-locked loop circuit

Abstract

The application relates to a delay-locked loop circuit, comprising: a variable delay line for delaying an initial clock signal to generate a delayed clock signal; a control circuit connected with the variable delay line, for controlling the variable delay line to perform delay adjustment in a first mode, and for controlling the variable delay line to perform delay adjustment in a second mode when the delayed clock signal meets a preset condition; wherein the step value of each delay adjustment in the first mode is a first step value, the step value of each delay adjustment in the second mode is a second step value, and the second step value is greater than the first step value. By judging whether the delayed clock signal meets the preset condition, the actual state of the delayed clock signal can be obtained, different strategies are adopted to adjust the delay of the variable delay line, so that the output of the delay-locked loop circuit can dynamically and adaptively track the timing change of the delayed clock signal, and the matching degree between the initial clock signal CK and the drifted DQS signal is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and in particular to a delay-locked loop circuit. BACKGROUND

[0002] With the continuous development of science and technology, double data rate (DDR) dynamic random access memory (DRAM) is widely used in various electronic devices, such as computers, mobile phones, tablet computers, etc. When the dynamic random memory performs data read and write operations, it needs to rely on the DQS signal to realize the signal synchronization between the memory and the controller. Specifically, if data is read from the memory, the controller determines when to receive the read data according to the DQS signal sent by the memory.

[0003] In order to realize accurate reading of data, the clock signal of the controller and the DQS signal need to be aligned at the rising edge to ensure correct data. However, during the memory operation, the voltage of the memory changes due to current changes and other reasons, and the phase of the DQS signal also drifts with the voltage fluctuation, resulting in a mismatch between the clock signal and the drifted DQS signal, which causes data reading errors and affects the operation reliability of the memory. SUMMARY

[0004] Therefore, it is necessary to provide a delay-locked loop circuit to solve the problem of phase mismatch between the clock signal and the drifted DQS signal.

[0005] A delay-locked loop circuit comprises:

[0006] a variable delay line configured to delay an initial clock signal to generate a delayed clock signal;

[0007] a control circuit connected to the variable delay line, configured to control the variable delay line to perform delay adjustment in a first mode, and further configured to control the variable delay line to perform delay adjustment in a second mode when the delayed clock signal meets a preset condition;

[0008] wherein a step value of each delay adjustment in the first mode is a first step value, and a step value of each delay adjustment in the second mode is a second step value, the second step value being greater than the first step value.

[0009] In one embodiment, the control circuit comprises:

[0010] a path replication module configured to receive the delayed clock signal and delay the delayed clock signal by a preset time to generate a feedback clock signal;

[0011] a phase detection module configured to detect a phase difference between the feedback clock signal and the initial clock signal, and generate a normal detection signal according to the phase difference;

[0012] a first control module connected to the phase detection module, configured to generate a first code group according to the normal detection signal, the first code group being used to adjust the delay of the variable delay line, and a least significant bit of the first code group corresponding to a step value of delay adjustment being the first step value.

[0013] In one of the embodiments, the control circuit further comprises:

[0014] a phase abnormality detection module configured to detect a phase difference between the feedback clock signal and the initial clock signal, and generate an abnormality detection signal according to the phase difference;

[0015] a second control module connected to the phase abnormality detection module, configured to generate a second code group according to the abnormality detection signal, the second code group being used to adjust the delay of the variable delay line, and a least significant bit of the second code group corresponding to a step value of delay adjustment being the second step value.

[0016] In one of the embodiments, the phase abnormality detection module is configured to determine that the delay clock signal meets the preset condition and switch the abnormality detection signal to a first state when the phase difference between the feedback clock signal and the initial clock signal is greater than or equal to a phase difference threshold, the abnormality detection signal in the first state being used to control the second code group to be valid.

[0017] In one of the embodiments, the phase abnormality detection module is further configured to determine that the delay clock signal does not meet the preset condition and switch the abnormality detection signal to a second state when the phase difference between the feedback clock signal and the initial clock signal is less than or equal to the phase difference threshold, the abnormality detection signal in the second state being used to control the second code group to be invalid.

[0018] In one of the embodiments, the phase abnormality detection module comprises:

[0019] a forward abnormality detection unit configured to generate a forward detection signal according to the feedback clock signal, a phase difference threshold signal and the initial clock signal;

[0020] a backward abnormality detection unit configured to generate a backward detection signal according to the feedback clock signal, a reversed signal of the phase difference threshold signal and the initial clock signal;

[0021] an operation unit configured to generate the abnormality detection signal according to the forward detection signal and the backward detection signal.

[0022] In one of the embodiments, the phase abnormality detection module is further configured to determine an abnormality level of the phase difference;

[0023] The second control module is further configured to receive the abnormality level and adjust the second step value according to the abnormality level.

[0024] In one of the embodiments, the phase abnormality detection module further comprises a threshold adjustment unit configured to update the phase difference threshold according to the abnormality detection signal;

[0025] The phase abnormality detection module is configured to determine the abnormality level of the phase difference by updating the phase difference threshold.

[0026] In one of the embodiments, the forward abnormality detection unit comprises:

[0027] A positive delay circuit configured to generate a first detection signal according to the feedback clock signal and the phase difference threshold signal;

[0028] A reference delay circuit configured to generate a reference detection signal according to the initial clock signal;

[0029] A forward phase detector connected with the positive delay circuit and the reference delay circuit respectively, and configured to generate the forward detection signal according to the first detection signal and the reference detection signal.

[0030] In one of the embodiments, the positive delay circuit comprises:

[0031] A first delay circuit comprising a plurality of first inverters connected in parallel, an input end of the first inverter being configured to receive the feedback clock signal, and the first inverter being configured to invert the input signal under the control of the phase difference threshold;

[0032] A second delay circuit comprising:

[0033] A fixed time chain configured to receive the feedback clock signal and perform a preset delay on the feedback clock signal to generate a delayed feedback signal;

[0034] A plurality of second inverters connected in parallel, an input end of the second inverter being configured to receive the delayed feedback signal, and the second inverter being configured to invert the input signal under the control of the phase difference threshold;

[0035] The outputs of the first delay circuit and the second delay circuit jointly constitute the first detection signal.

[0036] The delay-locked loop circuit comprises a variable delay line configured to delay an initial clock signal to generate a delayed clock signal; and a control circuit connected to the variable delay line, configured to control the variable delay line to perform a first mode of delay adjustment, and further configured to control the variable delay line to perform a second mode of delay adjustment when the delayed clock signal meets a preset condition; wherein the first mode of delay adjustment has a first step value, and the second mode of delay adjustment has a second step value, and the second step value is greater than the first step value. By judging whether the delayed clock signal meets the preset condition, the actual state of the delayed clock signal can be obtained, and different strategies of delay adjustment of the variable delay line can be performed, i.e., delay adjustment with different step values is performed, so that the output of the delay-locked loop circuit can dynamically and adaptively track the timing change of the delayed clock signal, and thus more rapid and flexible timing adjustment of the delayed clock signal is realized, the matching degree between the initial clock signal CK and the drifted DQS signal is improved, and the problem of data reading error is effectively avoided. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 Structure diagram of a delay-locked loop circuit according to an embodiment;

[0038] Figure 2 Timing diagram of a second phase difference threshold according to an embodiment;

[0039] Figure 3 Timing diagram of a third phase difference threshold according to an embodiment;

[0040] Figure 4 State machine of an abnormality level according to an embodiment;

[0041] Figure 5 Structure diagram of a phase abnormality detection module according to an embodiment;

[0042] Figure 6 Structure diagram of a positive delay circuit according to an embodiment;

[0043] Figure 7 Simulation diagram of voltage fluctuation according to an embodiment;

[0044] Figure 8 Simulation diagram of phase difference during voltage fluctuation according to an embodiment. Figure 7 Simulation diagram of phase difference during voltage fluctuation according to an embodiment.

[0045] Element number description:

[0046] Variable delay line: 100; Control circuit: 200; Path duplication module: 210; Phase detection module: 220; First control module: 230; Phase anomaly detection module: 240; Positive anomaly detection unit: 241; Negative anomaly detection unit: 242; Operation unit: 243; Positive delay circuit: 244; First delay circuit: 2441; Second delay circuit: 2442; Reference delay circuit: 245; Positive phase detector: 246; Negative delay circuit: 247; Negative phase detector: 248; Second control module: 250 DETAILED DESCRIPTION

[0047] For the purpose of promoting an understanding of the application, the application will now be described in greater detail with reference to the drawings. In the drawings, preferred embodiments of the application are depicted. The application may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] In the description of the application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", and the like, are intended to indicate the orientation or positional relationship as shown in the drawings, and are only for the purpose of facilitating the description of the application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be understood as limiting the application.

[0050] Figure 1 For an embodiment of the structure of the delay-locked loop circuit, reference is made to Figure 1 In this embodiment, the delay-locked loop circuit includes a variable delay line 100 and a control circuit 200.

[0051] The variable delay line 100 is used to delay the initial clock signal CK to generate a delayed clock signal.

[0052] The variable delay line 100 refers to a circuit that adjusts the phase of an input signal in steps and outputs the adjusted signal. Specifically, adjusting in steps refers to adjusting the input signal by one step value each time to generate an output signal, where the step value is the minimum adjustment unit. In this embodiment, the variable delay line 100 is used to delay the initial clock signal CK, i.e., the phase difference between the delayed clock signal and the initial clock signal CK is the aforementioned step value.

[0053] It can be understood that when the memory reads data, the rising edge of the initial clock signal CK needs to be aligned with the rising edge of the DQS signal, so as to achieve accurate reading of data, where the timing of the DQS signal corresponds to the timing of the delayed clock signal. However, the DQS signal may drift due to voltage changes, for example, the drift may change the period length of the DQS signal, or change the duty cycle of the DQS signal, etc., thereby causing the rising edge of the DQS signal to change, and further causing the rising edge of the initial clock signal CK to be misaligned with the rising edge of the DQS signal, resulting in data reading errors of the memory. In this embodiment, by adjusting the delay length of the variable delay line 100, the phase of the delayed clock signal can be changed, so that the rising edge of the initial clock signal CK is aligned with the rising edge of the DQS signal, thereby improving timing reliability.

[0054] The control circuit 200 is connected with the variable delay line 100, and is configured to control the variable delay line 100 to perform delay adjustment in a first mode, and is further configured to control the variable delay line 100 to perform delay adjustment in a second mode when the delayed clock signal meets a preset condition; where the step value of each delay adjustment in the first mode is a first step value, and the step value of each delay adjustment in the second mode is a second step value, and the second step value is greater than the first step value.

[0055] It can be understood that a larger step value can achieve faster adjustment of the signal, but if the phase error of the signal is small, adjusting the signal by a larger step value may easily cause the signal to become unstable. Therefore, a proper step value needs to be selected according to the actual state of the signal to achieve more accurate adjustment.

[0056] Specifically, the preset condition satisfied by the delayed clock signal can refer to a timing relationship between the delayed clock signal and the initial clock signal CK satisfying a set condition. For example, the set condition can be that a time difference between a rising edge of the delayed clock signal and a rising edge of the initial clock signal CK is greater than a threshold range, or a difference between a period of the delayed clock signal and a period of the initial clock signal CK is greater than a threshold range, or a difference between a duty cycle of the delayed clock signal and a duty cycle of the initial clock signal CK is greater than a threshold range. It should be noted that the above examples are only used for illustration and do not limit the protection scope of the present application. Other parameters that can reflect the timing relationship between the delayed clock signal and the initial clock signal CK also belong to the protection scope of the present application. In the embodiment, by setting the preset condition of the delayed clock signal, the delay of the variable delay line 100 can be accurately adjusted based on the state of the delayed clock signal, thereby improving the delay precision of the delay-locked loop circuit and achieving more accurate and faster matching between the DQS signal and the initial clock signal CK.

[0057] In the embodiment, the delay-locked loop circuit comprises: a variable delay line 100 configured to delay an initial clock signal CK to generate a delayed clock signal; and a control circuit 200 connected to the variable delay line 100 and configured to control the variable delay line 100 to perform delay adjustment in a first mode and to perform delay adjustment in a second mode when the delayed clock signal satisfies a preset condition. The first mode has a first step value for each delay adjustment, and the second mode has a second step value for each delay adjustment, the second step value being greater than the first step value. By judging whether the delayed clock signal satisfies the preset condition, the actual state of the delayed clock signal can be obtained to adjust the delay of the variable delay line 100 in different strategies, i.e., to perform delay adjustment with different step values, so that the output of the delay-locked loop circuit can dynamically and adaptively track the timing change of the delayed clock signal, thereby achieving more rapid and flexible timing adjustment of the delayed clock signal, improving the matching degree between the initial clock signal CK and the drifted DQS signal, and effectively avoiding the problem of data read error.

[0058] Further, the first step value and the second step value are directly related to the working rate of the memory. Still further, the first step value and the second step value are inversely related to the working rate of the memory, i.e., the faster the working rate of the memory, the smaller the first step value and the second step value. For example, the data transmission rate of LPDDR4 is 3200Mbps, while the data transmission rate of LPDDR4X is 4.266Gbps, then the first step value for LPDDR4X is correspondingly smaller than the first step value for LPDDR4, and the second step value for LPDDR4X is correspondingly also smaller than the second step value for LPDDR4. It can also be said that the first step value and the second step value are positively related to the period of the DQS signal to be matched, and exemplarily, if the period of the DQS signal of LPDDR4 is T1, and the period of the DQS signal of LPDDR4X is T2, then the ratio between the first step value for LPDDR4 and the first step value for LPDDR4X can be T1 / T2, so that the delay of the variable delay line 100 is properly adjusted to align the rising edge of the initial clock signal CK with the rising edge of the DQS signal.

[0059] In one of the embodiments, the control circuit 200 comprises a path replication module 210, a phase detection module 220 and a first control module 230.

[0060] The path replication module 210 is configured to receive the delayed clock signal and delay the delayed clock signal by a preset time to generate a feedback clock signal CKFB.

[0061] Specifically, the path replication module 210 is connected to the output end of the variable delay line 100, and the path replication module 210 is configured with a preset path length, which is the same as the path length from the output end of the variable delay line 100 to the DQS / DQ pad, and the preset path length is directly proportional to the preset time, and the ratio of the two is the transmission speed of the signal on the preset path. The path replication module 210 is configured to receive the delayed clock signal and generate the feedback clock signal CKFB according to the delayed clock signal and the preset path length, i.e., to delay the delayed clock signal by a preset time to generate the feedback clock signal CKFB. It can be understood that since the delayed clock signal corresponds to the DQS signal, and the path replication module 210 can accurately match the time of the variable delay line 100 to the DQS / DQ pad, the feedback clock signal CKFB can accurately feedback the timing of the DQS signal, and thus the timing relationship between the initial clock signal CK and the DQS signal can be obtained by comparing the timing relationship between the initial clock signal CK and the feedback clock signal CKFB.

[0062] The phase detection module 220 is connected with the path replication module 210, and is configured to detect a phase difference between the feedback clock signal CKFB and the initial clock signal CK, and generate a normal detection signal according to the phase difference.

[0063] The first control module 230 is connected with the phase detection module 220, and is configured to generate a first encoding group according to the normal detection signal, the first encoding group being used to adjust the delay of the variable delay line 100, and the least significant bit of the first encoding group corresponding to a step value of the delay adjustment being a first step value.

[0064] In the embodiment, the variable delay line 100 can include a plurality of delay units, each of which is configured to generate a delay of a set step length, the first encoding group includes a plurality of control encoding bits, and each of the control encoding bits corresponds to one of the delay units. For example, the variable delay line 100 includes eight delay units, the first encoding group includes eight control encoding bits, when the value of the first encoding group is 10000000, the first delay unit is controlled to be turned on and the other delay units are controlled to be turned off, so as to generate a delay of a set step length; when the value of the first encoding group is 10000001, the first delay unit and the eighth delay unit are controlled to be turned on and the other delay units are controlled to be turned off, so as to generate a delay of two set step lengths. Therefore, the variable delay line 100 can be controlled by changing the value of the first encoding group. It should be noted that the above examples are only used for illustration, and are not used for specific limitation of the variable delay line 100 and the first encoding group.

[0065] Specifically, the normal detection signal generated by the phase detection module 220 is used to instruct the first control module 230 to generate the first encoding group, and the first encoding group is used to adjust the delay of the variable delay line 100 correspondingly. For example, when the normal detection signal is at a high level, it indicates that the phase difference between the feedback clock signal CKFB and the initial clock signal CK exceeds the phase difference threshold of the phase detection module 220, and the timing of the delay clock signal needs to be adjusted so as to reduce the phase difference between the feedback clock signal CKFB and the initial clock signal CK. After the first control module 230 receives the normal detection signal at the high level, the value of the first encoding group is adjusted, so as to change the delay duration of the variable delay line 100. When the normal detection signal is at a low level, it indicates that the phase difference between the feedback clock signal CKFB and the initial clock signal CK is less than the phase difference threshold of the phase detection module 220, and the timing of the delay clock signal does not need to be adjusted. After the first control module 230 receives the normal detection signal at the low level, the value of the first encoding group is maintained unchanged, so as to maintain the timing state of the delay clock signal.

[0066] In one of the embodiments, the above description is continued with reference to Figure 1The control circuit 200 further comprises a phase abnormality detection module 240 and a second control module 250.

[0067] The phase abnormality detection module 240 is connected with the path duplication module 210 and is configured to detect a phase difference between the feedback clock signal CKFB and the initial clock signal CK and generate an abnormality detection signal PE according to the phase difference.

[0068] The second control module 250 is connected with the phase abnormality detection module 240 and is configured to generate a second encoding group according to the abnormality detection signal PE, the second encoding group being used to adjust the delay of the variable delay line 100, and the least significant bit of the second encoding group corresponding to a step value of the delay adjustment being a second step value.

[0069] It can be understood that when the memory is normally operated, the external disturbance factors such as temperature have a small influence on the timing of the DQS signal, and thus the adjustment of only the first step value can align the rising edge of the initial clock signal CK with the rising edge of the DQS signal. However, when the voltage of the memory changes, the DQS signal will be greatly affected, so that the timing of the rising edge of the DQS signal abnormally changes. The phase abnormality detection module 240 is configured to detect the abnormal change, and when the abnormal change occurs, the second control module 250 controls the delay of the variable delay line 100 to be adjusted by the second step value through the abnormality detection signal PE, so as to quickly correct the abnormal DQS signal.

[0070] Specifically, the phase abnormality detection module 240 is configured to determine that the delay clock signal satisfies a preset condition when the phase difference between the feedback clock signal CKFB and the initial clock signal CK is greater than or equal to a phase difference threshold, and switch the abnormality detection signal PE to a first state, the abnormality detection signal PE in the first state being used to control the second encoding group to be valid. The first state can be a high level, and when the second encoding group is valid, the delay of the variable delay line 100 can be controlled to be adjusted by the second step value. The phase abnormality detection module 240 is further configured to determine that the delay clock signal does not satisfy the preset condition when the phase difference between the feedback clock signal CKFB and the initial clock signal CK is less than or equal to the phase difference threshold, and switch the abnormality detection signal PE to a second state, the abnormality detection signal PE in the second state being used to control the second encoding group to be invalid. The second state can be a low level.

[0071] In one of the embodiments, the phase abnormality detection module 240 is further configured to determine an abnormality level of the phase difference, and the second control module 250 is further configured to receive the abnormality level and adjust the second step value according to the abnormality level. The abnormality level is determined by the phase difference between the initial clock signal CK and the feedback clock signal CKFB, and specifically, the abnormality level is determined by the range of the phase difference threshold value in which the phase difference between the initial clock signal CK and the feedback clock signal CKFB falls. For example, the abnormality level can include four levels, i.e., the abnormality levels are 0 to 3, and the phase difference corresponding to the abnormality level 0 to the abnormality level 3 increases in turn, and the first phase difference threshold value td0, the second phase difference threshold value td1, the third phase difference threshold value td2 and the fourth phase difference threshold value td3 are set respectively, and the relationship between the plurality of phase difference threshold values is td0 < td1 < td2 < td3. For example, if the phase difference is between the first phase difference threshold value td0 and the second phase difference threshold value td1, it can be determined that the abnormality level is 0, if the phase difference is between the first phase difference threshold value td1 and the second phase difference threshold value td2, it can be determined that the abnormality level is 1, if the phase difference is between the second phase difference threshold value td2 and the third phase difference threshold value td3, it can be determined that the abnormality level is 2, and if the phase difference is greater than the third phase difference threshold value td3, it can be determined that the abnormality level is 3.

[0072] Figure 2 a timing diagram of the second phase difference threshold value of one embodiment, Figure 3 a timing diagram of the third phase difference threshold value of one embodiment, referring to Figure 2 When the rising edge time of the feedback clock signal CKFB is within the range of + / - td1 of the rising edge time of the initial clock signal CK, it indicates that the phase difference between the feedback clock signal CKFB and the initial clock signal CK is less than or equal to the second phase difference threshold value td1, and the abnormality detection signal PE outputs the second state, i.e., low level, and the delay of the variable delay line 100 does not need to be adjusted. When the rising edge time of the feedback clock signal CKFB is outside the range of + / - td1 of the rising edge time of the initial clock signal CK, it indicates that the phase difference between the feedback clock signal CKFB and the initial clock signal CK is greater than the second phase difference threshold value td1, and the abnormality detection signal PE outputs the first state, i.e., high level, and the delay of the variable delay line 100 needs to be adjusted. In combination with Figure 2 and Figure 3 When the phase difference threshold value increases, the error window of the feedback clock signal CKFB becomes larger, i.e., a larger phase error can be corresponded, and thus the delay of the variable delay line 100 can be adjusted by a larger step value. In the present embodiment, by setting a plurality of phase difference threshold values, the phase difference is divided into abnormality levels, and the second step value is adjusted according to the divided abnormality level, and thus more flexible delay adjustment can be realized, and the adjustment accuracy and speed of the delay-locked loop circuit are improved.

[0073] In one embodiment, the phase abnormality detection module 240 further comprises a threshold adjusting unit, which is configured to update the phase difference threshold according to the abnormality detection signal PE, and the phase abnormality detection module 240 is configured to determine the abnormality level of the abnormal phase difference by updating the phase difference threshold. Figure 4 For the abnormality level state machine of one embodiment, refer to Figure 4 The state machine adjusts the abnormality level according to the current abnormality level and the state of the abnormality detection signal PE, for example, if the current abnormality level is 2 and the phase difference between the feedback clock signal CKFB and the initial clock signal CK is less than the phase difference threshold td2, i.e. the rising edge of the feedback clock signal CKFB is within the error window of the rising edge of the initial clock signal CK, it indicates that the error window can be further reduced to determine whether the abnormality level can be reduced to 1 or 0. The present embodiment can more accurately adjust the second step value by real-time tracking of the abnormality level, so as to match the phase difference with the second step value, and realize more accurate delay adjustment.

[0074] Figure 5 For the structure diagram of the phase abnormality detection module 240 of one embodiment, refer to Figure 5 In the present embodiment, the phase abnormality detection module 240 comprises a positive abnormality detection unit 241, a negative abnormality detection unit 242 and an operation unit 243. The positive abnormality detection unit 241 is configured to generate a positive detection signal according to the feedback clock signal CKFB, the phase difference threshold signal and the initial clock signal CK; the negative abnormality detection unit 242 is configured to generate a negative detection signal according to the feedback clock signal CKFB, the inverse signal of the phase difference threshold signal and the initial clock signal CK; and the operation unit 243 is configured to generate the abnormality detection signal PE according to the positive detection signal and the negative detection signal.

[0075] The positive abnormality detection unit 241 is configured to detect whether the rising edge of the feedback clock signal CKFB leads the rising edge of the initial clock signal CK and whether the leading amount is greater than the phase difference threshold, and outputs a high-level positive detection signal when the leading amount of the feedback clock signal CKFB is greater than the phase difference threshold. The negative abnormality detection unit 242 is configured to detect whether the rising edge of the feedback clock signal CKFB lags behind the rising edge of the initial clock signal CK and whether the lagging amount is greater than the phase difference threshold, and outputs a high-level negative detection signal when the lagging amount of the feedback clock signal CKFB is greater than the phase difference threshold. The operation unit 243 is configured to generate the abnormality detection signal PE according to the positive detection signal and the negative detection signal, and the operation unit 243 can be a logic gate circuit, for example, an or gate, i.e. when at least one of the positive detection signal and the negative detection signal is high, the abnormality detection signal PE output by the operation unit 243 is high.

[0076] In one embodiment, continuing to refer to Figure 5 , the positive abnormality detection unit 241 comprises a positive delay circuit 244, a reference delay circuit 245, and a positive phase discriminator 246. The positive delay circuit 244 is configured to generate a first detection signal according to the feedback clock signal CKFB and the phase difference threshold signal; the reference delay circuit 245 is configured to generate a reference detection signal according to the initial clock signal CK; and the positive phase discriminator 246 is connected with the positive delay circuit 244 and the reference delay circuit 245 respectively, and is configured to generate a positive detection signal according to the first detection signal and the reference detection signal.

[0077] The phase difference threshold signal is a signal corresponding to the phase difference threshold. For example, the phase difference threshold signal can comprise a plurality of threshold control bits, which can be used together to generate a delay duration, and the generated delay duration is equal to the phase difference threshold. Specifically, the first detection signal is a signal generated by delaying the feedback clock signal CKFB by the phase difference threshold. Compared with the processing method of first obtaining the phase difference and then determining the abnormality level, the generation method of the first detection signal in this embodiment can be easily adjusted for different phase difference thresholds, and has higher flexibility and operability. By comparing the phase matching between the first detection signal and the reference detection signal, the phase difference between the feedback clock signal CKFB and the initial clock signal CK, and the abnormality level corresponding to the phase difference can be accurately obtained.

[0078] Further, the negative abnormality detection unit 242 shares the reference delay circuit 245 with the positive abnormality detection unit 241, and additionally comprises a negative delay circuit 247 and a negative phase discriminator 248. The detection method of the negative abnormality detection unit 242 is similar to that of the positive abnormality detection unit 241, which will not be described here.

[0079] Figure 6 The structure diagram of the positive delay circuit 244 of one embodiment is shown in FIG. 4, and the reference Figure 6 In this embodiment, the positive delay circuit 244 comprises a first delay circuit 2441 and a second delay circuit 2442.

[0080] The first delay circuit 2441 comprises a plurality of first inverters connected in parallel. The input end of the first inverter is configured to receive the feedback clock signal CKFB, and the first inverter is configured to invert the input signal under the control of the phase difference threshold. The phase difference threshold signal comprises a plurality of threshold control bits, and is in one-to-one correspondence with the phase difference threshold.

[0081] Table 1 phase difference threshold signal-phase difference threshold truth table

[0082]

[0083]

[0084] Table 1 is a truth table of phase difference threshold signal and phase difference threshold. Referring to Table 1, in this embodiment, the phase difference threshold signal includes 4 threshold control bits, each corresponding to sel<3:0>, and selb<3:0> is the inverse of sel<3:0>. For example, if the phase difference threshold signal is 0101, then sel0=1, sel1=0, sel2=1, sel3=0, selb0=0, selb1=1, selb2=0, selb3=1. sel<3:0> and selb<3:0> are input to the first inverter in pairs, thereby acting as enable signals to control the output of each first inverter.

[0085] The second delay circuit 2442 includes a fixed delay chain and multiple second inverters. The fixed delay chain receives the feedback clock signal CKFB and applies a preset delay to CKFB to generate a delayed feedback signal. In this embodiment, the fixed delay chain includes four buffers. The input terminals of the multiple parallel second inverters receive the delayed feedback signal. The second inverters invert the input signal under the control of a phase difference threshold. The input method of the enable signal of the second inverter is similar to that of the first inverter, and will not be described again here. The outputs of the first delay circuit 2441 and the second delay circuit 2442 together constitute the first detection signal, that is, the first detection signal is generated based on the feedback clock signal CKFB and the phase difference threshold signal.

[0086] Figure 7 This is a simulation diagram of voltage fluctuations in one embodiment. Figure 8 for Figure 7 The simulation diagram of phase difference during voltage fluctuations in the embodiment is shown in the figure. Figure 8 In the diagram, the dashed line represents the phase difference curve of the delay-locked loop circuit without the embodiment of this application, while the solid line represents the phase difference curve of the delay-locked loop circuit with the embodiment of this application. (Reference) Figure 7 to Figure 8 To verify the performance of the delay-locked loop circuit, an application of a voltage such as... Figure 7 The 60mV voltage ramp signal shown is used to simulate voltage fluctuations, and the delay-locked loop circuit is opened and closed to check for changes in the signal's phase error. Figure 8 As shown, after adopting the delay-locked loop circuit of this application embodiment, the phase peak drift of the DQS signal is reduced by about 70%, thereby significantly improving stability and reliability.

[0087] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0088] The above embodiments only express several implementation manners of the present application, which are described in a more specific and detailed manner, but cannot be understood as a limitation on the patent scope of the present application. It should be noted that, for those skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A delay-locked loop circuit, characterized by comprising: The method comprises the steps of: a variable delay line for delaying an initial clock signal to generate a delayed clock signal; a control circuit connected with the variable delay line, configured to control the variable delay line to perform a first mode of delay adjustment, and further configured to control the variable delay line to perform a second mode of delay adjustment when the delayed clock signal meets a preset condition; wherein a step value of each delay adjustment in the first mode is a first step value, and a step value of each delay adjustment in the second mode is a second step value, the second step value being greater than the first step value; the control circuit comprises: a path replication module configured to receive the delayed clock signal and delay the delayed clock signal by a preset time to generate a feedback clock signal; a phase detection module configured to detect a phase difference between the feedback clock signal and the initial clock signal, and generate a normal detection signal according to the phase difference; a first control module connected with the phase detection module, configured to generate a first encoding group according to the normal detection signal, the first encoding group being used to adjust the delay of the variable delay line, and a least significant bit of the first encoding group corresponding to a step value of delay adjustment being the first step value; the control circuit further comprises: a phase anomaly detection module configured to detect a phase difference between the feedback clock signal and the initial clock signal, and generate an anomaly detection signal according to the phase difference; a second control module connected with the phase anomaly detection module, configured to generate a second encoding group according to the anomaly detection signal, the second encoding group being used to adjust the delay of the variable delay line, and a least significant bit of the second encoding group corresponding to a step value of delay adjustment being the second step value; the phase anomaly detection module is configured to determine that the delayed clock signal meets the preset condition when the phase difference between the feedback clock signal and the initial clock signal is greater than or equal to a phase difference threshold, and switch the anomaly detection signal to a first state, the anomaly detection signal in the first state being used to control the second encoding group to be valid; the phase anomaly detection module is further configured to determine an anomaly level of the phase difference; the second control module is further configured to receive the anomaly level and adjust the second step value according to the anomaly level; the phase anomaly detection module further comprises a threshold adjusting unit configured to update the phase difference threshold according to the anomaly detection signal; the phase anomaly detection module is configured to determine the anomaly level of the phase difference by updating the phase difference threshold, and adjust the anomaly level by using a state machine according to a current anomaly level and a state of the anomaly detection signal.

2. The delay-locked loop circuit of claim 1, wherein, the phase anomaly detection module is further configured to determine that the delayed clock signal does not meet the preset condition when the phase difference between the feedback clock signal and the initial clock signal is less than or equal to the phase difference threshold, and switch the anomaly detection signal to a second state, the anomaly detection signal in the second state being used to control the second encoding group to be invalid.

3. The delay-locked loop circuit of claim 1, wherein, the phase anomaly detection module comprises: A positive abnormality detection unit configured to generate a positive detection signal based on the feedback clock signal, a phase difference threshold signal, and an initial clock signal; A negative abnormality detection unit configured to generate a negative detection signal based on the feedback clock signal, an inverted signal of the phase difference threshold signal, and the initial clock signal; An operation unit configured to generate the abnormality detection signal based on the positive detection signal and the negative detection signal.

4. The delay-locked loop circuit of claim 3, wherein, The positive abnormality detection unit includes: A positive delay circuit configured to generate a first detection signal based on the feedback clock signal and the phase difference threshold signal; A reference delay circuit configured to generate a reference detection signal based on the initial clock signal; A positive phase discriminator connected to the positive delay circuit and the reference delay circuit, respectively, and configured to generate the positive detection signal based on the first detection signal and the reference detection signal.

5. The delay-locked loop circuit of claim 4, wherein, The positive delay circuit includes: A first delay circuit including a plurality of first inverters connected in parallel, an input end of the first inverter configured to receive the feedback clock signal, and the first inverter configured to invert the input signal under the control of the phase difference threshold; A second delay circuit including: A fixed delay chain configured to receive the feedback clock signal, and to generate a delayed feedback signal by presetting a delay of the feedback clock signal; A plurality of second inverters connected in parallel, an input end of the second inverter configured to receive the delayed feedback signal, and the second inverter configured to invert the input signal under the control of the phase difference threshold; Wherein, the outputs of the first delay circuit and the second delay circuit jointly constitute the first detection signal.

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