A method for manufacturing a shielded gate trench field effect transistor

Abstract

The present invention relates to a method for manufacturing a shielded-gate trench field-effect transistor. After forming a trench, a first silicon oxide layer, and a shield gate, a second silicon oxide layer is first formed within the trench, on the trench sidewalls, and on the substrate surface. The silicon oxide layer on the substrate surface is then removed using a three-step CMP process. Specifically, a CMP process is first used to remove most of the silicon oxide layer on the substrate surface. A CMP process is then performed using a polishing liquid with a high selectivity for the silicon oxide layer to the substrate to remove the remaining silicon oxide layer on the substrate surface. Finally, a CMP process is performed using a polishing liquid with a low selectivity for the silicon oxide layer to the substrate to remove the damaged layer on the substrate surface. After removing the excess second silicon oxide layer from the top of the shield gate in the trench, a gate is formed in the trench. The present invention utilizes an ONO-free structure, which simplifies process steps and significantly reduces manufacturing costs. A rational planarization process design eliminates damage to the silicon surface.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor device manufacturing, and in particular to a method for manufacturing a shielded gate trench field effect transistor. Background Art

[0002] The shielded-gate trench field-effect transistor (SGT) is an improved power device based on the traditional trench field-effect transistor and is currently widely used. The gate structure of an SGT transistor consists of a shield gate and a gate formed in a trench, insulated between the shield gate and the gate by an intermediate dielectric layer, commonly known as an inter-poly oxide (IPO). The conventional SGT manufacturing process is as follows: Before trench formation, a mask layer is formed on the substrate. This mask layer has an ONO structure (thin oxide layer-silicon nitride layer-thick oxide layer). A window is then etched using photolithography, and a trench is formed in the window. Subsequently, a trench isolation layer, a shield gate, an isolation layer between the shield gate and the gate, and the gate are formed in sequence. During this process, the mask layer is typically removed from the substrate surface using wet etching or CMP. Wet etching is a traditional process that relies on photolithography. With the increasing sophistication of photolithographic pattern lines, the requirements for photolithography and etching precision are becoming increasingly stringent. Limited by the development of process equipment, this traditional wet etching method can lead to surface unevenness and over-etching, making it unable to meet the current design requirements of semiconductor devices. The CMP process, which utilizes the synergistic effect of chemical etching and mechanical grinding, can effectively achieve both local and global flatness in semiconductor devices, and has become an indispensable alternative technology in integrated circuit manufacturing.

[0003] Traditional CMP processes use large abrasive particles and high polishing rates. These polishing slurries often have low selectivity for oxide and silicon nitride, often leading to over-erosion of the silicon nitride and significant butterfly effect between the center and edges. This can reduce device yield and performance. Later, based on the traditional CMP process, polishing slurries with high selectivity for oxide and silicon nitride were developed. These high-selectivity polishing slurries have a very low polishing rate for the silicon nitride layer, preventing over-erosion. Furthermore, the silicon nitride layer acts as a barrier layer, effectively minimizing the butterfly effect. In the traditional ONO structure manufacturing process for SGT products, the presence of the silicon nitride layer as a barrier prevents damage to the substrate surface during planarization. Considering the urgent need to reduce the manufacturing cost of SGT, the use of an ONO-free structure (no silicon nitride layer, only an oxide layer as a mask layer) can significantly simplify the process and reduce manufacturing costs, thereby improving market competitiveness. However, this also brings the following new problems: since there is no silicon nitride layer as a barrier layer during planarization, when the CMP process is used to remove the mask layer on the substrate surface, mechanical damage will be caused to the substrate surface, resulting in IDSS leakage problems. Summary of the Invention

[0004] The present invention aims to solve the problem of reducing the manufacturing cost of SGT, adopts an ONO-free structure for process design, and solves the IDSS leakage problem caused by damage to the substrate surface caused by the CMP process when using this structure.

[0005] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is:

[0006] A method for manufacturing a shielded gate trench field effect transistor comprises the following steps:

[0007] Step 1: forming a trench on a substrate, and forming a first silicon oxide layer on the trench sidewalls, the trench bottom, and the substrate surface;

[0008] Step 2: forming a shield grid inside the trench so that the upper surface of the shield grid is lower than the surface of the substrate;

[0009] Step 3: forming a second silicon oxide layer in the trench, on the trench sidewalls and on the substrate surface;

[0010] Step 4: performing CMP treatment on the silicon oxide layer on the surface of the substrate, namely: first using a first CMP process to remove a portion of the silicon oxide layer on the surface of the substrate, then using a second CMP process to remove the remaining silicon oxide layer on the surface of the substrate, and then using a third CMP process to remove the damaged layer on the substrate surface caused by the second CMP process; the polishing liquid used in the second CMP process has a greater selectivity ratio for the silicon oxide layer and the substrate than the polishing liquid used in the third CMP process;

[0011] Step 5: Remove the excess silicon oxide layer on the top of the shield gate in the trench, so that the upper surface of the remaining silicon oxide layer is lower than the surface of the substrate;

[0012] Step 6: Form a gate in the trench.

[0013] Further optimized, the second silicon oxide layer is formed by high-density plasma deposition.

[0014] According to further optimization, the selectivity of the polishing liquid used in the first CMP process to the silicon oxide layer and the substrate is smaller than the selectivity of the polishing liquid used in the second CMP process.

[0015] Further optimization is performed, and the selectivity ratio of the polishing liquid used in the first CMP process to the silicon oxide layer and the substrate is the same as the selectivity ratio of the polishing liquid used in the third CMP process.

[0016] According to further optimization, the erosion rates of the first CMP process and the third CMP process are both greater than the erosion rate of the second CMP process.

[0017] Further optimization is that the selectivity ratio of the polishing liquid used in the second CMP process to the silicon oxide layer and the substrate is ≥50:1; the selectivity ratio of the polishing liquid used in the third CMP process to the silicon oxide layer and the substrate is 1:1 to 3:1.

[0018] Further optimization is performed, in which the first CMP process removes 80%-90% of the thickness of the silicon oxide layer on the surface of the substrate, the second CMP process removes the remaining silicon oxide layer, and the third CMP process abrades the substrate together with the second silicon oxide layer in the groove, with an abrasion thickness of 1000Å to 2000Å.

[0019] Further optimization, the shielding grid is made of polysilicon, and the gate is made of polysilicon.

[0020] Further optimized, the base includes a silicon substrate located at the bottom layer and an epitaxial layer located on the surface of the silicon substrate, and the groove is formed in the epitaxial layer.

[0021] The present invention discloses a low-cost manufacturing method for shielded gate field-effect transistors. This method does not employ a traditional ONO structure, thus simplifying the process steps and significantly reducing manufacturing costs. The present invention utilizes a silicon oxide layer as a mask layer and an insulating dielectric layer. When the silicon oxide layer on the substrate surface is removed using a CMP process, the method is combined through three CMP steps: first, a polishing fluid with a low selectivity for the silicon oxide layer and the silicon substrate is used to remove the majority of the oxide layer on the substrate surface; then, a polishing fluid with a high selectivity for the silicon oxide layer and the silicon substrate is used to remove the remaining silicon oxide layer; and finally, a polishing fluid with a low selectivity for the silicon oxide layer and the silicon substrate is used to remove the damaged layer on the substrate surface. The first CMP polishing speed is relatively high, allowing for rapid removal of the majority of the silicon oxide layer; the second CMP polishing process can completely remove the remaining silicon oxide layer and correct the flattened surface to avoid the occurrence of butterfly-shaped defects. Because the mask layer of the present invention lacks silicon nitride as a barrier layer during planarization, the second CMP step causes mechanical damage to the substrate surface. This damage can increase IDSS leakage. The third CMP step, utilizing the rapid polishing effect of low selectivity, removes the damaged layer, reducing manufacturing costs while also avoiding new problems caused by process improvements. Because the three CMP steps can be integrated into the same process, the added final CMP step does not significantly increase costs, making the manufacturing cost significantly competitive compared to traditional ONO structure processing methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the manufacturing method of the present invention;

[0023] Figure 2 This is a schematic diagram of the structure before the grooves are opened in the manufacturing method of the present invention;

[0024] Figure 3 A schematic diagram of the process of the present invention after forming a first silicon oxide layer after trenching;

[0025] Figure 4 It is a schematic diagram after forming the shielding grid in the manufacturing method of the present invention;

[0026] Figure 5 is a schematic diagram after forming a second silicon oxide layer in the manufacturing method of the present invention;

[0027] Figure 6 This is a schematic diagram of the manufacturing method of the present invention after the first CMP process is performed;

[0028] Figure 7 This is a schematic diagram of the manufacturing method of the present invention after the second CMP process is performed;

[0029] Figure 8 It is a schematic diagram of the structure before forming the gate in the manufacturing method of the present invention. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0031] The present embodiment discloses a method for manufacturing a shielded gate trench field effect transistor. The biggest difference between this method and the existing manufacturing process is that it is designed without an ONO structure, which significantly reduces the manufacturing cost. When flattening the substrate surface, by means of the organic combination of three CMP processes with different grinding liquid selection ratios and a reasonable arrangement of the process sequence, not only the flattening efficiency is improved and the cost of the flattening process is reduced, but also the damage to the substrate surface that may be caused during the flattening process is solved, so that the IDSS leakage problem is improved. The content of this embodiment will be introduced in conjunction with the accompanying drawings, and only a brief description will be given of the parts of the process that are the same as the prior art. The manufacturing method flow adopted in this embodiment is as follows Figure 1 As shown, the process structure of manufacturing SGT products according to this method is shown in Figures 2 to 8 shown.

[0032] The specific steps of the above-mentioned manufacturing method are as follows:

[0033] The first step is to form a trench on the substrate: The substrate used in this embodiment includes a silicon substrate 1 and an epitaxial layer 2 on the surface of the silicon substrate 1. The trench is formed in the epitaxial layer 2. Before forming the trench, a mask layer 3 is first formed on the surface of the epitaxial layer 2 according to existing process methods. Then, a trench window is etched on the mask layer 3 using a photoresist 4 for protection. During the photolithography process, the mask layer 3 at the window is removed, and a trench 5 of a predetermined depth is formed by etching. The mask layer 3 is typically formed into a silicon oxide layer using thermal oxidation.

[0034] The second step is to form a first silicon oxide layer: Figure 3 As shown, after the groove 5 is formed, a silicon dioxide layer is formed as the first silicon oxide layer 6 by thermal oxidation in this embodiment. During the growth of the silicon oxide layer, an oxide layer will grow not only on the bottom and sidewalls of the groove 5, but also on the substrate surface on both sides of the groove 5. The silicon oxide layer formed on the substrate surface needs to be removed in a subsequent process.

[0035] The third step is to form a shield: Figure 4As shown, the shield gate in this embodiment is formed of polysilicon. When the polysilicon is filled into the trench 5, the polysilicon usually fills the entire trench 5. The excess polysilicon in the trench 5 needs to be further removed so that the upper surface of the shield gate 7 formed in the end is lower than the surface of the substrate. Before removing the polysilicon in the trench 5, the first silicon oxide layer 6 on both sides of the polysilicon on the sidewalls of the trench 5 can be left as is, or a portion of the first silicon oxide layer 6 can be removed. Considering that a V-shaped polysilicon layer will also form on the surface of the first silicon oxide layer 6 on the substrate when the polysilicon is filled into the trench 5, the polysilicon layer on the surface of the first silicon oxide layer 6 can be planarized using a CMP process after the filling is completed, and then the excess polysilicon in the trench 5 can be removed.

[0036] Step 4: Forming a second silicon oxide layer: The second silicon oxide layer is used to isolate the shielding gate and the gate. In order to improve the hole filling effect, in this embodiment, HDP (high density plasma deposition) is used to fill the trench 5 to form a second silicon oxide layer 8, and cover the surface of the substrate. The structure after the second silicon oxide layer 8 is formed is as follows: Figure 5 Before forming the second silicon oxide layer 8, the silicon oxide layer on the substrate surface may be as follows depending on the specific implementation:

[0037] In the first embodiment, the silicon oxide mask layer 3 and the first silicon oxide layer 6 remain on the substrate surface before the trench 5 is formed. After the second silicon oxide layer 8 is formed, the silicon oxide layer on the substrate surface is a superposition of the three aforementioned silicon oxide layers. In the second embodiment, the silicon oxide mask layer 3 is removed before the first silicon oxide layer 6 is formed. After the first silicon oxide layer 6 is retained on the substrate surface, the second silicon oxide layer 8 is formed. In this case, the silicon oxide layer on the substrate surface is a superposition of the first silicon oxide layer 6 and the second silicon oxide layer 8. In the third embodiment, after the silicon oxide mask layer 3 and the first silicon oxide layer 6 are removed, the substrate surface is oxidized to form a thin silicon oxide layer. A second silicon oxide layer 8 is formed on the surface of the thin silicon oxide layer. In this case, the silicon oxide layer on the substrate surface is a superposition of the thin silicon oxide layer and the second silicon oxide layer 8. Regardless of which of the above-mentioned embodiments is adopted, or other specific embodiments not shown, the silicon oxide layer on the substrate surface referred to in the fifth step of the present invention, when the substrate surface is subjected to CMP planarization, encompasses the oxide layers formed in the various aforementioned situations. The understanding of the silicon oxide layer structure formed in the trench 5 is the same as that listed in the above various embodiments.

[0038] Step 5: CMP planarization: This step aims to remove the silicon oxide layer on the substrate surface. To improve polishing efficiency and reduce costs, the removal of the substrate oxide layer is performed in two CMP processes. Specifically, the first CMP process abrades away the majority of the silicon oxide on the substrate surface, preferably removing 80% to 90% of the total thickness of the silicon oxide layer. The erosion rate of the first CMP process is greater than that of the second CMP process, aiming to improve erosion efficiency. Furthermore, to reduce costs, the first CMP process preferably utilizes a polishing slurry with a low selectivity ratio for the silicon oxide layer and the silicon substrate. This selectivity ratio is typically preferably within the range of 1:1 to 3:1 (preferably 1:1). A polishing slurry with a selectivity ratio within this range has similar or similar erosion rates for silicon oxide and silicon, resulting in larger polishing particles and a faster polishing speed, enabling rapid removal of the silicon oxide layer. While this low selectivity polishing slurry exhibits a faster erosion rate, it can also result in a butterfly effect. To eliminate this butterfly effect, this embodiment utilizes a second CMP process to remove the remaining silicon oxide layer on the substrate surface. The polishing liquid used in the second CMP process has a relatively high selectivity for silicon oxide and silicon, that is, the abrasive rate for silicon oxide is high, and the abrasive rate for the silicon substrate is low. The silicon substrate acts as a barrier layer to keep the abrasive surface at the silicon substrate. The polishing liquid used in the second CMP process has an ideal selectivity ratio of silicon oxide to silicon of ≥50:1, preferably ≥100:1. The abrasive rate of the second CMP process is lower than that of the first CMP process. The structure after the first CMP process is as follows: Figure 6 As shown, the structure after the second CMP process is as follows Figure 7 shown.

[0039] Because the substrate surface is not deposited with silicon nitride as a barrier layer during CMP planarization, as in existing processes, some polishing damage will remain on the substrate surface after the CMP process. This damaged layer can increase IDSS leakage, so it must be considered and addressed in the overall process design. The present invention removes this damaged layer by performing a second CMP process after the second CMP process, i.e., a third CMP process. This additional CMP step is intended to remove the thickness of the silicon damage layer on the substrate surface. Therefore, the third CMP process uses a slurry with a relatively low selectivity for the silicon oxide layer to the silicon layer (a selectivity ratio of 1:1 to 3:1, preferably 1:1). The abrasive rate of this CMP process is greater than that of the second CMP process, eliminating surface damage through rapid polishing of the silicon surface. During the third CMP process, the thickness of the damaged layer can be measured based on the specific settings of the second CMP process parameters. During the third CMP process, the polishing thickness can be set to slightly greater than the damaged layer thickness. Actual measurements show that the appropriate thickness for the third CMP process is approximately 1000Å-2000Å. Since the entire CMP process can be integrated into a single step, there is no significant increase in additional costs.

[0040] Step 6: Forming the gate: Before forming the gate, the excess silicon oxide layer on the top of the shield gate in the trench 5 must first be removed. This can be achieved by photolithography. The area that does not need to be removed is masked with photoresist. The silicon oxide layer of a preset depth in the trench 5 that needs to be removed is etched away. The remaining silicon oxide layer serves as an interlayer isolation layer between the shield gate and the gate. The upper surface of the remaining silicon oxide layer is lower than the substrate surface (e.g., Figure 8 As shown), finally, a gate is formed on the upper portion of the silicon oxide layer in the trench 5 (illustration omitted), and the gate may be made of polysilicon material.

[0041] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing a shielded gate trench field effect transistor, characterized in that: The steps include: Step 1: forming a trench on a substrate, and forming a first silicon oxide layer on the trench sidewalls, the trench bottom, and the substrate surface; Step 2: forming a shield grid inside the trench so that the upper surface of the shield grid is lower than the surface of the substrate; Step 3: forming a second silicon oxide layer in the trench, on the trench sidewalls and on the substrate surface; Step 4: CMP treatment is performed on the silicon oxide layer on the surface of the substrate, that is, first a first CMP process is used to remove part of the silicon oxide layer on the surface of the substrate, then a second CMP process is used to remove the remaining silicon oxide layer on the surface of the substrate, and then a third CMP process is used to remove the damaged layer on the surface of the substrate caused by the second CMP process; the selectivity of the grinding liquid used in the second CMP process to the silicon oxide layer and the substrate is greater than the selectivity of the grinding liquid used in the third CMP process, the first CMP process removes 80%-90% of the thickness of the silicon oxide layer on the surface of the substrate, the second CMP process removes the remaining silicon oxide layer, and the third CMP process abrades the substrate together with the second silicon oxide layer in the groove, and the abrasion thickness is Step 5: Remove the excess silicon oxide layer on the top of the shield gate in the trench, so that the upper surface of the remaining silicon oxide layer is lower than the surface of the substrate; Step 6: Form a gate in the trench.

2. The method for manufacturing a shielded gate trench field effect transistor according to claim 1, wherein: The second silicon oxide layer is formed by high-density plasma deposition.

3. The method for manufacturing a shielded gate trench field effect transistor according to claim 1, wherein: The selectivity ratio of the polishing liquid used in the first CMP process to the silicon oxide layer and the substrate is smaller than the selectivity ratio of the polishing liquid used in the second CMP process.

4. A method for manufacturing a shielded gate trench field effect transistor according to claim 1 or 3, characterized in that: The selectivity ratio of the polishing liquid used in the first CMP process to the silicon oxide layer and the substrate is the same as the selectivity ratio of the polishing liquid used in the third CMP process.

5. The method for manufacturing a shielded gate trench field effect transistor according to claim 1, wherein: The erosion rates of the first CMP process and the third CMP process are both greater than the erosion rate of the second CMP process.

6. The method for manufacturing a shielded gate trench field effect transistor according to claim 1, wherein: The selectivity ratio of the grinding liquid used in the second CMP process to the silicon oxide layer and the substrate is ≥50:1; the selectivity ratio of the grinding liquid used in the third CMP process to the silicon oxide layer and the substrate is 1:1 to 3:

1.

7. The method for manufacturing a shielded gate trench field effect transistor according to claim 1, wherein: The shielding grid is formed by filling the trench with shielding grid material, which also covers the surface of the substrate, removing the shielding grid material layer on the substrate surface by CMP process, and then removing the excess shielding grid material layer in the trench.

8. The method for manufacturing a shielded gate trench field effect transistor according to claim 1, wherein: The shielding grid is made of polysilicon, and the gate is made of polysilicon.

9. The method for manufacturing a shielded gate trench field effect transistor according to claim 1, wherein: The base comprises a silicon substrate located at a lower layer and an epitaxial layer located on a surface of the silicon substrate, and a groove is formed in the epitaxial layer.

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