Filter wafer packaging structure and method

Abstract

The invention discloses a wafer packaging structure and method for a filter, the wafer packaging structure comprises a substrate wafer and a glass wafer, a filter component and a first bonding compound are arranged on the substrate wafer, a TGV hole is formed in the glass wafer by laser-induced glass degeneration and wet etching, a first metal wiring layer is formed by electroplating on the first surface of the glass wafer and in the TGV hole, the first metal wiring layer is incompletely filled in the TGV hole, the electroplating time can be effectively shortened, the packaging efficiency is improved by more than 80%, and the thickness uniformity of the first metal wiring layer is improved, and the bonding yield is improved. A second bonding compound is made on the first metal wiring layer, and the second surface of the glass wafer is thinned to expose the first metal wiring layer at the bottom of the TGV hole so that it is interconnected with an external signal. The first bonding compound and the second bonding compound are bonded at the wafer level by solid-liquid interdiffusion, and after bonding, not only a good sealed cavity is formed to block the erosion of external water vapor, corrosive liquid, etc., but also ultra-thin packaging can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of wafer-level packaging, and in particular to a wafer packaging structure and method for a filter. Background Art

[0002] Bulk acoustic wave (BAW) filters use quartz crystal / silicon as substrates. The basic structure is two metal electrodes sandwiching a piezoelectric film. The thickness of the piezoelectric film is only 2μm at 2GHz. Above 2GHz, the thickness of the film deposition will be thinner. The sound waves oscillate in the piezoelectric layer to form standing waves. The frequency of resonance is determined by the thickness of the plate and the quality of the electrode. In order to keep the sound waves in the piezoelectric layer, the oscillating structure must be sufficiently isolated from the external environment to obtain a smaller insertion loss and a higher Q value. In order to provide the best performance of the BAW filter device, the piezoelectric layer structure of the BAW filter should be encapsulated in a reliable closed cavity to prevent moisture from penetrating.

[0003] Therefore, it is necessary to make a cap wafer and bond it to the bulk acoustic wave filter wafer to form a sealed cavity structure on the piezoelectric layer of the chip to prevent the intrusion of external water vapor, corrosive liquid, etc. and cause device failure. The commonly used packaging solutions in the industry: such as silicon-silicon (Silicon-Silicon) direct bonding technology, silicon-glass (Silicon-Glass) anodic bonding technology and bonding technology using glass material are typical examples. However, due to the high temperature required for these bonding methods and poor processability, these technologies are not widely used in BAW filter device packaging. Therefore, it is necessary to improve the BAW filter packaging technology to provide high oxidation resistance, high fracture toughness, low packaging cost, high performance, etc.

[0004] Currently, the industry's bulk acoustic wave filters mainly use silicon cap wafers with through silicon vias (TSV) and gold-deposited on the surface, which are gold-bonded to bulk acoustic wave filter wafers that also have a gold-deposited structure to achieve sealing protection and rewiring.

[0005] The existing packaging process of this type of filter has the following disadvantages:

[0006] 1. The TSV through-hole production process is complicated, and an insulating layer needs to be deposited inside the hole;

[0007] 2. The use of silicon cap wafers to create a sealed environment, evaporation of gold on the surface and gold-gold bonding make the packaging process costly;

[0008] 3. The gold-gold bonding packaging solution requires a thicker cap wafer and a thicker package body.

[0009] The TSV wafer is used as the capping layer. The TSV manufacturing process is complicated. Photolithography development must be performed first, and the required blind hole size must be etched at the photolithography opening by deep reactive ion etching (DRIE). After the blind hole is formed, the surface photoresist must be removed, which will introduce some impurities in the degumming liquid into the hole, causing the risk of subsequent electroplating voids in the hole. In addition, silicon is a semiconductor material, and an insulating layer must be made on the inner side wall of the hole, usually SiO2. The uniform coverage of the insulating layer along the hole further increases the difficulty of manufacturing.

[0010] Another packaging solution proposed in the acoustic wave filter package structure and manufacturing method requires making a groove structure on the cap wafer, which is a complicated process; the chip does not lead out the pad and cannot be interconnected with the outside world; the bonding temperature is set at 280℃-350℃, and the bonding temperature is too high, which will affect the chip performance; the cap wafer is too thick and cannot meet the ultra-thin packaging requirements of the chip. Summary of the invention

[0011] In view of the problems that the current filter packaging process is complex, the cost is high, and it is difficult to achieve ultra-thin packaging, the embodiments of the present application propose a filter wafer packaging structure and method to solve the above problems.

[0012] The present application proposes a filter wafer packaging method, comprising the following steps:

[0013] 1) providing a substrate wafer, wherein a filter component and a first bonding compound are provided on a first surface of the substrate wafer, and the first bonding compound is arranged around the filter component;

[0014] 2) providing a glass wafer, making a TGV hole on a first surface of the glass wafer, and electroplating a first metal wiring layer on the first surface of the glass wafer, wherein the first metal wiring layer also covers the sidewall and bottom of the TGV hole and does not completely fill the TGV hole;

[0015] 3) making a second bonding compound on the first metal wiring layer on the first surface of the glass wafer, and after turning the glass wafer or the substrate wafer upside down, bonding the first bonding compound to the second bonding compound by solid-liquid interdiffusion low-temperature wafer-level bonding to generate an intermetallic compound;

[0016] 4) thinning the second surface of the glass wafer to expose the first metal wiring layer at the bottom of the TGV hole;

[0017] 5) A welding portion is fabricated on the second surface of the glass wafer, wherein the welding portion is connected to the exposed first metal wiring layer.

[0018] In some embodiments, the TGV hole is formed in step 2 by laser-induced glass degeneration and wet etching.

[0019] In some embodiments, the bonding method between the first bonding compound and the second bonding compound is solid-liquid interdiffusion low-temperature wafer-level bonding, and an intermetallic compound is generated after bonding.

[0020] In some embodiments, the first bond is a gold pad, the second bond is a Sn solder, and the first bond and the second bond are bonded to generate an AuSn alloy phase.

[0021] In some embodiments, the welding portion includes a solder ball, and step 5 specifically includes: making a solder ball on the exposed first metal wiring layer on the second surface of the glass wafer.

[0022] In some embodiments, the welding portion includes a second metal wiring layer, a solder ball and a solder resist layer, and step 5 specifically includes:

[0023] Fabricating a second metal wiring layer on the second surface of the glass wafer, wherein the second metal wiring layer is connected to the exposed first metal wiring layer;

[0024] forming solder balls on the second metal wiring layer;

[0025] A solder resist layer is formed on the second metal wiring layer in an area other than the solder balls.

[0026] In some embodiments, after step 3, the method further includes: thinning the second surface of the substrate wafer.

[0027] In some embodiments, before forming the first metal wiring layer in step 2, the step further includes: forming a buffer layer around the opening edge of the TGV hole.

[0028] An embodiment of the present application also proposes a wafer packaging structure of a filter, comprising a substrate wafer and a glass wafer arranged relatively to each other, a filter component and a first bonding compound being provided on the substrate wafer, the first bonding compound being arranged around the filter component, a TGV hole and a first metal wiring layer being provided on the first surface of the glass wafer, the first metal wiring layer also covering the side wall and the bottom of the TGV hole and not completely filling the TGV hole, the first metal wiring layer at the bottom of the TGV hole being exposed on the second surface of the glass wafer, an intermetallic compound being provided between the first metal wiring layer of the glass wafer and the first bonding compound, the intermetallic compound being generated by solid-liquid interdiffusion low-temperature wafer-level bonding of the first bonding compound and the second bonding compound, and a welding portion connected to the exposed first metal wiring layer being provided on the second surface of the glass wafer.

[0029] In some embodiments, the welding portion includes a solder ball disposed above the exposed first metal wiring layer; or the welding portion includes a second metal wiring layer connected to the exposed first metal wiring layer, a solder ball disposed on the second metal wiring layer, and a solder resist layer covering the area of ​​the second metal wiring layer other than the solder ball.

[0030] In some embodiments, a buffer layer is disposed between the first surface of the glass wafer and the first metal wiring layer around the opening edge of the TGV hole.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] (1) The TGV hole of the present invention is partially filled with metal. Compared with completely filling the TGV hole, the electroplating process time can be greatly shortened, and the overall efficiency can be improved by 80%. In addition, from the perspective of post-packaging performance and reliability, incomplete filling of the TGV hole does not affect the electrical properties and reliability before and after packaging.

[0033] (2) The first bonding compound and the second bonding compound of the present invention are bonded at low temperature wafer level by solid-liquid interdiffusion, and mainly generate δ phase (AuSn) and ζ phase (Au5Sn) at the Sn-Au bonding interface. The bonding strength thereof has been tested to withstand the shear force test and reliability test of consumer electronics. The functional area (piezoelectric layer structure) of the filter is encapsulated inside the glass wafer to form a good sealed cavity, which can block the erosion of external water vapor, corrosive liquid, etc.

[0034] (3) The present invention provides a buffer layer near the opening edge of the TGV hole, which helps to improve the stress concentration problem at the edge of the TGV hole, prevents microcracks from occurring in the TGV hole, and improves the reliability of device packaging.

[0035] (4) The preparation of the TGV hole of the present invention does not require the preparation of a mask on a glass wafer. The fixed position can be modified directly by laser equipment, and the TGV hole can be formed by wet etching. The glass material itself is an insulating material, and there is no need to grow an insulating layer material on the side wall of the TGV hole. The TGV hole is formed as a trapezoidal hole, which is conducive to sputtering the seed layer and achieving better coverage. Therefore, the process flow can be simplified and the cost can be significantly reduced. By thinning the glass wafer and the substrate wafer, ultra-thin packaging can be achieved.

[0036] (5) Compared with completely filling the TGV hole, the first metal wiring layer in the TGV hole of the present invention is incompletely filled, which can improve the thickness uniformity of the first metal wiring layer and increase the bonding yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and are used together with the description to explain the principles of the present invention. It will be easy to recognize other embodiments and many expected advantages of the embodiments because they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale with each other. The same reference numerals refer to corresponding similar parts.

[0038] Figure 1-8 A schematic diagram of a process flow of a filter wafer packaging method according to Embodiment 1 of the present application;

[0039] Fig. 9 and Fig.10 It is a cross-sectional schematic diagram of the wafer packaging structure of the filter of the second embodiment of the present application;

[0040] Fig.11 and Fig.12 It is a cross-sectional schematic diagram of the wafer packaging structure of the filter of the third embodiment of the present application. DETAILED DESCRIPTION

[0041] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It should also be noted that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0043] Embodiment 1

[0044] An embodiment of the present invention provides a filter wafer packaging method, comprising the following steps:

[0045] 1)Reference Figure 1 , providing a substrate wafer 100, wherein a filter component 101 and a first bonding compound 102 are provided on a first surface of the substrate wafer 100, wherein the first bonding compound 102 is arranged around the filter component 101, and the first bonding compound 102 surrounds the filter component 101, and the filter component 101 can be an acoustic wave filter, preferably a bulk acoustic wave filter, especially a device functional area, but not limited thereto, and only the filter component that needs to be packaged can be used. In a preferred embodiment, the first bonding compound 102 is a gold pad. The substrate wafer 100 can be selected from quartz, silicon, etc., and the thickness of the substrate wafer 100 is 700-800μm.

[0046] 2)Reference Figure 2A glass wafer 200 is provided. The thickness of the glass wafer 200 is 500-600 μm. The glass wafer 200 can be selected to have a CTE similar to that of the substrate wafer 100 according to the difference of the substrate wafer 100 . A TGV hole 201 is made on the first surface of the glass wafer 200 . Specifically, after the incoming glass wafer 200 is cleaned, the TGV hole 201 is formed by laser-induced glass denaturation and wet etching. The TGV hole 201 is a blind hole, and there is no need to make a mask on the glass wafer 200. The fixed position on the glass wafer 200 is directly modified by a laser device, and the TGV hole 201 can be formed by wet etching. The glass blind hole formed after laser-induced glass denaturation and wet etching is a large trapezoidal hole, which is conducive to the sputtering seed layer of the subsequent electroplating process and achieves better coverage of the seed layer. Preferably, the opening size of the TGV hole 201 is 30-60μm, the bottom size is 20-50μm, and the depth of the TGV hole 201 is 130-170μm. The laser device uses a pulsed laser, and the wet etching uses hydrofluoric acid. The pulsed laser induces the glass to produce a continuous denaturation zone. Compared with the glass in the undenatured area, the denatured glass has a faster etching rate in hydrofluoric acid. Based on this phenomenon, a blind hole can be made on the glass wafer 200.

[0047] 3)Reference Figure 3 , a first metal wiring layer 202 is formed by electroplating on the first surface of the glass wafer 200, and the first metal wiring layer 202 also covers the sidewalls and bottom of the TGV hole 201 and is not completely filled in the TGV hole 201. The first metal wiring layer 202 inside the TGV hole 201 is partially filled with metal. Compared with the complete filling in the TGV hole 201, the electroplating process time can be greatly shortened, and the overall efficiency can be improved by more than 80%. From the perspective of post-packaging performance and reliability, the incomplete filling in the TGV hole 201 does not affect the electrical properties and reliability before and after packaging. At the same time, compared with the complete filling in the TGV hole, the use of incomplete filling can improve the uniformity of the thickness of the first metal wiring layer and improve the bonding yield. In addition to the first metal wiring layer 202, a certain gap is left in the TGV hole 201. The TGV hole 201 is incompletely filled with electroplating, and a first metal wiring layer 202 is also formed on the first surface of the glass wafer 200 outside the opening of the TGV hole 201. The first metal wiring layer 202 is made by an electroplating process. Since the glass wafer 200 itself is an insulating material, there is no need to grow an insulating layer on the sidewall of the TGV hole 201. A seed layer is directly deposited on the glass wafer 200, and then metal is electroplated on the seed layer to form the first metal wiring layer 202. Specifically, the material of the seed layer is titanium / copper (Ti / Cu), and the material of the filling metal is Cu or other conductive metal materials.

[0048] 4)Reference Figure 4-5, a second bonding compound 203 is made on the first metal wiring layer 202 on the first surface of the glass wafer 200. In a preferred embodiment, the second bonding compound 203 is Sn solder. Therefore, the second bonding compound 203 is electrically connected to the first metal wiring layer 202. After the glass wafer 200 or the substrate wafer 100 is inverted, the first surface of the glass wafer 200 and the first surface of the substrate wafer 100 are arranged opposite to each other, and then the first bonding compound 102 and the second bonding compound 203 are bonded. The bonding method between the first bonding compound 102 and the second bonding compound 203 is solid-liquid interdiffusion low-temperature wafer-level bonding, and an intermetallic compound 204 is generated after bonding. In a specific embodiment, the temperature of the solid-liquid interdiffusion low-temperature wafer-level bonding is 200-300°C, preferably 250-280°C, the bonding pressure is 3-8Mpa, preferably 4-5Mpa, and the bonding time is 5-20min, preferably 10min. Specifically, since the first bond 102 is a gold pad and the second bond 203 is Sn solder. Therefore, the first bond 102 and the second bond 203 generate AuSn alloy phase after bonding, and mainly generate δ phase (AuSn) and ζ phase (Au5Sn) at the Sn-Au bonding interface. The bonding strength of the first bond 102 and the second bond 203 after bonding can withstand the shear force test and reliability test of consumer electronics after testing. And the device functional area (piezoelectric layer structure) is encapsulated inside the glass wafer to form a good sealed cavity, which can block the erosion of external water vapor, corrosive liquid, etc. The sealed cavity is formed by the first bond 102, the second bond 203 and the intermetallic compound. Combined with the gold pad and Sn solder, a solid-liquid interdiffusion low-temperature wafer-level bonding process is adopted, so it is not necessary to make a groove structure on the glass wafer 200 to accommodate the device functional area (piezoelectric layer structure), the process is simple, and the manufacturing cost is low. In addition, in combination with the incomplete filling of metal in the TGV hole 201, more space is reserved above the device functional area without affecting the performance of the device functional area, which can effectively improve the reliability of the device.

[0049] 5)Reference Figure 6 , the second surface of the glass wafer 200 is thinned to expose the first metal wiring layer 202 at the bottom of the TGV hole 201. At this time, the TGV hole 201 is changed from a blind hole to a through hole, and the first metal wiring layer 202 at the bottom of the TGV hole 201 is exposed from the second surface of the glass wafer 200. The exposed first metal wiring layer 202 can further realize interconnection with external signals. Specifically, the glass wafer 200 is thinned by mechanical grinding, which can be rough ground first and then fine ground and polished. The thickness of the thinned glass wafer 200 is selected to be 70-150μm.

[0050] 6)Reference Figure 7A soldering portion is made on the second surface of the glass wafer 200, and the soldering portion is connected to the exposed first metal wiring layer 202, so that external signals can be interconnected through the soldering portion. Specifically, the soldering portion is a solder ball 205, and the solder ball 205 is made above the exposed first metal wiring layer 202 on the second surface of the glass wafer 200.

[0051] 7)Reference Figure 8 , the second surface of the substrate wafer 100 is thinned and diced, not only the glass wafer 200 can be thinned to 70-150 μm, but the substrate wafer 100 can also be thinned to 80 to 120 μm, thereby effectively realizing ultra-thin packaging of devices.

[0052] The above filter wafer packaging method not only solves the problem of complex process and low cost performance of existing packaging structure, but also effectively improves the reliability of the device.

[0053] Corresponding to the above-mentioned filter wafer packaging method, the embodiment of the present application also proposes a filter wafer packaging structure, referring to Figure 7The wafer packaging structure includes a substrate wafer 100 and a glass wafer 200 arranged relatively to each other, a filter component 101 and a first bonding compound 102 are arranged on the substrate wafer 100, the first bonding compound 102 is arranged around the filter component 101, and a TGV hole 201 and a first metal wiring layer 202 are arranged on the first surface of the glass wafer 200, the first metal wiring layer 202 covers the side wall and bottom of the TGV hole 201 and is not completely filled in the TGV hole 201. Compared with the complete filling in the TGV hole, the use of the incomplete filling method can improve the uniformity of the thickness of the first metal wiring layer and improve the bonding yield. The first metal wiring layer 202 in the TGV hole 201 is formed by incomplete filling electroplating, so the electroplating process time can be effectively shortened, and the processing efficiency can be greatly improved. The first metal wiring layer 202 at the bottom of the TGV hole 201 is exposed on the second surface of the glass wafer 200. An intermetallic compound 204 is formed at a position corresponding to the first bonding compound on the first metal wiring layer 201 of the glass wafer 200. The intermetallic compound 204 is generated by bonding the first bonding compound 102 and the second bonding compound 203 through a solid-liquid interdiffusion low-temperature wafer-level bonding process. The first bonding compound 102 is a gold pad, and the second bonding compound 203 is Sn solder. Therefore, the intermetallic compound is an AuSn alloy phase. A welding portion connected to the exposed first metal wiring layer 202 is provided on the second surface of the glass wafer 200. Specifically, the welding portion is a solder ball 205 arranged above the exposed first metal wiring layer 202, which can realize an electrical interconnection structure from a device pad to an external welding portion. The wafer packaging structure of the filter of the present application solves the problems of complex process and low cost performance of the existing packaging structure, and realizes a low-cost and high-reliability packaging structure of a bulk acoustic wave filter.

[0054] Embodiment 2

[0055] The difference between the second embodiment and the first embodiment is that: Fig. 9 and Fig.10 The welding part includes a second metal wiring layer 206, a solder ball 205 and a solder resist layer 207. The second metal wiring layer 206 is connected to the exposed first metal wiring layer 202. The solder ball 205 is arranged at any position on the second metal wiring layer 206. The solder resist layer 207 covers the area of ​​the second metal wiring layer other than the solder ball 205. Therefore, according to the different positions of the external substrate, the Sn solder can be rewired at any position on the glass wafer 200 through the second metal wiring layer 206. The rewiring forms are various and can realize interconnection with external signals. The step 6 specifically includes:

[0056] A second metal wiring layer 206 is formed on the second surface of the glass wafer 200, and the second metal wiring layer 206 is connected to the exposed first metal wiring layer 202;

[0057] A solder ball 205 is formed on the second metal wiring layer 206. In this case, the position of the solder ball 205 can be determined according to specific wiring requirements, which is more flexible.

[0058] A solder resist layer 207 is formed on the second metal wiring layer 206 in the area other than the solder ball 205 . The solder resist layer 207 covers the area other than the solder ball 205 above the second metal wiring layer 206 , which can improve the reliability of the device.

[0059] The rest is the same as that of the first embodiment.

[0060] Embodiment 3

[0061] The difference between the third embodiment and the first or second embodiment is that: Fig.11 and Fig.12 In step 2, before making the first metal wiring layer 202, the step further includes: making a buffer layer 208 around the opening edge of the TGV hole 201. The buffer layer 208 is disposed between the first surface of the glass wafer 200 and the first metal wiring layer 202 around the opening edge of the TGV hole. The buffer layer 208 can improve the stress concentration problem at the edge of the TGV hole 201 and prevent micro cracks from appearing around the TGV hole 201. Specifically, the material of the buffer layer 208 can be selected from an organic dry film or glue.

[0062] The above describes the specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0063] In the description of the present application, it should be understood that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The simple fact that certain measures are recorded in mutually different dependent claims does not indicate that a combination of these measures cannot be used for improvement. Any reference symbols in the claims should not be interpreted as limiting the scope.

Claims

1. A filter wafer packaging method, characterized in that: The following steps are involved: 1) providing a substrate wafer, wherein a filter component and a first bonding compound are provided on a first surface of the substrate wafer, and the first bonding compound is arranged around the filter component; 2) providing a glass wafer, making a TGV hole on a first surface of the glass wafer, and electroplating a first metal wiring layer on the first surface of the glass wafer, wherein the first metal wiring layer also covers the sidewall and bottom of the TGV hole and does not completely fill the TGV hole; 3) making a second bonding compound on the first metal wiring layer on the first surface of the glass wafer, and after turning the glass wafer or the substrate wafer upside down, bonding the first bonding compound to the second bonding compound by solid-liquid interdiffusion low-temperature wafer-level bonding to generate an intermetallic compound; 4) thinning the second surface of the glass wafer to expose the first metal wiring layer at the bottom of the TGV hole; 5) A welding portion is fabricated on the second surface of the glass wafer, wherein the welding portion is connected to the exposed first metal wiring layer.

2. The filter wafer packaging method according to claim 1, characterized in that: In the step 2, the TGV hole is formed by laser-induced glass degeneration and wet etching.

3. The filter wafer packaging method according to claim 1, characterized in that: The first bonding compound is a gold pad, the second bonding compound is a Sn solder, and the first bonding compound and the second bonding compound are bonded to generate an AuSn alloy phase.

4. The filter wafer packaging method according to claim 1, characterized in that: The welding portion includes a solder ball, and the step 5 specifically includes: making a solder ball on the exposed first metal wiring layer on the second surface of the glass wafer.

5. The filter wafer packaging method according to claim 1, characterized in that: The welding portion includes a second metal wiring layer, a solder ball and a solder resist layer, and the step 5 specifically includes: Fabricating a second metal wiring layer on the second surface of the glass wafer, wherein the second metal wiring layer is connected to the exposed first metal wiring layer; forming solder balls on the second metal wiring layer; A solder resist layer is formed on the second metal wiring layer in an area other than the solder balls.

6. The filter wafer packaging method according to claim 1, characterized in that: Before forming the first metal wiring layer in step 2, the step further includes: forming a buffer layer on the first surface of the glass wafer around the opening edge of the TGV hole.

7. The filter wafer packaging method according to claim 1, characterized in that: After step 3, the method further includes: thinning the second surface of the substrate wafer.

8. A filter wafer packaging structure, characterized in that: It includes a substrate wafer and a glass wafer arranged opposite to each other, wherein a filter component and a first bond are arranged on the substrate wafer, wherein the first bond is arranged around the filter component, a TGV hole and a first metal wiring layer are arranged on the first surface of the glass wafer, wherein the first metal wiring layer also covers the side wall and the bottom of the TGV hole and does not completely fill the TGV hole, wherein the first metal wiring layer at the bottom of the TGV hole is exposed on the second surface of the glass wafer, an intermetallic compound is arranged between the first metal wiring layer of the glass wafer and the first bond, wherein the intermetallic compound is generated by solid-liquid interdiffusion low-temperature wafer-level bonding of the first bond and the second bond, and a welding portion connected to the exposed first metal wiring layer is arranged on the second surface of the glass wafer.

9. The filter wafer packaging structure according to claim 8, characterized in that: The welding portion includes a solder ball arranged above the exposed first metal wiring layer; or, the welding portion includes a second metal wiring layer connected to the exposed first metal wiring layer, a solder ball arranged on the second metal wiring layer, and a solder resist layer covering the area of ​​the second metal wiring layer other than the solder ball.

10. The filter wafer packaging structure according to claim 8, characterized in that: A buffer layer is provided between the first surface of the glass wafer and the first metal wiring layer around the opening edge of the TGV hole.

Images