Device and method for controlling a clock signal

Abstract

An apparatus and method for controlling a clock signal are provided. In certain embodiments, a semiconductor die includes a core circuit and a clock interface circuit that provides a clock signal to the core circuit. The clock interface circuit includes an oscillator for generating an oscillator signal and a comparator for controlling the operation of the clock interface circuit in a selected clock control mode based on comparing an electrical characteristic of a clock interface pin with a comparison threshold. The selected clock control mode is selected from: a first clock control mode, in which the clock interface circuit generates a clock signal based on an input clock signal received on a clock interface pin; or a second clock control mode, in which the clock interface circuit generates a clock signal based on an oscillator signal.

Description

Technical Field

[0001] Embodiments of the present invention relate to electronic systems and, more particularly, to clock interface circuits for integrated circuits (ICs). Background Art

[0002] A variety of electronic systems operate based on the timing of clock signals. For example, examples of electronic circuits that operate based on the timing of clock signals include, but are not limited to, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), data communication links, amplifiers, digital circuits, and / or voltage regulators. Summary of the invention

[0003] Devices and methods for controlling clock signals are provided. In certain embodiments, a semiconductor die includes a core circuit and a clock interface circuit that provides a clock signal to the core circuit. The semiconductor die also includes a plurality of pins or pads, including at least a power supply voltage pin and a clock interface pin coupled to the clock interface circuit. The clock interface circuit includes: an oscillator for generating an oscillator signal; and a comparator for selecting a selected clock control mode from two or more clock control modes to control the operation of the clock interface circuit based on comparing the electrical characteristics of the clock interface pin and a comparison threshold. The two or more clock control modes include: a first clock control mode, in which the clock interface circuit generates a clock signal based on an input clock signal received on the clock interface pin; and a second clock control mode, in which the clock interface circuit generates a clock signal based on the oscillator signal. Therefore, the clock interface circuit provides flexibility in controlling the clock signal provided to the core circuit.

[0004] In one aspect, a semiconductor die with clock control is provided. The semiconductor die includes: a plurality of pins, including a power pin and a first clock interface pin. The semiconductor die also includes a clock interface circuit configured to output a clock signal, the clock interface circuit being coupled to the power pin and the first clock interface pin. The clock interface circuit includes: an oscillator configured to generate an oscillator signal; and a first comparator configured to control the operation of the clock interface circuit in a selected clock control mode selected from two or more clock control modes based on comparing an electrical characteristic of the first clock interface with a comparison threshold. The two or more clock control modes include: a first clock control mode, in which the clock interface circuit generates a clock signal based on an input clock signal received on a clock interface pin; and a second clock control mode, in which the clock interface circuit generates a clock signal based on the oscillator signal.

[0005] On the other hand, a clock control method in an electronic system is provided. The method includes: using a clock signal provided by a clock interface circuit coupled to a power pin and a first clock interface pin to control the timing of a core circuit; using a comparator of the clock interface circuit to compare an electrical characteristic of the first clock interface pin with a comparison threshold; and operating the clock interface circuit in a selected clock control mode selected from two or more clock control modes based on the comparison, including: in a first clock control mode, generating a clock signal based on an input clock signal received on the clock interface pin; and in a second clock control mode, using an oscillator of the clock interface circuit to generate a clock signal.

[0006] On the other hand, an electronic system is provided. The electronic system includes a power supply configured to generate a power supply voltage and a first semiconductor die. The first semiconductor die includes: a power supply pin configured to receive the power supply voltage; a clock interface pin; and a clock interface circuit configured to output a clock signal. The clock interface circuit includes: an oscillator configured to generate an oscillator signal; and a first comparator configured to control the operation of the clock interface circuit in a selected clock control mode selected from two or more clock control modes based on comparing an electrical characteristic of the first clock interface with a comparison threshold. The two or more clock control modes include: a first clock control mode, in which the clock interface circuit generates a clock signal based on an input clock signal received on the clock interface pin; and a second clock control mode, in which the clock interface circuit generates a clock signal based on the oscillator signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram of a semiconductor die including a clock interface circuit according to one embodiment.

[0008] Figure 2A It is a depiction Figure 1 A schematic diagram of an example of a first clock control mode of a semiconductor die.

[0009] Figure 2B Is a description Figure 1 A schematic diagram of an example of a second clocking mode of a semiconductor die.

[0010] Figure 2C It is a depiction Figure 1 Schematic diagram of another example of a second clock control mode of a semiconductor die.

[0011] Figure 3 is a schematic diagram of a semiconductor die including a clock interface circuit according to another embodiment.

[0012] Figure 4is a schematic diagram of a semiconductor die including a clock interface circuit according to another embodiment.

[0013] Figure 5A is a schematic diagram of a semiconductor die including a clock interface circuit according to another embodiment.

[0014] Figure 5B It is a depiction Figure 5A An example of a graph of the operation of a semiconductor die.

[0015] Figure 6 is a schematic diagram of a semiconductor die including a clock interface circuit according to another embodiment.

[0016] Fig. 7A is a schematic diagram of another embodiment of a semiconductor die.

[0017] Figure 7B is a schematic diagram of another embodiment of a semiconductor die.

[0018] Figure 7C is a schematic diagram of another embodiment of a semiconductor die.

[0019] Fig.7D is a schematic diagram of another embodiment of a semiconductor die.

[0020] Fig. 8A is a schematic diagram of an electronic system according to another embodiment.

[0021] Figure 8B is a schematic diagram of an electronic system according to another embodiment. DETAILED DESCRIPTION

[0022] The following detailed description of the embodiments presents various descriptions of specific embodiments of the invention. However, the invention may be implemented in a variety of different ways. In this description, reference is made to the accompanying drawings in which similar reference numerals may indicate identical or functionally similar elements. It will be understood that the elements shown in the drawings are not necessarily drawn to scale. In addition, it will be understood that some embodiments may include more elements than those shown in the drawings and / or a subset of the elements shown in the drawings. In addition, some embodiments may combine any suitable combination of features from two or more drawings.

[0023] Devices and methods for controlling clock signals are provided. In certain embodiments, a semiconductor die includes a core circuit and a clock interface circuit that provides a clock signal to the core circuit. The semiconductor die also includes a plurality of pins or pads, including at least a power supply voltage pin and a clock interface pin coupled to the clock interface circuit. The clock interface circuit includes: an oscillator for generating an oscillator signal; and a comparator for selecting a selected clock control mode from two or more clock control modes to control the operation of the clock interface circuit based on comparing electrical characteristics of the clock interface pin and a comparison threshold. The two or more clock control modes include: a first clock control mode, in which the clock interface circuit generates a clock signal based on an input clock signal received on the clock interface pin; and a second clock control mode, in which the clock interface circuit generates a clock signal based on the oscillator signal.

[0024] Thus, the clock interface circuit provides flexibility in controlling the clock signal provided to the core circuit.

[0025] For example, using the first clock control mode, the semiconductor die can be deployed in a first application in which it is desired to clock the core circuit using an input clock signal provided to the clock interface pin. For example, the core circuit can communicate with another circuit external to the semiconductor die (e.g., a data converter), and the common clock signal can be used to control the timing of the core circuit and the external circuit to avoid intermodulation distortion and / or aliasing. When operating in the first clock control mode, the frequency of the input clock signal can be changed as needed, and / or the frequency of the input clock signal can be stopped and resumed as needed.

[0026] In addition, using the second clock control mode, the semiconductor die can be further deployed in a second application, where the oscillator of the clock interface circuit generates a clock signal for the core circuit. For example, in some use cases, the default oscillation frequency of the oscillator may be suitable for clocking the core circuit, thereby reducing costs by avoiding the need for an external clock source.

[0027] The clock interface circuit thus provides enhanced flexibility to enable the same semiconductor die to be used in a wide range of applications.Thus, the need to manufacture many different types of semiconductor dies with respective custom clock designs is avoided.

[0028] In some embodiments, the comparison threshold of the comparator is generated based on the voltage level of the power supply voltage pin.For example, the clock interface circuit may include a bias voltage source that changes the power supply voltage to generate a reference voltage used as the comparison threshold.

[0029] Implementing the clock interface circuit in this manner has a number of advantages, including the ability to operate the clock interface circuit in a second clock control mode by connecting the clock interface pin to the supply voltage pin directly or through an impedance (eg, an external resistor).

[0030] In some embodiments, when operating in the second clock control mode, the voltage level of the clock interface pin is used to adjust the oscillation frequency of the oscillator. In such an implementation, flexibility can be further improved by providing a mechanism for tuning the oscillator of the clock interface circuit.

[0031] The voltage level of the clock interface pin can be set to a desired voltage level in a variety of ways, such as by connecting a resistor with a specific resistance between the power supply voltage pin and the clock interface pin, thereby setting the voltage level of the clock interface pin to a specific voltage level corresponding to the desired oscillation frequency. In another example, a digital-to-analog converter (DAC) or other external control circuit sets a tuning voltage that can be changed over time to achieve the desired oscillation frequency.

[0032] In some embodiments, the clock interface circuit includes a plurality of clock interface pins, such as a pair of clock interface pins implemented in a differential manner. For example, using a pair of differential clock interface pins allows providing a differential input clock signal in the first clock control mode, which has the advantages of lower clock noise and / or reduced jitter relative to a single-ended configuration.

[0033] In the above embodiment, the core circuit is integrated with the clock interface circuit on the same semiconductor die. However, other configurations are possible. In another embodiment, the clock interface circuit and the core circuit are on separate semiconductor dies, which can be packaged together in a module. In yet another embodiment, the core circuit is integrated with the clock interface circuit on the chip, but the clock signal is also provided off-chip to an external component, which can be, for example, the core circuit of another semiconductor die.

[0034] Figure 1 is a schematic diagram of a semiconductor die 10 according to an embodiment. The semiconductor die 10 includes a clock interface circuit 1, a core circuit 2, a power supply voltage pin 5 (SUPPLY) and a clock interface pin 6 (SYNC). The semiconductor die, for example Figure 1 The semiconductor die 10 is also referred to herein as a semiconductor chip or an integrated circuit (IC).

[0035] The power supply voltage pin 5 and the clock interface pin 6 correspond to pins (e.g., bonding pads) of the semiconductor die 10. Although described as including only two pins, the semiconductor die 10 typically includes other pins and other circuits for implementing the desired operation or function. For clarity, these details have been removed from Figure 1Omitted in .

[0036] like Figure 1 As shown, semiconductor die 10 includes core circuit 2, the timing of which is controlled by clock signal CLK provided by clock interface circuit 1. The performance of core circuit 2 is affected by multiple operating parameters of clock signal CLK, including but not limited to frequency, phase and / or noise.

[0037] The core circuit 2 may correspond to a variety of circuits. For example, examples of circuits that may be included in the core circuit 2 include data converters, digital circuits, amplifiers, frequency synthesizers, voltage regulators, and / or data communication circuits. The clock interface circuits herein may provide clock signals to various types of circuits.

[0038] The desired properties (eg, frequency) of clock signal CLK may vary from one application to another. Furthermore, it is desirable for semiconductor die 10 to be used in a wide variety of applications without custom designing semiconductor die 10 to have clock signal characteristics suitable for one specific application.

[0039] To provide flexibility in controlling the clock signal CLK, in this embodiment, the semiconductor die 10 includes a clock interface circuit 1, which is coupled to the power supply voltage pin 5 and the clock interface pin 6. The clock interface circuit 1 senses the electrical characteristics of the clock interface pin 6 and selects a clock control mode for controlling the clock signal CLK based on the sensed characteristics.

[0040] For example, Figure 1 The clock interface circuit 1 includes a comparator 3 that compares an electrical characteristic (e.g., a voltage level) of a clock interface pin 6 with a comparison threshold. In addition, the result of the comparison is used to set the clock interface circuit 1 to a selected clock control mode. In some embodiments, the comparison threshold of the comparator 3 is generated based on the voltage level of the power supply voltage pin 5. The power supply voltage pin 5 can correspond to any power supply voltage pin, including a positive power supply voltage pin, a negative power supply voltage pin, or a ground pin.

[0041] Continue to refer Figure 1 The clock interface circuit 1 further comprises an oscillator 4 which generates an internal oscillator signal when enabled.

[0042] Figure 1 The clock interface circuit 1 can operate in two or more clock control modes, including at least a first clock control mode in which the clock interface circuit 1 generates a clock signal CLK based on an input clock signal received on a clock interface pin 6, and a second clock control mode in which the clock interface circuit 1 generates a clock signal CLK based on an oscillator signal from an oscillator 4. The selected clock control mode is selected based on the comparison of the comparator 3.

[0043] In some embodiments, when operating in the second clock control mode, the voltage level of the clock interface pin 6 is used to tune the oscillation frequency of the oscillator 4. In such embodiments, flexibility can be further increased by providing a mechanism for adjusting the oscillator 4 of the clock interface circuit.

[0044] Figure 2A It is shown Figure 1 FIG. 1 is a schematic diagram of an example of a first clock control mode 20 of a semiconductor die 10. Figure 2A As shown, the power supply voltage V sup A power supply voltage is supplied to the power supply voltage pin 5 , and an external clock source 11 has provided an input clock signal to the clock interface pin 6 .

[0045] In this configuration, the clock interface control circuit 1 operates in the first clock control mode. Therefore, the input clock signal provided to the clock interface pin 6 is used to generate the clock signal CLK of the core circuit 2. In some embodiments, when operating the first clock control mode, the clock signal CLK corresponds to a buffered version of the input clock signal and therefore has the same frequency.

[0046] In some embodiments, the comparator 3 compares the voltage level of the clock interface pin 6 with the threshold voltage and sets the selected clock control mode based on the comparison result. In addition, the clock source 11 controls the voltage level of the input clock signal, including when the input clock signal is at a peak amplitude level and a minimum amplitude level, to be lower or higher than the threshold voltage of the comparator 3, so that when the input clock signal switches, the output of the comparator 3 does not change.

[0047] Therefore, the clock source 11 sets the voltage level of the clock interface pin 6 to inform the clock interface circuit 1 to operate in the first clock control mode. In addition, the clock source 11 provides the input clock signal to the clock interface circuit 1, which generates the clock signal CLK for the core circuit 2 using the clock interface circuit 1.

[0048] When operating in the first clock control mode, the frequency of the input clock signal can be changed as needed, and / or the frequency of the input clock signal can be stopped and restored as needed. Therefore, the clock source 11 does not need to generate an input clock signal with a fixed frequency. In addition, the clock source 11 can enable or disable the input clock signal as needed.

[0049] Figure 2B Is a description Figure 1 FIG. 1 is a schematic diagram of an example of a second clock control mode 30 of a semiconductor die 10. Figure 2B As shown, the power supply voltage V has been supplied to the power supply voltage pin 5. sup, and an external resistor 21 is connected between the power supply voltage pin 5 and the clock interface pin 6.

[0050] In this configuration, the clock interface control circuit 1 operates in the second clock control mode. Therefore, the internal oscillator signal from the oscillator 4 is used to generate the clock signal CLK for the core circuit 2.

[0051] In some embodiments, when operating in the second clock control mode, the voltage V at the clock interface pin 6 is EXT It is used to set the oscillation frequency of the internal oscillator signal, thereby setting the frequency of the clock signal CLK.

[0052] In such an embodiment, a resistor value corresponding to the desired oscillation frequency of the oscillator 4 may be selected to be connected between the power supply pin 5 and the clock interface pin 6. Thus, by simply selecting a resistor with a particular resistance, the end user may instruct the clock interface circuit 1 to use the oscillator 4 to generate the clock signal CLK and use the resistor value to set V EXT , thereby setting the oscillation frequency of oscillator 4.

[0053] Figure 2C It is shown Figure 1 Schematic diagram of another example of a second clock control mode 40 of the semiconductor die 10. Figure 2B Compared to the example, DAC 31 instead of a resistor is used to set the voltage level V of the clock interface pin 6 EXT .

[0054] Various external control circuits can be used to set the voltage level V at clock interface pin 6 EXT Therefore, despite the Figure 2B and 2C An example using a resistor and a DAC is described in , but the second clock control mode may be set in other ways.

[0055] In the illustrated embodiment, the DAC 31 provides enhanced flexibility in tuning or adjusting the oscillation frequency of the oscillator 4. Thus, the DAC 31 may be suitable for applications where it is desirable to dynamically change the oscillation frequency of the oscillator 4, for example, in applications where the operating frequency varies over time and / or in applications where the oscillation frequency is adjusted to account for changes in operating conditions (e.g., temperature and / or supply voltage).

[0056] Figure 3 1 is a schematic diagram of a semiconductor die 120 including a clock interface circuit according to another embodiment. The semiconductor die 120 includes a clock interface circuit 101, a core circuit 102, a high power supply pin VDD, a low power supply pin VSS, a first clock interface pin SYNCP, and a second clock interface pin SYNCN.

[0057] In the depicted embodiment, the clock interface circuit 101 includes a first hysteresis comparator 103 , a second hysteresis comparator 104 , a digital logic circuit 105 , a clock buffer 106 , an oscillator 107 , a multiplexer 108 , and a reference voltage source 109 .

[0058] like Figure 3 As shown, the reference voltage source 109 is based on the high power supply pin V DD The power supply voltage received on the hysteresis comparator 103 is shifted to generate a reference voltage for the first hysteresis comparator 103 and the second hysteresis comparator 104. For example, in some embodiments, the reference voltage corresponds to V DD -VB, where V DD is the high power supply pin V DD The voltage level, while V B is the voltage of the reference voltage source 109 .

[0059] The first hysteresis comparator 103 generates a first comparison signal COMPP based on comparing the voltage level of the first clock interface pin SYNCP with a reference voltage, and the second hysteresis comparator 104 generates a second comparison signal COMPN based on comparing the voltage level of the second clock interface pin SYNCN with a reference voltage.

[0060] Continue to refer Figure 3 The digital logic circuit 105 processes the first comparison signal COMP and the second comparison signal COMPN to generate an oscillator enable signal OSCEN, which is used to enable the oscillator 107 and control the selection of the multiplexer 108.

[0061] The clock buffer 106 includes a differential input connected to a first clock interface pin SYNCP and a second clock interface pin SYNCN. The clock buffer 106 further includes a clock signal V SYNC The output of the first signal input provided to the multiplexer 108. When enabled, the oscillator 107 generates the oscillator signal V OSC is provided to the second signal input of the multiplexer 108. The multiplexer 108 converts the clock signal V CLK Output to the core circuit 102.

[0062] In the illustrated embodiment, the first hysteresis comparator 103 and the second hysteresis comparator 104 compare the reference voltage from the reference voltage source 109 with the voltage levels of the first clock interface pin SYNCP and the second clock interface pin SYNCN, respectively. Using hysteresis comparators has many advantages, such as providing hysteresis to suppress noise from inadvertently changing the comparison results during operation.

[0063] Based on the comparison result, the digital logic circuit 105 sets the clock interface circuit 101 to the first clock control mode or the second clock control mode. Therefore, relative to the reference voltage used for comparison, the voltage levels of the first clock interface pin SYNCP and the second clock interface pin SYNC determine whether the clock interface circuit 101 operates in the first clock control mode or the second clock control mode. In some embodiments, when the voltage levels of the clock interface pins are greater than the reference voltage, the second clock control mode is selected, otherwise, the first clock control mode is selected.

[0064] In the illustrated embodiment, when operating in the first clock control mode, the oscillator 107 is disabled and the multiplexer 108 selects the synchronous clock signal V SYNC As the clock signal V of the core circuit 102 CLK In addition to the delay of the clock buffer 106, the synchronous clock signal V SYNC Synchronized to a differential input clock signal received between the first clock interface pin SYNCP and the second clock interface pin SYNCN. Using a pair of differential clock interface pins allows providing a differential input clock signal in the first clock control mode, which has the advantage of lower clock noise and / or reduced jitter relative to a single-ended configuration.

[0065] Continue to refer Figure 3 , when operating in the second clock control mode, the oscillator 107 is enabled, and the oscillator signal V OSC The clock signal V selected by the multiplexer 108 to be used as the clock signal of the core circuit 102 CLK The frequency of the oscillator 107 is not adjusted by the voltage level of the clock interface pin.

[0066] Figure 4 1 is a schematic diagram of a semiconductor die 130 including a clock interface circuit according to another embodiment. The semiconductor die 130 includes a clock interface circuit 121, a core circuit 102, a high power supply pin VDD, a low power supply pin VSS, and a clock interface pin SYNCP. The clock interface circuit 121 includes a hysteresis comparator 103, a digital logic circuit 105, a clock buffer 106, an oscillator 107, a multiplexer 108, a first reference voltage source 109, and a second reference voltage source 129.

[0067] and Figure 3 Compared to the semiconductor die 120, Figure 4 The semiconductor die 130 omits the second clock interface pin SYNCN and the second hysteresis comparator 104. In addition, Figure 4 The clock interface circuit 121 includes a second reference voltage source 129 for generating a clock buffer reference voltage for the clock buffer 106 .

[0068] like Figure 4 As shown, the second reference voltage source 129 generates a clock buffer reference voltage based on shifting the power supply voltage received on the low power supply pin VSS. For example, in some embodiments, the clock buffer reference voltage corresponds to V SS +V BN , where V SS is the voltage level of the low power pin VSS, V BN is the voltage of the second reference voltage source 129 .

[0069] When operating in the first clock control mode, the synchronous clock signal VSYNC corresponds to a buffered version of the single-ended input clock signal received on the clock interface pin VSYNCP. Figure 3 Compared to semiconductor die 120 , semiconductor die 130 has fewer clock interface pins but is more susceptible to noise in the first clock control mode.

[0070] Figure 5A 1 is a schematic diagram of a semiconductor die 150 including a clock interface circuit according to another embodiment. The semiconductor die 150 includes a clock interface circuit 131, a core circuit 102, a high power supply pin VDD, a low power supply pin VSS, a first clock interface pin SYNCP, and a second clock interface pin SYNCN. The clock interface circuit 131 includes a first hysteresis comparator 103, a second hysteresis comparator 104, a digital logic circuit 105, a clock buffer 106, a multiplexer 108, a reference voltage source 109, a voltage-to-current converter 141, an oscillator 142, a current source I REF In the depicted embodiment, the voltage-to-current converter 141 includes an amplifier 143, a reference resistor 144 (having a resistance R REF ) and transistor 145.

[0071] and Figure 3 Compared with the clock interface circuit 101, Figure 5A The clock interface circuit 131 also includes a voltage-current converter 141 and a current source I REF When operating in the second clock control mode, the current source I REF is enabled, and the voltage-to-current converter 141 generates a control current I OSC_Ctrl , the control current I OSC_Ctrl The control current I OSC_Ctrl Used to tune the oscillation frequency of the oscillator 142.

[0072] Thus, when operating in the second clock control mode, the voltage level of the first clock interface pin SYNCP is used to tune the frequency of the oscillator 142, thereby tuning the frequency of the clock signal VCLK provided to the core circuit 102. Frequency enhancement is achieved by providing a mechanism for oscillator frequency control.

[0073] For example, the control current I OSC_Ctrl An expression of I REF *R EXT / R REF , so the control current I OSC_Ctrl Increases with the resistance of the external resistor.

[0074] In the embodiment shown, an external resistor R EXT However, other implementations of setting the voltage level of the first clock interface pin SYNCP are also possible.

[0075] Figure 5B It is a depiction Figure 5A FIG. 1 is an example of a graph of operation of semiconductor die 150 .

[0076] The graph depicts a first time period that depicts operation when the input clock signal switches in the first clock control mode. In addition, the graph depicts a second time period that depicts operation when the input clock signal does not switch in the first clock control mode. Figure 5B As shown, when operating in the first clock control mode, the frequency of the input clock signal can be changed as needed, and / or the input clock signal can be stopped and restored as needed.

[0077] Continue to refer Figure 5B The graph also includes a third time period, which depicts a circuit having a small resistance value R in the second clock control mode. EXT In addition, the graph also includes a fourth time period, which depicts the operation of the large resistance value R in the second clock control mode. EXT Operations. Figure 5B As shown, when operating in the second clock control mode, the frequency of the oscillator of the clock interface control circuit can be adjusted based on the resistance value selected for the external resistor.

[0078] Figure 61 is a schematic diagram of a semiconductor die 160 including a clock interface circuit according to another embodiment. The semiconductor die 160 includes a clock interface circuit 151, a core circuit 102, a high power supply pin VDD, a low power supply pin VSS, a first clock interface pin SYNCP, and a second clock interface pin SYNCN. The clock interface circuit 151 includes a first hysteresis comparator 103, a second hysteresis comparator 104, a digital logic circuit 105, a clock buffer 106, a multiplexer 108, a reference voltage source 109, a voltage-to-current converter 141, and a current source I REF , oscillator 152 and ADC 153.

[0079] Figure 6 The clock interface circuit 151 is similar to Figure 5A The clock interface circuit 131 includes, in addition to the clock interface circuit 151, an ADC 153 for digitizing the controllable current from the current-voltage converter 141. The ADC 153 provides a digital tuning signal to the oscillator 152.

[0080] Thus, digital tuning of the oscillator 152 is provided. Using digital tuning provides a number of advantages, including but not limited to the flexibility of digitally processing the digital control signal using any desired processing (eg, shaping, variation compensation, and / or other processing).

[0081] Figures 7A-7D Various examples of core circuits that receive clock signals from clock interface circuits are depicted. Although various applications of clock interface circuits are depicted, the clock interface circuit can be used to generate clock signals for a variety of core circuits. Therefore, other implementations are also possible.

[0082] Fig. 7A FIG. 2 is a schematic diagram of another embodiment of a semiconductor die 210. The semiconductor die 210 includes a clock interface circuit 191 and a chopper amplifier 192. For clarity, Fig. 7A Pins coupled to the clock interface circuit 191 and components of the clock interface circuit 191 are not shown. However, the clock interface circuit 191 may be implemented according to any embodiment herein.

[0083] In the illustrated embodiment, the chopper amplifier 192 includes an input chopper circuit 201, an amplifier circuit 202, and an output chopper circuit 203, which are electrically connected along a differential signal path between a pair of input terminals (V IN+ 、V IN- ) and a pair of output terminals (V OUT+ 、V OUT- )between.

[0084] like Fig. 7AAs shown, the clock interface circuit 191 generates a clock signal CLK, which is used to control the chopping operations of the input chopping circuit 201 and the output chopping circuit 203.

[0085] When operating in the first clock control mode, the input chopping circuit 201 can be controlled by an input clock signal that is synchronized with an external component (e.g., an ADC that digitizes the output voltage of the chopping amplifier 192) to avoid aliasing. In addition, when operating in the first clock control mode, the input clock signal can be stopped as needed to provide continuous amplification without chopping, and then restored when chopping is required.

[0086] Furthermore, when operating in the second clock control mode, the oscillator of the clock interface circuit 191 generates the clock signal CLK. Thus, the chopping can be controlled using an internal self-clock that can be adjusted to a user-selected frequency by setting the voltage level of the clock interface pin.

[0087] Figure 7B FIG. 2 is a schematic diagram of another embodiment of a semiconductor die 220. The semiconductor die 220 includes a clock interface circuit 191 and an ADC 212. For clarity of the figure, pins coupled to the clock interface circuit 191 and components of the clock interface circuit 191 are not shown. Figure 7B However, the clock interface circuit 191 may be implemented according to any embodiment herein.

[0088] In the illustrated embodiment, ADC 212 receives an input signal IN and generates a digital output signal DOUT. The timing of the data conversion operation of ADC 212 is controlled by a clock signal CLK from clock interface circuit 191.

[0089] Figure 7C 2 is a schematic diagram of another embodiment of a semiconductor die 230. The semiconductor die 230 includes a clock interface circuit 191 and a DAC 222. For clarity of the figure, pins coupled to the clock interface circuit 191 and components of the clock interface circuit 191 are not shown. Figure 7C However, the clock interface circuit 191 may be implemented according to any embodiment herein.

[0090] In the illustrated embodiment, the DAC 222 receives a digital input signal DIN and generates an output signal OUT. The timing of the data conversion operation of the DAC 222 is controlled by the clock signal CLK from the clock interface circuit 191.

[0091] Fig.7D FIG. 2 is a schematic diagram of another embodiment of a semiconductor die 240. The semiconductor die 240 includes a clock interface circuit 191 and a switching regulator 232. For the sake of clarity, the Fig.7DPins coupled to the clock interface circuit 191 and components of the clock interface circuit 191 are not shown. However, the clock interface circuit 191 may be implemented according to any embodiment herein.

[0092] In the illustrated embodiment, the switching regulator 232 generates a regulated voltage V based on the timing of the clock signal CLK from the clock interface circuit 191. REG Thus, the switch of the switching regulator 232 may be opened or closed to control regulation. For example, the switching regulator 232 may correspond to a buck converter or a boost converter having a switch for controlling the current delivered to the inductor.

[0093] Fig. 8A 3 is a schematic diagram of an electronic system 330 according to another embodiment. The electronic system 330 includes a first semiconductor die 318 and a second semiconductor die 320.

[0094] Apart from Fig. 8A In addition to outputting a clock signal CLK at a clock output pin, the first semiconductor die 318 and the Figure 1 The semiconductor die 10 is similar to the semiconductor die 10 of FIG. Fig. 8A As shown, the clock signal CLK is provided from the first semiconductor die 318 to the core circuit 302 of the second semiconductor die 320. In some embodiments, the first semiconductor die 318 and the second semiconductor die 320 are co-packaged on a module.

[0095] Figure 8B 3 is a schematic diagram of an electronic system 340 according to another embodiment. The electronic system 340 includes a first semiconductor die 319 and a second semiconductor die 320.

[0096] Apart from Figure 8B The semiconductor die 319 omits the core circuit 2. Figure 8B The first semiconductor die 319 is similar to Fig. 8A Therefore, the first semiconductor die 319 does not include the core circuit 2, but outputs the clock signal CLK on the clock output pin to provide the core circuit 302 of the second semiconductor die 320.

[0097] application

[0098] The device using the above solution can be implemented as various electronic devices. Examples of electronic devices include but are not limited to consumer electronic products, electronic testing equipment, communication systems, data converters, etc.

[0099] in conclusion

[0100] The foregoing description may refer to elements or features as being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" refers to an element / feature being directly or indirectly connected to another element / feature, and not necessarily mechanically. Similarly, unless expressly stated otherwise, "coupled" refers to an element / feature being directly or indirectly coupled to another element / feature, and not necessarily mechanically. Therefore, although the various schematic diagrams shown in the drawings depict example arrangements of elements and components, additional intermediate elements, devices, features, or components may be present in actual embodiments (assuming that the functionality of the depicted circuits is not adversely affected).

[0101] Although certain embodiments have been described, these embodiments are given by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods and systems described herein can be embodied in a variety of other forms. In addition, without departing from the spirit of the present disclosure, various omissions, replacements and changes can be made to the forms of the methods and systems described herein. For example, although the disclosed embodiments are presented in a given arrangement, alternative embodiments can perform similar functions with different components and / or circuit topologies, and certain elements can be deleted, moved, added, subdivided, combined and / or modified. Each of these elements can be implemented in a variety of different ways. Any appropriate combination of the elements and actions of the various embodiments described above can be combined to provide other embodiments. Therefore, the scope of the present invention is limited only by reference to the appended claims.

[0102] Although the claims set forth herein are filed in the United States Patent and Trademark Office (USPTO) in a single dependent format, it should be understood that any claim may be dependent on any previous claim of the same type unless it is obviously technically infeasible.

Claims

1. A semiconductor die with clock control, the semiconductor die comprising: a plurality of pins, including a power pin and a first clock interface pin, the power pin being configured to receive a power supply voltage from a power supply when in use; and A clock interface circuit is configured to output a clock signal, wherein the clock interface circuit is coupled to the power supply pin and the first clock interface pin, wherein the clock interface circuit comprises: an oscillator configured to generate an oscillator signal; and a first comparator configured to control the operation of the clock interface circuit in a selected clock control mode selected from two or more clock control modes based on comparing an electrical characteristic of the first clock interface pin with a comparison threshold, the clock interface circuit being configured to generate the comparison threshold based on a voltage level VDD of the power supply voltage, Wherein, the two or more clock control modes include: a first clock control mode, in which the clock interface circuit generates the clock signal based on an input clock signal received on the first clock interface pin; and a second clock control mode, in which the clock interface circuit generates the clock signal based on the oscillator signal.

2. The semiconductor die of claim 1, wherein: The voltage level of the first clock interface pin tunes the oscillation frequency of the oscillator in the second clock control mode.

3. The semiconductor die of claim 2, wherein: The clock interface circuit also includes a voltage-to-current converter configured to convert a voltage level of the first clock interface pin into a control current.

4. The semiconductor die of claim 3, wherein: The clock interface circuit further includes an analog-to-digital converter ADC configured to convert the control current into a digital control signal for controlling an oscillation frequency of the oscillator.

5. The semiconductor die of claim 3, wherein: The clock interface circuit further includes a current source connected to the first clock interface pin, wherein the current source is disabled in the first clock control mode and enabled in the second clock control mode.

6. The semiconductor die of claim 1, wherein: The plurality of pins further includes a second clock interface pin, wherein the input clock signal is differentially received between the first clock interface pin and the second clock interface pin in the first clock control mode.

7. The semiconductor die of claim 6, wherein: The clock interface circuit also includes: a second comparator configured to compare the electrical characteristics of the second clock interface pin with the comparison threshold; and a digital logic circuit configured to receive a first comparison signal from the first comparator and a second comparison signal from the second comparator.

8. The semiconductor die of claim 1, wherein: The clock interface circuit further includes a voltage source configured to generate the comparison threshold based on the voltage level VDD of the power supply pin.

9. The semiconductor die of claim 1, wherein: The clock interface circuit also includes: a clock buffer having an input coupled to the first clock interface pin and an output configured to provide a synchronous clock signal; and a multiplexer having a first signal input configured to receive the synchronous clock signal and a second input configured to receive the oscillator signal.

10. The semiconductor die of claim 9, wherein: The clock interface circuit also includes a digital logic circuit configured to control selection of the multiplexer based on a comparator output signal from the first comparator, wherein an output of the multiplexer controls the clock signal.

11. The semiconductor die of claim 1 further comprising a chopper amplifier having an input chopper circuit and an output chopper circuit controlled by the clock signal.

12. A clock control method in an electronic system, the method comprising: controlling the timing of the core circuitry using a clock signal provided by a clock interface circuit coupled to a power supply pin and a first clock interface pin, the power supply pin being configured, in use, to receive a supply voltage from a power supply; comparing, using a comparator of the clock interface circuit, an electrical characteristic of the first clock interface pin with a comparison threshold, the comparison threshold being generated based on a voltage level of the power supply voltage; and Based on the comparison, to operate the clock interface circuit in a selected clock control mode selected from two or more clock control modes, including: in a first clock control mode, generating the clock signal based on an input clock signal received on the first clock interface pin; and in a second clock control mode, using an oscillator of the clock interface circuit to generate the clock signal.

13. The method of claim 12, further comprising tuning an oscillation frequency of the oscillator based on a voltage level of the first clock interface pin in the second clock control mode.

14. The method according to claim 12, wherein: The method also includes differentially receiving the input clock signal between the first clock interface pin and a second clock interface pin in the first clock control mode.

15. An electronic system comprising: a power supply configured to generate a supply voltage; and A first semiconductor die comprising: a power pin configured to receive said supply voltage from said power supply when in use; Clock interface pins; and A clock interface circuit configured to output a clock signal, wherein the clock interface circuit comprises: an oscillator configured to generate an oscillator signal; and a first comparator configured to control the operation of the clock interface circuit in a selected clock control mode selected from two or more clock control modes based on comparing an electrical characteristic of the clock interface pin with a comparison threshold, the clock interface circuit being configured to generate the comparison threshold based on a voltage level VDD of the power supply voltage, Wherein, the two or more clock control modes include: a first clock control mode, in which the clock interface circuit generates the clock signal based on the input clock signal received on the clock interface pin; and a second clock control mode, in which the clock interface circuit generates the clock signal based on the oscillator signal.

16. The electronic system of claim 15, further comprising an external resistor connected between the power pin and the clock interface pin.

17. The electronic system according to claim 16, wherein: The oscillation frequency of the oscillator varies based on the resistance of the external resistor. 18 . The electronic system of claim 15 , further comprising an external clock source configured to provide the clock signal to the clock interface pin.

19. The electronic system of claim 15, further comprising a second semiconductor die including core circuitry that receives the clock signal.

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