Gate drive circuit and semiconductor circuit breaker

Abstract

A gate drive circuit (1) includes: an input terminal (T1); a first circuit path (5) inserted in a wire connecting the input terminal (T1) and a gate of a power transistor (2); a second circuit path (6) connected in parallel with the first circuit path (5); and a third circuit path (7) connected in parallel with the second circuit path (6), the first circuit path (5) has a gate resistor (Rgon), the second circuit path (6) has a first capacitor (C1) and a first resistor (R1) connected in series, the third circuit path (7) has a second capacitor (C2) and a second resistor (R2) connected in series, the second capacitor (C2) has a larger capacitance than the first capacitor (C1), the second resistor (R2) has a larger resistance than the first resistor (R1), and the gate resistor (Rgon) has a larger resistance than the second resistor (R2).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a gate drive circuit that drives a power transistor and a semiconductor circuit breaker. BACKGROUND

[0002] Highly reliable and high-quality systems are required in data centers and communication stations. A direct current power supply system used in these systems branches electric power supplied from a superior power supply device by a current distribution device to supply electric power to a plurality of loads. The current distribution device is provided with a protection device at the time of a short circuit. The types of the protection device include a fuse, an MCCB (Molded-Case Circuit Breaker), a protection device using a semiconductor power transistor (hereinafter, referred to as a semiconductor circuit breaker), and the like. For example, the semiconductor circuit breaker operates as follows, that is, if an overcurrent is detected, the overcurrent is limited by controlling a gate voltage of the semiconductor power transistor and turning off the semiconductor power transistor.

[0003] The semiconductor power transistor is controlled by a gate drive circuit that supplies a signal for driving a switching operation to a gate. For example, Patent Documents 1 to 7 and Non-Patent Document 1 disclose a gate drive circuit.

[0004] (Prior Art Documents)

[0005] (Patent Documents)

[0006] Patent Document 1: Japanese Patent No. 3964833

[0007] Patent Document 2: Japanese Patent No. 5925434

[0008] Patent Document 3: Japanese Laid-Open Patent Publication No. H10-327059

[0009] Patent Document 4: Japanese Laid-Open Patent Publication No. 2010-220325

[0010] Patent Document 5: Japanese Laid-Open Patent Publication No. 2003-284318

[0011] Patent Document 6: Japanese Laid-Open Patent Publication No. 2000-232347

[0012] Patent Document 7: Japanese Laid-Open Patent Publication No. H1-183214

[0013] (Non-Patent Documents)

[0014] Non-Patent Document 1: "Double-stage Gate Drive Circuit for Parallel Connected IGBT Modules" D. Bortis, P. Steiner, J. Biela and J. W. Kolar, Published in: IEEE Transactions on Dielectrics and Electrical Insulation (Volume: 16, Issue: 4, August 2009)

[0015] However, in the semiconductor circuit breaker, if the current is cut off at high speed, a surge voltage generated from the energy stored in the parasitic inductance of the load circuit is applied to the device. In a case where the surge voltage exceeds the withstand voltage, there is a possibility that the semiconductor circuit breaker is destroyed. Thus, if the current is cut off at high speed, there is a problem that the reliability of the semiconductor circuit breaker is reduced.

[0016] On the other hand, if the current is cut off at low speed, a Miller plateau in which the gate voltage of the semiconductor power transistor becomes flat is lengthened. In the Miller plateau, the current between the drain and the source is not cut off, and thus, there is a possibility that the semiconductor circuit breaker is destroyed due to overcurrent. Thus, if the current is cut off at low speed, there is also a problem that the reliability of the semiconductor circuit breaker is reduced. SUMMARY

[0017] Therefore, an object of the present disclosure is to provide a gate drive circuit and a semiconductor circuit breaker that suppress a surge voltage and shorten a Miller plateau to improve reliability.

[0018] To solve the problem, a gate drive circuit according to one embodiment of the present disclosure includes an input terminal, a first circuit path inserted in a wiring connecting the input terminal and a gate of a power transistor, a second circuit path connected in parallel to the first circuit path, and a third circuit path connected in parallel to the second circuit path, the first circuit path having a gate resistor, the second circuit path having a first capacitor and a first resistor connected in series, the third circuit path having a second capacitor and a second resistor connected in series, the second capacitor having a larger capacitance than the first capacitor, the second resistor having a larger resistance than the first resistor, and the gate resistor having a larger resistance than the second resistor.

[0019] Further, a semiconductor circuit breaker according to one embodiment of the present disclosure includes the above-described gate drive circuit and the power transistor.

[0020] According to the gate drive circuit and the semiconductor circuit breaker of the present disclosure, it is possible to suppress a surge voltage and shorten a Miller plateau to improve reliability. BRIEF DESCRIPTION OF DRAWINGS

[0021] FIG. 1A is a circuit diagram showing a power switching system including a gate drive circuit of a comparative example.

[0022] FIG. 1B is a graph showing waveforms of a gate-source voltage, a drain-source voltage, and a drain-source current of a gate drive circuit of a comparative example.

[0023] FIG. 1C is a graph showing characteristics of a gate-source voltage and a drain-source current with respect to a size of a gate resistor of a comparative example.

[0024] FIG. 2A is a graph showing a structure example of a power switching system including a gate drive circuit to which an embodiment is applied.

[0025] FIG. 2B is a waveform graph showing a gate voltage, a gate current, and a source current of a gate drive circuit of a comparative example and an embodiment.

[0026] FIG. 3 is a graph showing one example of a gate charge characteristic of a power transistor at the time of turn-off.

[0027] FIG. 4 is an explanatory diagram showing a case of a gate current of a gate drive circuit to which an embodiment is applied.

[0028] FIG. 5 is a graph showing experimental results of a gate drive circuit of a comparative example and an embodiment.

[0029] FIG. 6 is a graph showing other experimental results of a gate drive circuit of a comparative example and an embodiment.

[0030] FIG. 7A is a graph showing a structure example of a power switching system including a modified example 1 of a gate drive circuit to which an embodiment is applied.

[0031] FIG. 7B is an operation explanatory diagram of a gate drive circuit of the modified example 1 and a comparative example.

[0032] FIG. 8A is a graph showing a structure example of a power switching system including a modified example 2 of a gate drive circuit to which an embodiment is applied.

[0033] FIG. 8B is an operation explanatory diagram of a comparative example provided with an FEF as a power transistor.

[0034] FIG. 8Cis a working explanatory diagram of a gate drive circuit having an FEF as a power transistor according to an embodiment.

[0035] FIG. 9A is a diagram showing a structure example of a power switching system including Modification 3 of the gate drive circuit according to the embodiment.

[0036] FIG. 9B is a working explanatory diagram of Modification 3 of the gate drive circuit according to the embodiment.

[0037] FIG. 10 is a diagram showing a structure example of a power switching system including Modification 4 of the gate drive circuit according to the embodiment.

[0038] FIG. 11A is a diagram showing a structure example of a power switching system including Modification 5 of the gate drive circuit according to the embodiment.

[0039] FIG. 11B is a working explanatory diagram of Modification 5 of the gate drive circuit according to the embodiment. DETAILED DESCRIPTION

[0040] (Procedure for obtaining one embodiment of the present disclosure)

[0041] The inventors found that the above-described problems occur with the gate drive circuit described in the "BACKGROUND" section. Hereinafter, the problems will be described using FIGS. 1A-1C the problems.

[0042] FIG. 1A is a circuit diagram showing a power switching system including a gate drive circuit according to a comparative example. The power switching system of this diagram has a load circuit 13, a power transistor 12, and a gate drive circuit 11.

[0043] The load circuit 13 is a schematic equivalent circuit including a diode DO and a parasitic inductance Ls.

[0044] The power transistor 12 is a power device for power control.

[0045] The gate drive circuit 11 has a control circuit 14 and a gate resistor Rg.

[0046] The control circuit 14 generates a rectangular wave signal, i.e., a gate signal, for causing the power transistor 12 to switch, and supplies the gate signal to the gate of the power transistor 12 via the gate resistor Rg.

[0047] The gate resistor Rg moderates a sharp change in the gate signal. The gate resistor Rg increases the rise time and the fall time. In other words, the gate resistor Rg is a resistor for performing adjustment to make the slew rate of the rising edge and the falling edge large.

[0048] FIG. 1B is a graph schematically showing waveforms of the gate-source voltage Vgs, the drain-source voltage Vds, and the drain-source current Ids of the gate drive circuit of the comparative example. The horizontal axes of the upper section and the lower section of the graph are time axes. The vertical axis of the upper section shows the gate-source voltage at the time of turn-off of the power transistor 12. Hereinafter, the gate-source voltage Vgs will be sometimes referred to simply as the gate voltage Vgs. The vertical axis of the lower section shows the drain-source voltage Vds and the drain-source current Ids. Hereinafter, the drain-source voltage Vds will be sometimes referred to simply as the drain voltage Vds, and the drain-source current Ids will be sometimes referred to simply as the drain current Ids. Vth shows the threshold voltage of the power transistor 12.

[0049] The time t1 is set as the start point of the fall of the gate signal from the control circuit 14, that is, the start point of turn-off of the power transistor 12. The time t4 is the end point of turn-off. From the time t1 to the time t4, a monotonic change does not occur, but a Miller plateau period in which the gate voltage Vgs becomes flat occurs.

[0050] Here, the Miller plateau period will be described. In a case where the gate voltage Vgs becomes near the threshold voltage Vth at the time of turn-on or turn-off of the power transistor 12, a period in which the gate voltage Vgs becomes flat occurs in order to charge and discharge a parasitic capacitance Cgd between the gate and the drain (which has a larger effect than an actual capacitance value due to the Miller effect). This period is the Miller plateau period. The Miller voltage Vgm refers to the gate voltage Vgs in this Miller plateau period. The Miller plateau period is a period in which the drain-source voltage Vds changes, and ends when the drain-source voltage Vds reaches a final value.

[0051] As shown in FIG. 1B , if the change in current after the end of the Miller plateau period is referred to as the current breaking speed di / dt, the surge voltage due to the parasitic inductance Ls is proportional to Ls(di / dt). That is, the magnitude of the surge voltage is proportional to the inductance coefficient of the parasitic inductance Ls, and is proportional to the current breaking speed di / dt. In a case where the surge voltage exceeds the withstand voltage, there is a possibility that the semiconductor circuit breaker is destroyed, and thus it is necessary to reduce the current breaking speed di / dt.

[0052] FIG. 1C is a graph showing characteristics of the gate-source voltage Vgs and the drain-source current Ids with respect to the size of the gate resistance Rg of the comparative example. The double-dot chain line, the broken line, the one-dot chain line, the dash line, and the solid line in the graph correspond to the size of the resistance value of the gate resistance Rg in order. As shown in FIG. 1CAs shown, if the resistance value of the gate resistor Rg is small, the Miller plateau period is short, and if the resistance value of the gate resistor Rg is large, the Miller plateau period is long. In the Miller plateau period, the drain current Ids is not cut off, and thus, there is a possibility that the semiconductor circuit breaker is destroyed due to overcurrent, and thus, it is necessary to shorten the Miller plateau period.

[0053] However, as shown in FIG. 2, if the resistance value of the gate resistor Rg is small, the current breaking speed di / dt is high, and thus, there is a trade-off relationship between the suppression of the surge voltage and the shortening of the Miller plateau period. FIG. 1C

[0054] Thus, the present disclosure provides a gate drive circuit and a semiconductor circuit breaker that simultaneously achieve the suppression of the surge voltage and the shortening of the Miller plateau period, and thus, improves the reliability.

[0055] To solve the problem, a gate drive circuit according to an embodiment of the present disclosure includes: an input terminal; a first circuit path inserted in a wiring connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel to the first circuit path; and a third circuit path connected in parallel to the second circuit path, the first circuit path having a gate resistor, the second circuit path having a first capacitor and a first resistor connected in series, the third circuit path having a second capacitor and a second resistor connected in series, the second capacitor having a larger capacitance than the first capacitor, the second resistor having a larger resistance value than the first resistor, and the gate resistor having a larger resistance value than the second resistor.

[0056] Accordingly, it is possible to shorten the Miller plateau period and suppress the surge voltage (i.e., reduce the current breaking speed di / dt). That is, it is possible to improve the reliability of the power transistor.

[0057] For example, during the turn-off of the power transistor, first, the second circuit path 6 releases a portion of the charge from the gate capacitance of the power transistor 2 at a high speed. Accordingly, it is possible to shorten the Miller plateau period.

[0058] For example, the third circuit path is configured to release another portion of the charge from the gate capacitance at a lower speed than the second circuit path after the release of the second circuit path is completed. Accordingly, the current breaking speed is reduced, and thus, it is possible to suppress the surge voltage.

[0059] In addition, the resistance value of the gate resistor of the first circuit path is larger than the second resistor, and thus, it hardly contributes to the release at the time of the turn-off of the power transistor.

[0060] Also, a semiconductor circuit breaker according to an embodiment of the present disclosure includes the above-described gate drive circuit and the power transistor. ​

[0061] Accordingly, it is possible to shorten the Miller plateau and suppress the surge voltage. That is, it is possible to improve the reliability of the power transistor.

[0062] Hereinafter, for the embodiments, specific description will be made with reference to the drawings.

[0063] Moreover, the embodiments described below each show a general or specific example. The numerical values, shapes, materials, component configurations, component arrangement positions, connection methods, steps, order of steps, and the like shown in the embodiments below are one example, and the gist is not limited to them. Moreover, for the components of the embodiments below, components not described in the embodiment showing the most general concept are described as arbitrary components.

[0064] (Embodiment)

[0065] [1. Structure]

[0066] FIG. 2A is a diagram showing a structure example of a power switching system including a gate drive circuit according to the embodiment. The power switching system of this diagram is, for example, a semiconductor circuit breaker.

[0067] The load circuit 3 is a schematic equivalent circuit including a diode D0 and a parasitic inductance Ls.

[0068] The power transistor 2 is a power device for power control, for example, a semiconductor switching element having a withstand voltage of several hundred V. For example, the power transistor 2 can also be an IGBT (Insulated Gate Bipolar Transistor), a SiC FET (Field Effect Transistor), and a gallium nitride (GaN) transistor. Moreover, the power transistor 2 can have a P-type gate structure, can be a GaN bidirectional switch of a P-type double gate structure, or can be a MOSFET.

[0069] The gate drive circuit 1 charges and discharges the gate capacitance of the power transistor 2, thereby driving the power transistor 2. Therefore, the gate drive circuit 1 has an input terminal T1, a control circuit 4, a first circuit path 5, a second circuit path 6, and a third circuit path 7. In addition, the gate capacitance of the power transistor 2 also includes a parasitic capacitance such as a parasitic capacitance between the gate and the drain.

[0070] The control circuit 4 generates a rectangular wave signal, that is, a gate signal for causing the power transistor 2 to perform switching, and supplies the gate signal to the gate of the power transistor 2 via the input terminal T1 and a parallel circuit of the first circuit path 5, the second circuit path 6, and the third circuit path 7.

[0071] A first circuit path 5 is inserted into a wiring connecting the input terminal Tl and the gate of the power transistor 2. The first circuit path 5 has a diode Dl and a gate resistor Rgon connected in series. The first circuit path 5 contributes mainly to the turn-on and the on state of the power transistor 2 and hardly contributes to the turn-off of the power transistor 2.

[0072] A second circuit path 6 is connected in parallel to the first circuit path 5. The second circuit path 6 has a first capacitor Cl and a first resistor Rl connected in series. The second circuit path 6 has a lower capacity and a lower resistance than the third circuit path 7. The first resistor Rl is a low resistance, and therefore, the second circuit path 6 first discharges a part of the charge from the gate capacitance of the power transistor 2 at a higher speed than the third circuit path 7 during the turn-off of the power transistor 2. The Miller plateau period can be shortened by the high-speed discharge through the second circuit path 6. Also, the amount of the charge discharged at the high speed can be limited by appropriately setting the capacitance value of the first capacitor Cl. For example, the second circuit path 6 discharges a first amount of charge from the gate capacitance of the power transistor 2 during the turn-off of the power transistor 2. The first amount of charge is set to be smaller than a second amount of charge discharged from the gate capacitance of the power transistor 2 from the start of the turn-off of the power transistor 2 to the end of the Miller plateau period of the power transistor 2.

[0073] A third circuit path 7 is connected in parallel to the second circuit path 6. The third circuit path 7 has a second capacitor C2 and a second resistor R2 connected in series. Here, the capacitance value of the second capacitor C2 is larger than that of the first capacitor Cl. The resistance value of the second resistor R2 is larger than that of the first resistor Rl. Also, the resistance value of the gate resistor Rgon is larger than that of the second resistor R2. The third circuit path 7 discharges another part of the charge from the gate capacitance at a lower speed than the second circuit path 6 after the discharge of the second circuit path 6 during the turn-off of the power transistor 2. Accordingly, the current break speed di / dt is reduced, and therefore, the surge voltage can be suppressed.

[0074] Next, the signal waveforms during the turn-off of the power transistor 2 will be described.

[0075] FIG. 2B is a waveform chart showing the gate voltage Vgs, the gate current iG, and the source current Ids of the gate drive circuit according to the comparative example and the embodiment. FIG. 2B The column of (a) comparative example of FIG. 1A corresponds to the gate drive circuit 11 of FIG. 2B The column of (b) embodiment of FIG. 2A corresponds to the gate drive circuit 1 of

[0076] In FIG. 2BIn (a) and (b), time t1 shows a turn-off start point, and time t5 shows a turn-off end point. Times t2 to t3 show a Miller plateau. Time t4 shows a time at which the gate voltage Vgs reaches the threshold voltage Vth. That is, after time t4, the power transistor 2 is in an off state.

[0077] As shown in (b), the gate drive circuit 1 according to the present embodiment shortens the Miller plateau compared to the comparative example of the gate drive circuit 11. FIG. 2B FIG. 1A As shown in (b), the gate drive circuit 1 according to the present embodiment shortens the Miller plateau compared to the comparative example of the gate drive circuit 11.

[0078] The 2nd circuit path 6 contributes to the shortening of the Miller plateau. For example, the capacitance value of the 1st capacitor C1 of the 2nd circuit path 6 is set to be the size of the charge absorption for discharging the gate capacitance from time t1 of the turn-off start to time t3 of the end of the Miller plateau. Also, the 1st resistor R1 is set to be a relatively small resistance value that enables high-speed movement of the charge. Accordingly, the 2nd circuit path 6 discharges the gate capacitance at high speed from the turn-off start at time t1 to the end of the Miller plateau. In this way, the Miller plateau is shortened.

[0079] In addition, the "before the end of the Miller plateau" described above can be "before time t3 at which the gate voltage Vgs reaches the threshold voltage Vth".

[0080] Also, after time t3 or the end of the discharge of the 2nd circuit path 6, the 3rd circuit path 7 discharges the gate capacitance at low speed. The gate voltage Vgs is lower than the threshold voltage at time t4 during the period from time t3 to time t5, and the gate capacitance is discharged at low speed, so the change in the drain current Ids is moderated. Accordingly, the current cutoff speed di / dt is low, so the surge voltage can be suppressed.

[0081] FIG. 3 is a graph showing one example of the gate charge characteristics of the power transistor 2 at the time of turn-off. The horizontal axis of the graph shows the time axis. The vertical axis shows the gate voltage Vg.

[0082] The amount of charge Qg(ON) charged in the gate capacitance when the power transistor 2 is in an on state is represented by the following mathematical expression.

[0083] Qg(ON) = Qgs1 + Qgd + Qgs2

[0084] Here, Qgs1 shows the parasitic capacitance between the gate and the source corresponding to the gate voltage smaller than the threshold value. Qgd shows the parasitic capacitance between the gate and the drain. Qgs2 shows the parasitic capacitance between the gate and the source corresponding to the gate voltage larger than the threshold value.​

[0085] The capacitance value of the first capacitor C1 is set to satisfy the following mathematical formula.

[0086] C1 < (Qgs2 + Qgd)

[0087] More precisely, the first capacitor C1 is set to satisfy the following mathematical expression.

[0088] C1(Vg(t1)-Vg(t2))<(Qgs2+Qgd)

[0089] Here, Vg(t1) shows that FIG. 3 The gate voltage at time t1. Vg(t2) shows, FIG. 3 The left side of the mathematical formula shows the charge represented by the product of the difference between the gate voltage Vg at time t1 and the gate voltage Vg at time t2, and the first capacitor C1. The first capacitor C1 is set such that the charge represented on the left side is smaller than (Qgs2 + Qgd) on the right side. Accordingly, the high-speed discharge of the first capacitor C1 and the first resistor R1 can be stopped before the Miller plateau ends.

[0090] In other words, the first capacitor C1 is set such that when the power transistor 2 is in the on state, the charge on the first capacitor C1 is less than (Qgs2 + Qgd) of the charge Qg of the gate capacitance of the power transistor 2. Accordingly, from the start of the turn-off until the middle of the Miller plateau period, the gate charge of the power transistor 2 can be discharged through the low-resistance second circuit path 6, thereby shortening the Miller plateau period.

[0091] The charge Q(C1_ON) of the first capacitor C1 when the power transistor 2 is in the on state is defined by the following mathematical formula.

[0092] Q(C1_ON) = capacitance value of C1 × (Vdd - Vgs(ON))

[0093] Here, Vdd is the gate drive power supply voltage, and Vgs(ON) is the gate-source voltage when power transistor 2 is turned on.

[0094] The capacitance value of the second capacitor C2 is set to satisfy the following mathematical formula.

[0095] C2>(Qgs1+Qgd+Qgs2)

[0096] In other words, the capacitance value of the second capacitor C2 is set to be greater than the charge Qg(ON)=Qgs1+Qgd+Qgs2 of the gate capacitor when the power transistor 2 is in the on state.

[0097] More specifically, the second capacitor C2 is set to satisfy the following mathematical expression.

[0098] C2(Vg(tl) - Vg(t5)) < (Qgsi + Qgd + Qgs2)

[0099] Here, Vg(tl) shows the gate voltage at time tl of FIG. 3 Vg(t5) shows the gate voltage at time t5 of FIG. 3

[0100] After the first capacitor Cl absorbs the charge amount of Q (Cl_ON) during the off process, the voltage applied to both ends of the first capacitor Cl becomes small, and the amount of current flowing in the first capacitor Cl is smaller than the amount of current flowing in the second capacitor C2. The amount of current flowing in the second capacitor C2 can be adjusted in accordance with the size of the second resistor R2, and the current cutoff speed di / dt can be adjusted.

[0101] Also, in the case where the power transistor 2 is of the p-type gate, the gate resistor Rgon is required in order to determine the gate voltage at the time of conduction. However, it is required that the gate resistor Rgon be set to be larger than the second resistor R2. This is because, if the gate resistor Rgon is smaller than the second resistor R2, the adjustment of the current cutoff speed di / dt based on the resistance value of the second resistor R2 becomes complicated or difficult.

[0102] Also, the diode Dl can make the gate resistor Rgon unable to be energized at the time of the off of the power transistor 2, and the second resistor R2 can easily adjust the current cutoff speed di / dt.

[0103] In addition, in the case where FIG. 2A C1 < C2 and Rl < R2 are satisfied, C1 x Rl < C2 x R2 can also be satisfied instead. Here, C1 x Rl is the time constant of the second circuit path 6, and C2 x R2 is the time constant of the third circuit path 7.

[0104] [2. Operation]

[0105] Next, the operation of the gate drive circuit 1 will be described.

[0106] FIG. 4 is a explanatory diagram showing the case of the gate current of the gate drive circuit 1 according to the embodiment. FIG. 4 ​Figure (a) shows the gate current of power transistor 2 immediately after turn-on. The thick arrows in the figure indicate the main gate current path. The dashed arrows indicate the gate current paths with smaller current volumes than those indicated by the thick arrows. Immediately after turn-on, most of the gate current charges the gate capacitance of power transistor 2 through the second circuit path 6. Simultaneously, a portion of the gate current charges the gate capacitance of power transistor 2 through the first circuit path 5 and the third circuit path 7.

[0107] FIG. 4 Figure (b) shows the stable on-state of power transistor 2. When power transistor 2 is on, the main gate current can be supplied to the gate through the first circuit path 5. At this time, the second circuit path 6 and the third circuit path 7 do not allow DC gate current to pass through.

[0108] FIG. 4 As shown in (c), the power transistor 2 immediately follows the start of the turn-off, for example... FIG. 2B The gate current situation from time t1 to time t3 in (b). Immediately after the turn-off begins, most of the gate current flows in the first resistor R1 and the first capacitor C1 in the second circuit path 6, and a small portion of the gate current flows in the second resistor R2 and the second capacitor C2 in the third circuit path 7. This is because the resistance value of the first resistor R1 is smaller than that of the second resistor R2. According to the gate current indicated by the thick arrow, the gate capacitance is highly released, thus shortening the Miller plateau period. Furthermore, the gate current indicated by the thick arrow does not flow if the first capacitor C1 is fully charged. The capacitance value of the first capacitor C1 is set such that, in FIG. 2B In (b), before time t3, that is, at the end or in the middle of the Miller plateau period, it becomes full.

[0109] FIG. 4 (d) shows the gate current during the period following (c). FIG. 4 In (d), the Miller plateau period has ended, therefore, the gate voltage decreases as the gate capacitance is released. At this time, the first capacitor C1 is fully charged, therefore, no gate current flows in the second circuit path 6. The main gate current flows in the second resistor R2 and the second capacitor C2 in the third circuit path 7. The resistance value of the second resistor R2 is larger than that of the first resistor R1, therefore, the gate current flowing in the third circuit path 7 is limited compared to (c). Accordingly, the current interruption speed di / dt can be reduced, and surge voltage can be suppressed.

[0110] [3. Experimental Results]

[0111] Next, experimental results of the operation of the analog gate drive circuit 1 involved in the embodiment will be explained.

[0112] FIG. 5 This is a diagram showing the experimental results of the gate drive circuit 1 involved in the comparative example and the embodiment. FIG. 5 (b) shows that FIG. 2A The gate drive circuit 1 is shown. Regarding this, FIG. 5 (a) shows that from FIG. 5 In (b) the gate drive circuit 1, the structure of the second circuit path 6 is removed as a comparative example. The removed second circuit path 6 is a circuit consisting of a first capacitor C1 and a first resistor R1, used to rapidly release the gate capacitance of the power transistor 2 during the turn-off process.

[0113] The following settings FIG. 5 The constants of each circuit element in (a) and (b). The gate resistor Rgon in the first circuit path 5 is set to 330Ω. The first capacitor C1 in the second circuit path 6 is set to 2nF, and the first resistor R1 is set to 10Ω. The second capacitor C2 in the third circuit path 7 is set to 4.7nF, and the second resistor R2 is set to 4.7kΩ. Furthermore, FIG. 5 The power transistor 2 in the experiment is a GaN bidirectional switch with a P-type dual-gate structure.

[0114] FIG. 5 The waveforms on the right side of (a) and (b) show the gate voltage Vg1, the drain-source current Is, and the drain-source voltage Vs2s1, as simulated experimental results.

[0115] FIG. 5 In comparative example (a), the Miller plateau period from the turn-off start time t1 to time t2a is 20 μs. Regarding this, FIG. 5 In embodiment (b), the Miller plateau period from the turn-off start time t1 to time t2b of the gate drive circuit 1 is 5 μs.

[0116] Confirmed FIG. 5 The second circuit path 6 of (b) has, with FIG. 5 Compared to (a), it can shorten Miller's plateau period to 1 / 4. Furthermore, as... FIG. 6 As shown in waveform (b), shortening the Miller plateau period suppresses the current Is between the drain and source during the Miller plateau period, and also suppresses the voltage Vs2s1 between the drain and source. In other words, it suppresses the overcurrent of Is between the drain and source during the Miller plateau period, thus preventing the potential damage to power transistor 2.

[0117] Furthermore, other experimental results regarding the operation of the analog gate drive circuit 1 involved in the embodiment will be explained.

[0118] FIG. 6 The figure shows other experimental results of the gate drive circuit involved in the comparative example and the embodiment. FIG. 5 The circuit structures of (b) and (a) are similar to... FIG. 6 (b) and (a) are the same. However, FIG. 5 The constants of each circuit element, and FIG. 6 Different. The following settings... FIG. 5 The constants of each circuit element in (a) and (b). The gate resistor Rgon in the first circuit path 5 is set to 330Ω. The first capacitor C1 in the second circuit path 6 is set to 1.5nF, and the first resistor R1 is set to 7.5Ω. The second capacitor C2 in the third circuit path 7 is set to 4.7nF, and the second resistor R2 is set to 2.2kΩ. Furthermore, with... FIG. 6 same, FIG. 6 The power transistor 2 in the experiment is a GaN bidirectional switch with a P-type dual-gate structure.

[0119] and FIG. 6 Compared to (a), FIG. 6 The Miller plateau period in (b) was shortened to approximately 1 / 4.

[0120] Furthermore, the drain-source current Is, in FIG. 6 In (a), the Miller plateau begins with 8A and increases to 18A at the end of the Miller plateau. In response, the drain-source current Is... FIG. 7A (b) The Miller plateau begins at 8A and ends at 9A, with a small increase. Thus, in FIG. 7A In (b), by shortening the Miller plateau period, the current amount of the drain-source current Is during the Miller plateau period is significantly suppressed. In other words, the overcurrent of the drain-source current Is during the Miller plateau period is significantly suppressed, thus reducing the possibility of damage to the power transistor 2.

[0121] [Variation Example 1]

[0122] Next, a modified example 1 of the gate drive circuit 1 will be described.

[0123] FIG. 2A This is a diagram illustrating a structural example of a power switching system including a gate drive circuit, according to a modified example 1 of the embodiments. FIG. 7A ,and FIG. 2A In comparison, the difference is that diode D1 in circuit path 5 of the first circuit has been removed. The following explanation will focus on the differences to avoid repeating what is already said.

[0124] In circuit path 5 of the first circuit, diode D1 is removed, thus allowing the gate current released from the gate capacitance of power transistor 2 to flow during turn-off. However, the resistance value of the gate resistor Rgon is sufficiently large compared to the second resistor R2; therefore, the gate current flowing in circuit path 5 of the first circuit can be ignored compared to the gate current flowing in circuit path 6 of the second circuit. Therefore, according to FIG. 7B The gate drive circuit 1 of the modified example 1 can also obtain the same as FIG. 7B The same function and effect.

[0125] Furthermore, an example of the operation of the gate drive circuit 1 in Modified Example 1 will be explained.

[0126] FIG. 7B This is a diagram illustrating the operation of the gate drive circuit in Modified Example 1 and the Comparative Example. FIG. 7B (a) shows the gate voltage Vg and gate current Ig of the gate drive circuit 1 of Modified Example 1 at the start of the turn-off (i.e., at the end of the turn-on state). FIG. 7B (b) and (c) correspond to the low-speed gate capacitance release period of the third circuit path 7. That is, FIG. 7B (b) shows the gate voltage Vg and gate current Ig immediately following the high-speed release of the second circuit path 6. FIG. 7B Figure (c) shows the gate voltage Vg and gate current Ig during the slow release period of the third circuit path 7. Additionally, FIG. 7A In this context, Ig@R2 means the gate current Ig flowing in the second resistor R2.

[0127] and, FIG. 7B Comparative examples, from FIG. 7B The circuit example of the gate drive circuit 1 of the modified example 1 in which the second capacitor C2 is deleted is taken as a premise. FIG. 7B Figure (a1) shows the gate voltage Vg and gate current Ig of the gate drive circuit of the comparative example at the start of the turn-off (i.e., at the end of the turn-on state). FIG. 7B (b1) and (c1) correspond to the period of slow gate capacitance release of the second resistor R2. That is, FIG. 8A (b1) shows the gate voltage Vg and gate current Ig immediately following the high-speed release of the second circuit path 6. FIG. 8A (c1) shows the gate voltage Vg and gate current Ig during the slow release period of the third circuit path 7.

[0128] During the low-speed discharge period of the modified example 1 ((b) to (c)), the gate current Ig@R2 changes from 11 V / R2 to 10 V / R2. That is, the rate of change of Ig is approximately 9%. That is, the current cutoff speed di / dt is relatively low. Accordingly, the surge voltage can be suppressed, and the possibility of destruction of the power transistor 2 can be suppressed.

[0129] In this regard, during the low-speed discharge period of the comparative example ((b1) to (c1)), the gate current Ig@R2 changes from 2 V / R2 to 1 V / R2. That is, the rate of change of Ig is approximately 50%. That is, the current cutoff speed di / dt is relatively high. Accordingly, the suppression effect of the surge voltage is small, and the effect of suppressing the possibility of destruction of the power transistor 2 is also small.

[0130] [Modified Example 2]

[0131] Next, a modified example 2 of the gate drive circuit 1 will be described.

[0132] FIG. 7A is a diagram showing a structure example of a power switching system including the modified example 2 of the gate drive circuit according to the embodiment. FIG. 8A , and FIG. 8A The difference is that the power transistor 2 is a MOSFET. That is, the power transistor 2 of FIG. 8B is not a GIT (Gate Insulated Transistor) in which the gate portion is a diode, but a MOSFET having an insulated gate. In this case, in the power transistor 2 of FIG. 8B , there is a gate resistor Rgon, and therefore, the gate voltage when the power transistor 2 is in the on state rises to the voltage of the input terminal T1.

[0133] If, as shown in FIG. 8C , there is no gate resistor Rgon, the gate voltage in the on state of the power transistor 2 becomes a voltage value obtained by dividing the voltage of the input terminal T1 in accordance with the capacitance ratio of the first capacitor C1 and the second capacitor C2 to the gate capacitance. In FIG. 8C , an example in which the gate voltage obtained by dividing 12 V of the input terminal T1 is 6 V is shown.

[0134] If, as shown in FIG. 8A , the gate resistor Rgon is connected in series with the diode D1, there is no discharge path for the charge accumulated in the gate capacitance, and therefore, there is a possibility that a problem occurs in which the gate voltage Vg of the MOSFET does not become zero. However, if FIG. 8C the second capacitor C2 is not present in , the charge of the gate capacitance can be discharged.

[0135] Therefore, in the case where the power transistor 2 is a MOSFET, a suitable structure is FIG. 8C the structure of FIG. 9A the structure in which the second capacitor C2 is not provided.

[0136] In addition, in the case of a p-type gate like a GaN bidirectional switch, the gate itself is a pn diode, and naturally discharges the gate charge through the pn diode, FIG. 9A the structure of

[0137] [Modified Example 3]

[0138] Next, a modified example 3 of the gate drive circuit 1 will be described.

[0139] FIG. 2A is a diagram showing a structure example of a power switching system including the modified example 3 of the gate drive circuit according to the embodiment. FIG. 9B , and FIG. 9B The difference is that a diode D2 is provided instead of the first resistor Rl. Hereinafter, the difference will be described.

[0140] Instead of the low-resistance first resistor Rl for high-speed discharge, the diode D2 is provided, and like the first resistor Rl, high-speed discharge at the time of turn-off is achieved.

[0141] Further, according to the modified example 3, the ringing of the source current and the gate voltage occurring at the time of turn-on can be suppressed. Also, in the modified example 3, the diode D2 is provided, and thus the current flowing from the first capacitor Cl to the gate capacitor during turn-on hardly flows, and the gate current during turn-on flows in the diode Dl and the gate resistor Rgon. By setting the resistance value of the gate resistor Rgon, the speed of turn-on can be adjusted independently of the current breaking speed di / dt at the time of turn-off.

[0142] Also, the main path of the gate current during turn-on is the one with the smaller resistance value between the second resistor R2 and the gate resistor Rgon. In addition, the diode D2 itself also has a capacitance, and thus the current momentarily flows, but generally the capacitance value is small with respect to the first capacitor Cl, and thus this current can be ignored.

[0143] FIG. 10 is a working explanatory diagram of the modified example 3 of the gate drive circuit according to the embodiment. FIG. 10The waveforms of the gate voltage Vgs, the drain voltage Vds, and the drain current Ids in the conduction of the power transistor 2 are shown. In Modification 3, the diode D2 is provided instead of the first resistor Rl, and thus the high-speed charging of the gate capacitance of the first capacitor Cl and the first resistor Rl at the time of turn-on is prohibited. Accordingly, the adjustment of the turn-on speed by the setting of the resistance value of the gate resistor Rgon can be easily achieved.

[0144] [Modification 4]

[0145] Next, Modification 4 of the gate drive circuit 1 will be described.

[0146] FIG. 2A is a diagram showing a structure example of the power switching system including Modification 4 of the gate drive circuit according to the embodiment. FIG. 10 In contrast to FIG. 10 , the difference is that the second capacitor C2 is deleted. Hereinafter, the difference will be described as the center.

[0147] The third circuit path 7 does not have the second capacitor C2, but is constituted by the second resistor R2. The gate current does not receive the DC break action of the second capacitor C2, and thus the input terminal Tl and the gate can be continuously turned on. The third circuit path 7 can release the gate charge in the off state of the power transistor 2 and does not leave the gate charge. Therefore, FIG. 2A The gate drive circuit 1 of FIG. 11A , even if the second capacitor C2 is not present, is the same as FIG. 11B , and can achieve the shortening of the Miller plateau period and the reduction of the current break speed di / dt.

[0148] [Modification 5]

[0149] Next, Modification 5 of the gate drive circuit 1 will be described.

[0150] FIG. 11A is a diagram showing a structure example of the power switching system including Modification 5 of the gate drive circuit according to the embodiment. Also, FIG. 2A is a working explanatory diagram of Modification 5 of the gate drive circuit according to the embodiment.

[0151] FIG. 11B In contrast to FIG. 11A , the difference is that the fourth circuit path 8 is added. Hereinafter, the difference will be described as the center.

[0152] The fourth circuit path 8 is connected in parallel with the third circuit path 7. The fourth circuit path 8 has the third capacitor C3 and the third resistor R3 connected in series. Here, the capacitance of the third capacitor C3 is larger than that of the second capacitor C2. The resistance of the third resistor R3 is larger than that of the second resistor R2.

[0153] In LEGEND the working example, the second circuit path 6 mainly discharges the gate capacitance at the highest speed during the period from the start of the turn-off to the beginning of the Miller plateau. The third circuit path 7 mainly discharges the gate capacitance at a high speed during the Miller plateau. The fourth circuit path 8 mainly discharges the gate capacitance at a low speed during the period from the end of the Miller plateau to the end of the turn-off. Therefore, the capacitance and the resistance satisfy the following mathematical expressions.

[0154] C1 < C2 < C3

[0155] R1 < R2 < R3 < Rgon

[0156] Accordingly, during the turn-off, the main gate current flows in the order of the first capacitor C1, the second capacitor C2, and the third capacitor C3, and is broken in that order when it becomes full. Even in the case where the Miller plateau cannot be shortened sufficiently by only the first capacitor C1, it can be shortened or adjusted sufficiently by the second capacitor C2. The current break speed di / dt after the Miller plateau can be adjusted easily by the third capacitor C3.

[0157] In addition, in ​ the working example, instead of satisfying C1 < C2 < C3 and R1 < R2 < R3, C1 x R1 < C2 x R2 < C3 x R3 can be satisfied. Here, C1 x R1 is the time constant of the second circuit path 6, C2 x R2 is the time constant of the third circuit path 7, and C3 x R3 is the time constant of the fourth circuit path 8.

[0158] As described above, the gate drive circuit 1 according to one aspect of the embodiment includes: an input terminal T1; a first circuit path 5 inserted in a wiring connecting the input terminal T1 and the gate of the power transistor 2; a second circuit path 6 connected in parallel with the first circuit path 5; and a third circuit path 7 connected in parallel with the second circuit path 6. The first circuit path 5 has a gate resistor Rgon. The second circuit path 6 has a first capacitor C1 and a first resistor R1 connected in series. The third circuit path 7 has a second capacitor C2 and a second resistor R2 connected in series. The capacitance of the second capacitor C2 is larger than that of the first capacitor C1. The resistance of the second resistor R2 is larger than that of the first resistor R1. The resistance of the gate resistor Rgon is larger than that of the second resistor R2.

[0159] Accordingly, it is possible to shorten the Miller plateau and suppress the surge voltage (i.e., reduce the current cutoff speed di / dt). That is, it is possible to improve the reliability of the power transistor 2.

[0160] Here, the second circuit path 6 can be configured to discharge a portion of the charge from the gate capacitance of the power transistor 2 during the turn-off of the power transistor 2, and the third circuit path 7 can be configured to discharge another portion of the charge from the gate capacitance of the power transistor 2 at a lower speed than the second circuit path 6 after the discharge by the second circuit path 6 is completed.

[0161] Accordingly, it is possible to shorten the Miller plateau by the high-speed discharge by the second circuit path 6. It is possible to suppress the surge voltage by the low-speed discharge by the third circuit path 7, which reduces the current cutoff speed di / dt.

[0162] Here, the second circuit path 6 can be configured to discharge a first amount of charge from the gate capacitance of the power transistor 2 during the turn-off of the power transistor 2, and the first amount of charge can be set to be smaller than a second amount of charge discharged from the gate capacitance of the power transistor 2 from the start of the turn-off of the power transistor 2 to the end of the Miller plateau of the power transistor 2.

[0163] Accordingly, it is possible to set the period during which the high-speed discharge by the second circuit path 6 is performed within the range of the Miller plateau.

[0164] Here, the first circuit path 5 can include a diode D1 connected in series with the gate resistor Rgon, and the forward direction of the diode D1 can be from the input terminal toward the gate of the power transistor.

[0165] Accordingly, the resistance value of the gate resistor Rgon of the first circuit path 5 is larger than the second resistance R2, and thus, the first circuit path 5 hardly contributes to the discharge during the turn-off of the power transistor 2. Accordingly, the turn-off operation can be set or adjusted by the second circuit path 6 and the third circuit path 7 exclusively.

[0166] Here, the circuitry can further include a fourth circuit path 8 connected in parallel with the third circuit path 7, and the fourth circuit path 8 can include a third capacitor C3 and a third resistor R3 connected in series, the third capacitor C3 can have a larger capacitance value than the second capacitor C2, and the third resistor R3 can have a larger resistance value than the second resistor R2.

[0167] Accordingly, for example, the Miller plateau can be easily adjusted by the third circuit path 7, and the current cutoff speed di / dt can be easily adjusted by the fourth circuit path 8.

[0168] Here, the power transistor 2 can have a P-type gate structure.

[0169] Here, the power transistor 2 can also be a GaN bidirectional switch of a P-type double-gate structure.

[0170] Here, the power transistor 2 can also be a MOSFET.

[0171] Also, the gate drive circuit 1 according to one aspect of the embodiment includes: an input terminal T1; a first circuit path 5 inserted in a wiring 2nd circuit path 6 connecting the input terminal T1 and a gate of the power transistor 2; a second circuit path 6 connected in parallel to the first circuit path 5; and a third circuit path 7 connected in parallel to the second circuit path 6, the first circuit path 5 has a gate resistor Rgon, the second circuit path 6 has a first capacitor C1 and a diode D2 connected in series, the third circuit path 7 has a second capacitor C2 and a second resistor R2 connected in series, the second capacitor C2 has a larger capacitance than the first capacitor C1, and the gate resistor Rgon has a larger resistance than the second resistor R2.

[0172] Accordingly, the Miller plateau period can be shortened and the surge voltage can be suppressed (i.e., the current breaking speed di / dt can be reduced). That is, the reliability of the power transistor 2 can be improved.

[0173] Here, the second circuit path 6 can be configured to discharge a first amount of charge from the gate capacitance of the power transistor 2 during the off process of the power transistor 2, and the first amount of charge can be set to be smaller than a second amount of charge discharged from the gate capacitance of the power transistor 2 from the start of the off process of the power transistor 2 to the end of the Miller plateau period of the power transistor 2.

[0174] Accordingly, the period in which the second circuit path 6 performs the high-speed discharge can be set within the Miller plateau period.

[0175] Here, the first circuit path 5 can also include a diode D1 connected in series with the gate resistor Rgon.

[0176] Accordingly, the gate resistor Rgon of the first circuit path 5 has a larger resistance than the second resistor R2, and thus hardly contributes to the discharge of the off process of the power transistor 2. Therefore, the off operation can be performed by the second circuit path 6 and the third circuit path 7 alone.

[0177] Here, the forward direction of the diode D1 in the first circuit path 5 can be a direction from the input terminal T1 toward the gate of the power transistor, and the forward direction of the diode D2 in the second circuit path 6 can be a direction from the gate of the power transistor toward the input terminal T1.

[0178] Also, the gate drive circuit 1 according to one aspect of the embodiment includes: an input terminal T1; a first circuit path 5 inserted between the input terminal T1 and a wiring 6 connecting a gate of the power transistor 2; a second circuit path 6 connected in parallel to the first circuit path 5; and a third circuit path 7 connected in parallel to the second circuit path 6. The first circuit path 5 has a diode D1 and a gate resistor Rgon connected in series. The second circuit path 6 has a first capacitor C1 and a first resistor R1 connected in series. The third circuit path 7 has a second resistor R2. The resistance value of the second resistor R2 is larger than that of the first resistor R1. The resistance value of the gate resistor Rgon is larger than that of the second resistor R2.

[0179] Accordingly, it is possible to shorten the Miller plateau period and suppress the surge voltage (i.e., reduce the current breaking speed di / dt). That is, it is possible to improve the reliability of the power transistor 2.

[0180] Here, the second circuit path 6 can be configured to release a first amount of charge from the gate capacitance of the power transistor 2 during the off process of the power transistor 2. The first amount of charge can be set to be smaller than a second amount of charge discharged from the gate capacitance of the power transistor 2 from the start of the off process of the power transistor 2 to the end of the Miller plateau period of the power transistor 2.

[0181] Accordingly, it is possible to set the period in which the second circuit path 6 releases the first amount of charge at a high speed within the range of the Miller plateau period.

[0182] Also, the semiconductor circuit breaker according to one aspect of the embodiment includes: the above-described gate drive circuit 1; and the power transistor 2.

[0183] Accordingly, it is possible to shorten the Miller plateau period and suppress the surge voltage (i.e., reduce the current breaking speed di / dt). That is, it is possible to improve the reliability of the power transistor 2.

[0184] The above describes the gate drive circuit according to one or more aspects in accordance with the embodiment, but the present disclosure is not limited to the embodiment. As long as the purpose of the present disclosure is not deviated from, various modified aspects that a person skilled in the art can think of, or aspects configured by combining constituent elements of different embodiments can be included in the range of one or more aspects.

[0185] The gate drive circuit and the semiconductor circuit breaker according to the present disclosure can be used in, for example, a power switching system.

[0186] ​

[0187] 1 Gate drive circuit

[0188] 2 Power transistor

[0189] 3 load circuit

[0190] 4 control circuit

[0191] 5 first circuit path

[0192] 6 second circuit path

[0193] 7 third circuit path

[0194] 8 fourth circuit path

[0195] C1 first capacitor

[0196] C2 second capacitor

[0197] C3 third capacitor

[0198] D1, D2 diode

[0199] R1 first resistor

[0200] R2 second resistor

[0201] R3 third resistor

[0202] Rgon gate resistor

[0203] T1 input terminal

Claims

1. A gate drive circuit, The gate drive circuit includes: an input terminal; a first circuit path inserted in a wiring connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel with the first circuit path; and a third circuit path connected in parallel with the second circuit path, the first circuit path has a gate resistor, the second circuit path has a first capacitor and a first resistor connected in series, the third circuit path has a second capacitor and a second resistor connected in series, the second capacitor has a larger capacitance than the first capacitor, the second resistor has a larger resistance than the first resistor, the gate resistor has a larger resistance than the second resistor.

2. The gate drive circuit according to claim 1, the second circuit path is configured to discharge a part of a charge from a gate capacitance of the power transistor during turn-off of the power transistor, the third circuit path is configured to discharge another part of the charge from the gate capacitance at a lower speed than the second circuit path after the discharge by the second circuit path ends.

3. The gate drive circuit according to claim 1 or 2, the second circuit path is configured to discharge a first amount of charge from the gate capacitance of the power transistor during turn-off of the power transistor, the first amount of charge is set to be smaller than a second amount of charge, which is an amount of charge discharged from the gate capacitance of the power transistor from the start of turn-off of the power transistor to the end of a Miller plateau of the power transistor.

4. The gate drive circuit according to claim 1 or 2, the first circuit path includes a diode connected in series with the gate resistor, a forward direction of the diode is a direction from the input terminal toward the gate of the power transistor.

5. The gate drive circuit according to claim 1 or 2, the gate drive circuit further includes a fourth circuit path connected in parallel with the third circuit path, the fourth circuit path has a third capacitor and a third resistor connected in series, the third capacitor has a larger capacitance than the second capacitor, the third resistor has a larger resistance than the second resistor.

6. The gate drive circuit according to claim 1 or 2, the power transistor has a P-type gate structure.

7. The gate drive circuit according to claim 1 or 2, the power transistor is a GaN bidirectional switch of a P-type double-gate structure.

8. The gate drive circuit according to claim 1 or 2, the power transistor is a MOSFET.

9. A gate drive circuit, The gate drive circuit includes: an input terminal; a first circuit path inserted in a wiring connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel with the first circuit path; and a third circuit path connected in parallel with the second circuit path, the first circuit path has a gate resistor, the second circuit path has a first capacitor and a diode connected in series, the third circuit path has a second capacitor and a second resistor connected in series, The capacitance value of the second capacitor is larger than that of the first capacitor, The resistance value of the gate resistor is larger than that of the second resistor, wherein The diode in the second circuit path has a forward direction from the gate of the power transistor toward the input terminal.

10. The gate drive circuit according to claim 9, The second circuit path is configured to discharge a first amount of charge from the gate capacitance of the power transistor during turn-off of the power transistor, The first amount of charge is set to be smaller than a second amount of charge, which is an amount of charge discharged from the gate capacitance of the power transistor from the start of turn-off of the power transistor to the end of the Miller plateau of the power transistor.

11. The gate drive circuit according to claim 9 or 10, The first circuit path includes a diode connected in series with the gate resistor, wherein The diode in the first circuit path has a forward direction from the input terminal toward the gate of the power transistor.

12. A gate drive circuit, The gate drive circuit includes: an input terminal; a first circuit path inserted in a wiring connecting the input terminal and a gate of a power transistor; a second circuit path connected in parallel with the first circuit path; and a third circuit path connected in parallel with the second circuit path, The first circuit path includes a diode and a gate resistor connected in series, The second circuit path includes a first capacitor and a first resistor connected in series, The third circuit path includes a second resistor, The resistance value of the second resistor is larger than that of the first resistor, The resistance value of the gate resistor is larger than that of the second resistor, wherein, The diode in the first circuit path has a forward direction from the input terminal toward the gate of the power transistor.

13. The gate drive circuit according to claim 12, The second circuit path is configured to discharge a first amount of charge from the gate capacitance of the power transistor during turn-off of the power transistor, The first amount of charge is set to be smaller than a second amount of charge, which is an amount of charge discharged from the gate capacitance of the power transistor from the start of turn-off of the power transistor to the end of the Miller plateau of the power transistor.

14. A semiconductor circuit breaker including: the gate drive circuit according to any one of claims 1 to 13; and the power transistor.

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