Microprocessor with instruction prefetching

Abstract

A microprocessor efficiently performs instruction prefetching, having an instruction cache, a branch predictor, a fetch target queue coupled between the branch predictor and the instruction cache, and a comparator. The instruction cache caches contents for fetching in response to a fetch address. The fetch target queue stores at least one instruction address predicted by the branch predictor to be in a branch direction, to be read out as the fetch address, or output as a plurality of prefetch candidate addresses for selection as a prefetch address to operate the instruction cache for instruction prefetching. The comparator compares the plurality of prefetch candidate addresses with a previous prefetch address to determine which prefetch candidate address is the prefetch address, to exclude instruction prefetching of consecutive instructions of the same cache line.

Description

TECHNICAL FIELD

[0001] The present invention relates to instruction fetching of a microprocessor, and in particular to instruction pre-fetching to speed up instruction fetching. BACKGROUND

[0002] In computer architecture, a branch predictor is usually implemented in digital circuitry to predict the branch of a branch instruction (e.g., an 'if-then-else' conditional branch instruction, a 'call' instruction, a'return' instruction, and a 'jump' instruction). The branch prediction result will guide the instruction fetching from an instruction cache (e.g., an instruction level 1 cache Ll i as well known in the art).

[0003] However, a cache miss can occur in the instruction cache. As a result, instruction pre-fetching is developed. SUMMARY

[0004] The present invention proposes an efficient instruction pre-fetching technique.

[0005] According to an embodiment of the present invention, a microprocessor includes an instruction cache, a branch predictor, a fetch target queue coupled between the branch predictor and the instruction cache, and a comparator. The instruction cache caches instructions for fetching according to a fetch address. The fetch target queue stores at least one instruction address predicted by the branch predictor in a branch direction, to be read out as the fetch address or output as a plurality of pre-fetch candidate addresses for selection as a pre-fetch address to operate the instruction cache for instruction pre-fetching. The comparator compares the plurality of pre-fetch candidate addresses with a previous pre-fetch address to determine which pre-fetch candidate address is the pre-fetch address, so as to exclude instruction pre-fetching of a same cache line consecutively.

[0006] The pre-fetch address of the instruction pre-fetching operation of the microprocessor according to the above embodiment of the present invention is read out from the fetch target queue independently, so as to separate the instruction pre-fetching operation from the instruction fetching operation, and to exclude instruction pre-fetching of a same cache line consecutively by selection of the pre-fetch address, so as to avoid meaningless instruction pre-fetching operation and improve the efficiency of instruction pre-fetching.

[0007] The present invention is described in detail below with reference to the following embodiments and accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 Figure 1 is a block diagram illustrating a hardware implementation of instruction fetching techniques for a microprocessor 100;

[0009] Figure 2 Figure 2 is a block diagram illustrating a microprocessor 200 implemented in accordance with an embodiment of the present application;

[0010] Figure 3 Figure 3 is a block diagram illustrating a hardware implementation of instruction prefetching in accordance with an embodiment of the present application, in which openings made for instruction prefetching are depicted;

[0011] Figure 4 Figure 4 is an implementation of a prefetch read pointer control circuit 308;

[0012] Figure 5 Figure 5 illustrates a prefetch miss replay event; and

[0013] Figure 6 Figure 6 illustrates a prefetch state machine including S, C, I, B, and U levels. DETAILED DESCRIPTION

[0014] The following description sets forth numerous specific details such as particular embodiments, techniques, etc. in order to provide a thorough understanding of the present application. However, those of ordinary skill in the art will appreciate that the present application can be practiced without all the specific details given below. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present application.

[0015] Figure 1 Figure 1 is a block diagram illustrating a hardware implementation of instruction fetching techniques for a microprocessor 100.

[0016] From the instruction cache 104, instructions 102 are fetched based on an instruction fetch address AddrLl i, decoded by a decoder 106, and executed by an execution unit 108. The instruction fetch unit can be 16 bytes (16B), i.e., one instruction fetch address AddrLl i corresponds to a 16B instruction fetch. Unlike conventional techniques in which the instruction cache 104 instruction fetch address AddrLl i is also used for branch prediction, the microprocessor 100 is designed such that branch prediction by a branch predictor 110 is highly advanced of the instruction cache 104 instruction fetch. For example, the branch prediction address AddrBP for branch prediction can not be tied to the instruction fetch address AddrLl i.

[0017] One embodiment is to decouple the instruction cache 104 from the branch predictor 110. Please refer to Figure 1The microprocessor 100 provides a fetch target queue FTQ coupled between the branch predictor 110 and the instruction cache 104 that stores instruction addresses (each corresponding to a fetch unit, such as 16 bytes of instructions) that have completed branch prediction by the branch predictor 110 to be popped (indicated by a fetch read pointer RdPtr) as the instruction cache's 104 fetch addresses AddrLi. The fetch target queue FTQ decouples the branch predictor 110 from the instruction cache 104, allowing the branch predictor 110 to predict branch jumps early, without the meaningless (off-predicted direction) instruction addresses being pushed into the fetch target queue FTQ, and only the meaningful addresses (on-predicted direction) being pushed into the fetch target queue FTQ to form a fetch track for the instruction cache's 104 fetch addresses AddrLi to direct instruction fetching from the instruction cache 104. The fetch target queue FTQ allows the branch predictor 110 to be more highly pipelined than the instruction cache 104.

[0018] There are other sources of the instruction cache's 104 fetch addresses AddrLi. These are discussed below.

[0019] If a branch jump is predicted, the incrementing addresses 118 from the jump target address, incrementing one cycle at a time, are used as the instruction cache's 104 fetch addresses AddrLi to the instruction cache 104 until the contents of the fetch target queue FTQ catch up to the instruction cache's 104 needs.

[0020] In addition, the microprocessor's 100 pipeline can require that the instruction cache's 104 fetch addresses AddrLi be flushed. For example, the branch predictor 110 can be inaccurate, and the fetch track in the fetch target queue FTQ can be wrong. Such an error can be recognized by the microprocessor's 100 pipeline's later stage decoder 106 or execution unit 108. As another example, the decoder 106 or execution unit 108 can also flush when an exception occurs during execution. When a flush is initiated, the decoder 106 or execution unit 108 sends back a flush address 120 or 122 to be used as the instruction cache's 104 fetch addresses AddrLi to the instruction cache 104, and also to the branch predictor 110. In the following cycles, the instruction cache 104 also starts from the flush address 120 / 122 and increments the instruction cache's 104 fetch addresses AddrLi one cycle at a time from the incrementing addresses 118 until the contents of the fetch target queue FTQ catch up to the instruction cache's 104 needs.

[0021] Instruction cache 104 has an instruction lookaside buffer (itlb), a cache list (it_cores), and an instruction cache area (ic_cores). It manages multiple pages of instructions on a single memory location (not shown). Each page of instructions (e.g., managing 4K, 2M, or even 1G instruction addresses, without limitation) can be divided into multiple cache lines, which can be loaded line by line into instruction cache 104. The instruction cache area (ic_cores) is capable of loading multiple cache lines, each cache line including multiple address units (e.g., four address units, each address unit corresponding to a 16-byte instruction). The instruction lookaside buffer (itlb) records the mapping between the logical instruction addresses of previously accessed pages and the physical instruction addresses in that memory location; it can be understood as a cache of page tables. The cache list (it_cores) lists, one by one, which cache lines for these pages have been loaded into the instruction cache area (ic_cores). When the fetch unit corresponding to the fetch address AddrL1i spans a page, it is necessary to access the instruction mapping cache itlb to confirm that the mapping relationship is known before accessing the cache list it_cores and then confirming whether it is a cache line that has been loaded.

[0022] If there is a fetch request for a new page and the corresponding logical-to-physical instruction address mapping is not recorded in the instruction mapping cache itlb, then the instruction mapping cache itlb needs to be updated accordingly. That is, the corresponding logical-to-physical instruction address mapping (i.e., page table) is loaded from that memory. This operation is called table walk.

[0023] The instruction fetch address AddrL1i of a page in the instruction mapping cache itlb is recorded. The cache list it_cores is then queried. If the corresponding cache line (64B) has been loaded into the instruction cache ic_cores (i.e., an icache hit has occurred), then instruction 102 is fetched from the instruction cache ic_cores. Conversely, if the cache list it_cores shows that the cache line corresponding to the fetch address AddrL1i has not yet been loaded into the instruction cache ic_cores (i.e., a fetch icache miss has occurred), then a load request is issued to load the corresponding cache line from memory into the instruction cache ic_cores, and the cache list it_cores is updated with a load record.

[0024] As mentioned earlier, the instruction cache ic_cores may fail to find an instruction, i.e., an instruction failout (fetchicache miss) event occurs. Figure 1 The architecture performs instruction prefetching operations on a cache line basis, based on the prefetch address PfAddr. This pre-loads instructions from memory into the corresponding instruction cache (ic_cores), ensuring sufficient instruction fetch capacity and reducing fetch cache miss events. Figure 1 The prefetch address PfAddr of the architecture is generated by incrementing the fetch address AddrL1i.

[0025] but, Figure 1 The instruction prefetching technique in this architecture has its drawbacks. If a branch instruction exists before the prefetch address PfAddr and a branch is taken, the prefetch address PfAddr incremented from the fetch address AddrL1i is useless. Furthermore, instruction prefetch events compete with fetch events and even other events; only after successful arbitration can the cache list it_cores and the instruction cache ic_cores be used for instruction prefetching. Instruction prefetching cannot occur consistently. Even if the instruction prefetch event competition is successful, instruction prefetching that preempts hardware resources can still negatively impact fetch performance. Additionally, because the prefetch address PfAddr is not directly sent to the instruction mapping cache itlb, if the incremented prefetch address PfAddr exceeds the mapping range recorded in the current instruction mapping cache itlb (e.g., in the case of a page crossover), instruction prefetching will directly fail.

[0026] Figure 2A microprocessor 200 implemented according to one embodiment of the present invention is illustrated using a block diagram. This microprocessor 200 can perform instruction fetching and instruction prefetching in parallel. For this purpose, three additional prefetch candidate address openings are created in the instruction fetch target queue (FTQ). Three prefetch candidate addresses 202 are read according to the prefetch read pointers PfRdPtr1 to PfRdPtr3. The address of a new cache line (different from the previous cache line in the previous prefetch) is used as the prefetch address PfAddr, and instruction prefetching is performed using the instruction cache 204. The instruction mapping cache itlb and cache list it_cores in the instruction cache 204 also have corresponding newly added prefetch address PfAddr openings for dedicated prefetch lookups, enabling instruction fetching and instruction prefetching to be performed in parallel. The prefetch read pointers PfRdPtr1 to PfRdPtr3 are three consecutive pointers pointing to three adjacent entries in the instruction fetch target queue (FTQ). For example, if the prefetch pointer PfRdPtr1 indicates that the Nth entry of the target queue FTQ is to be read, then the prefetch pointer PfRdPtr2 indicates that the (N+1)th entry of the target queue FTQ is to be read, and the prefetch pointer PfRdPtr3 indicates that the (N+2)th entry of the target queue FTQ is to be read, where N is a positive integer.

[0027] In this embodiment, the instruction address stored in the instruction fetch target queue FTQ is used instead of the address generated by incrementing the instruction fetch address AddrL1i as the prefetch address PfAddr. Since the instruction fetch target queue FTQ stores the branch prediction result, which is usually the effective instruction fetch direction, the effective prefetch rate can be greatly improved.

[0028] The dedicated opening within instruction cache 204 for the prefetch address PfAddr allows PfAddr to be directly assigned to the instruction mapping cache itlb and the cache list it_cores, eliminating the need for hardware resource arbitration during instruction prefetching. In the fetch target queue (FTQ), addresses starting from fetch address AddrL1i, as long as they belong to an uncached cache line, can be used as the prefetch address PfAddr. Because there is no need to contend for hardware resources, instruction prefetching can proceed continuously.

[0029] In particular, since instruction prefetching does not require arbitration, cross-page prefetch addresses PfAddr can also be planned. This instruction cache 204 includes multi-stage pipelined hardware configured to support both instruction fetching and instruction prefetching in parallel.

[0030] The instruction mapping cache (itlb) stores the mapping relationship between logical instruction addresses and physical instruction addresses across multiple pages; that is, it acts as a cache for the page table, caching a portion of the complete page table in memory. In one implementation, instructions managed by every 4K instruction addresses constitute a page. The logical instruction address (VA) consists of 48 bits, with the lower 12 bits (bits 11 to 0) representing the page offset. The itlb has 16 entries and 6 way mappings. Bits 15-12 of the logical instruction address (VA) are the entry index of the itlb, and bits 47-16 are the entry tag. Each logical instruction address (VA) maps to a physical instruction address (PA) in that memory, and bits 47-12 of the physical instruction address (PA) are the entry data of the itlb. This invention allows access to the instruction mapping cache itlb when the prefetch address PfAddr crosses a page (bits 47-12 of the logical instruction address VA change). As long as the address mapping for the new page is also stored in the instruction mapping cache itlb, instruction prefetching can be performed on the prefetch address PfAddr for this page crossing. This architecture is particularly helpful for fetching instructions in programs that frequently cross pages.

[0031] In other implementations, the Fetch Target Queue (FTQ) may only require opening one additional read port for instruction prefetching. Other implementations may open a different number of read ports for instruction prefetching. The following discussion will still use the Fetch Target Queue (FTQ) with three additional read ports as an example.

[0032] Figure 3 According to one embodiment of the present invention, the hardware architecture of instruction prefetching is illustrated, wherein the hardware parts involved in the instruction fetching operation are omitted, and the hardware involved in the instruction prefetching operation is simply depicted.

[0033] like Figure 3As shown, the instruction fetch target queue (FTQ) provides up to three prefetch candidate addresses PfAddr1 to PfAddr3 to a comparator 302 based on the prefetch read pointers PfRdPtr1, PfRdPtr2, and PfRdPtr3. Comparator 302 compares these three prefetch candidate addresses PfAddr1 to PfAddr3 with a previous prefetch address CompAddr from the previous prefetch operation to confirm whether the cache lines corresponding to these three prefetch candidate addresses PfAddr1 to PfAddr3 are the same as the cache lines corresponding to the previous prefetch address CompAddr. It then generates an acknowledgment result, i.e., a control signal Pf1 / 2 / 3_C, to indicate which of the three prefetch candidate addresses PfAddr1 to PfAddr3 can be used for prefetching, and sends these signals to logic units 312 and 314 respectively.

[0034] Logic unit 314 counts the number of instruction addresses in the instruction fetch target queue (FTQ) that can be used as prefetch candidates as new addresses are pushed onto the FTQ (in response to the indication signal Ftqpush indicating whether an address has been pushed onto the FTQ) and popped from the FTQ (in response to the control signal Pf1 / 2 / 3_C, which can also be used to indicate whether an address has been popped from the FTQ). This count generates a valid number PfValid_C. This count can be implemented using a counter or a shift register. The valid number PfValid_C indicates whether there are addresses in the FTQ to support the determination of whether instruction prefetching should be performed. Specifically, the valid number PfValid_C represents how many (and / or which) addresses in the FTQ support instruction prefetching. If the valid number PfValid_C is zero, it means that there are no addresses in the FTQ to support instruction prefetching, and therefore instruction prefetching will only be restarted when an instruction address is filled into the FTQ. Logic unit 314 provides the valid number PfValid_C to multiplexer 316. Multiplexer 316 defaults to using the valid number PfValid_C as the C-level valid number Valid_C and outputs the C-level valid number Valid_C to logic unit 312. Logic unit 312 generates a selection signal SEL based on the control signal Pf1 / 2 / 3_C (indicating which of the up to three prefetch candidate addresses PfAddr1 to PfAddr3 can be used for prefetching) and the C-level valid number Valid_C (that is, the valid number PfValid_C, which here indicates whether the up to three prefetch candidate addresses PfAddr1 to PfAddr3 that can be used for prefetching supports prefetching). This selects the multiplexer 310 to output the one that can actually be used for prefetching from the up to three prefetch candidate addresses PfAddr1 to PfAddr3 as the prefetch address PfAddr.

[0035] Furthermore, if comparator 302 determines that more than one of the at most three prefetch candidate addresses PfAddr1 to PfAddr3 corresponds to a cache line different from the cache line corresponding to the previous prefetch address CompAddr, meaning that multiple prefetch candidate addresses PfAddr1 to PfAddr3 correspond to cache lines different from the previous cache line corresponding to the previous prefetch address CompAddr, and all support prefetching, then the multiplexer 310 is controlled by the selection signal SEL to select the earlier prefetch candidate address in the instruction fetch target queue FTQ as the prefetch address PfAddr. If the cache lines corresponding to the at most three prefetch candidate addresses PfAddr1 to PfAddr3 are all the same as the previous cache line, then the instruction prefetch is not performed in that clock cycle.

[0036] In one embodiment, comparator 302 further determines whether the prefetch address PfAddr (one of the three prefetch candidate addresses PfAddr1 to PfAddr3) spans a page by comparing the at most three prefetch candidate addresses PfAddr1 to PfAddr3 with a previous prefetch address CompAddr from the previous prefetch operation, and generates a query request AccessTlb for querying the instruction mapping cache itlb. In one implementation, if the query result is that the instruction mapping cache itlb does not yet have a new page of mapping information (at this time, instruction prefetching will result in an itlb miss), the instruction prefetching operation is paused, and a new page of mapping information is not loaded from memory for prefetching. That is, when an instruction prefetching results in an itlb miss, a tablewalk operation is not performed. This is because loading mapping information from memory involves multiple indexes, which is very time-consuming (hereinafter referred to as the prefetch replay event, indicated by the signal PfReplay). This invention pauses the instruction prefetch operation and replays the prefetch address PfAddr of the current clock cycle. When the instruction fetch operation also reaches this page, the page mapping information is loaded from memory into the instruction mapping cache itlb. The replayed prefetch address PfAddr can then be successfully executed, and instruction prefetching can continue from this prefetch address PfAddr.

[0037] In one implementation, the instruction mapping cache (itlb) stores the mapping between logical instruction addresses of a first page and physical instruction addresses in memory, and the mapping between logical instruction addresses of a second page and physical instruction addresses in memory. When a previous cache line (in one embodiment, the previous prefetch occurred in the previous clock cycle or an earlier clock cycle) belongs to the first page, if a current (in one embodiment, the current clock cycle) prefetch target line belongs to the second page (i.e., instruction prefetching crosses pages, but there is no itlb miss), the instruction mapping cache (itlb) accesses and provides the aforementioned mapping for the second page for use by the instruction prefetch operation. For example, it translates the logical instruction address of the prefetch address PfAddr into a physical instruction address, and queries the cache list (it_cores) with the physical instruction address to determine whether the cache line corresponding to the prefetch address PfAddr has been loaded into memory. Figure 2 The instruction cache ic_cores( Figure 3 (Not shown). In one embodiment, the instruction mapping cache itlb includes at least one opening designed for instruction prefetching, used to query the aforementioned mapping of the second page based on the prefetch address PfAddr that spans to the second page. In one embodiment, if the instruction mapping cache itlb does not store the mapping between the instruction address of a third page and the memory, and a prefetch target line belongs to the third page (i.e., instruction prefetching crosses pages and itlb misses), instruction prefetching is paused and the prefetch address PfAddr of the current clock cycle is replayed until a fetch target line corresponding to the fetch address AddrL1i belongs to the third page, so that the aforementioned mapping of the third page is loaded from memory into the instruction mapping cache itlb. The replayed (possibly repeatedly replayed) prefetch address PfAddr can then be successfully executed, and instruction prefetching can continue from the prefetch address PfAddr onwards.

[0038] Now let's discuss Figure 3 The cache list `it_cores` has an opening designed for instruction prefetching; it is used to check whether the prefetch target line corresponding to the prefetch address `PfAddr` has been loaded. Figure 2 The instruction cache ic_cores( Figure 3(Not shown). If the instruction has not yet been loaded, a signal PfMiss is generated, triggering a load request LoadReq. ​​Multiplexer 304 ensures that a fetch miss event in instruction cache 204 (i.e., the fetch target line corresponding to fetch address AddrL1i has not yet been loaded in the instruction cache ic_cores, represented by the signal FetMiss) takes precedence over a prefetch miss event in instruction cache 204 (i.e., the prefetch target line corresponding to prefetch address PfAddr has not yet been loaded in the instruction cache ic_cores, represented by the signal PfMiss) triggering a load request LoadReq. ​​The triggered load request LoadReq ensures that the missed fetch target line (indicated by FetMiss) is loaded before the missed prefetch target line (indicated by PfMiss).

[0039] Now let's discuss Figure 3The cache replacement logic circuit ilru (ICache LRU) has an opening designed for instruction prefetching. The location in the instruction cache ic_cores where a cache line loaded from memory is placed is determined by the cache replacement logic circuit ilru. For example, the cache line corresponding to the least recently used (LRU) address in the instruction cache ic_cores can be updated by the cache line loaded under the operation of the cache replacement logic circuit ilru. The diagram clearly depicts the opening designed for instruction prefetching in the cache replacement logic circuit ilru. When instruction cache 204 is not found during prefetching, the signal PfMiss raises the enable signal WrEn of the cache replacement logic circuit ilru. In one implementation, the cache replacement logic circuit ilru manages a usage frequency flag for each entry in the instruction cache ic_cores. When an instruction fetch hit occurs, the frequency flag of the corresponding entry is updated (promoted) to indicate that the entry is most recently used, preventing the hit line from being replaced. When loading fetch target rows / prefetch target rows during a fetch miss / prefetch miss, the frequency flag of the filled entries is updated to a default value, indicating that the entry is the most recently used, preventing the loaded fetch target rows / prefetch target rows from being replaced in the next cycle. When a fetch hit and a prefetch miss occur simultaneously, the frequency flag of the corresponding entry is updated (increased) first for the fetch hit case, and then, after selecting the row to be replaced by the loaded prefetch target row, the frequency flag of the corresponding entry is updated (increased) again for the prefetch miss event. By managing this frequency flag, fetch target rows and prefetch target rows can be filled with entries that have low usage rates. Through multiplexer 306, the destination entry LoadWay of the cache line load instruction cache ic_cores can be loaded in response to a prefetch request (prefetch load destination entry PfWay) or in response to an instruction fetch request (fetch load destination entry FetWay).

[0040] For example Figure 3 As shown, instruction cache 204 is pipelined, as further described herein, spanning four pipeline stages: stage C represents the arbitration stage, stage I represents the address access stage, stage B represents the array access stage, and stage U represents the decision cycle stage. These pipeline stages are typically separated by registers R (registers) timed by the core clock. The invention also includes generating a U-level valid number, Valid_U, at stage U. Figure 3As shown, the multiplexer 318 defaults to using the valid number PfValid_U as the U-level valid number Valid_U. The valid number PfValid_U is generated by the logic unit 320 based on the push of new addresses into the instruction fetch target queue FTQ (in response to the indication signal Ftqpush indicating whether an address has been pushed) and the popping of addresses (in response to the control signal Pf1 / 2 / 3_C flowing to the U-level, hereinafter referred to as control signal Pf1 / 2 / 3_U, which can also be used to indicate whether an address has been popped). It indicates how many (and / or which) addresses in the instruction fetch target queue FTQ seen at the U-level support instruction prefetching. Figure 3 As shown, when an instruction prefetch needs to be replayed, the multiplexer 316, in response to the corresponding indication signal PfReplay, uses the U-level valid number Valid_U, which defaults to the valid number PfValid_U, as the C-level valid number Valid_C. In other words, if the instruction prefetch at prefetch address PfAddr is seen to need to be replayed at the U-level, the U-level valid number Valid_U (i.e., the valid number PfValid_U) will be selected by the multiplexer 316 in response to the replay indication signal PfReplay to restore the C-level valid number Valid_C, which has been changed to another value, thus supporting the pull-back of the instruction prefetch at prefetch address PfAddr back to the C-level.

[0041] However, for the instruction prefetch of the prefetch address PfAddr to be pulled back to the C level, the corresponding prefetch read pointer also needs to be pulled back to the C level. Therefore, in one implementation, the prefetch read pointer PfRdPtr1 is also passed along the pipeline hardware to a U-level pipeline hardware, becoming a reset read pointer PfRdPtr_U. Figure 3 (Not shown). When the U-level pipeline hardware determines that the prefetch address PfAddr needs to be replayed (i.e., a prefetch replay event has occurred), it sets the prefetch read pointer PfRdPtr1 using the reset read pointer PfRdPtr_U. How the prefetch read pointer PfRdPtr1 is set using the reset read pointer PfRdPtr_U will be discussed later. Figure 4 Please provide an explanation.

[0042] Furthermore, if the instruction prefetch at prefetch address PfAddr needs to be replayed, the previous prefetch address CompAddr compared by comparator 302 will be the prefetch address PfComAddr that precedes the replayed prefetch address PfAddr. Specifically, multiplexer 308 selects the previous prefetch address PfComAddr as the previous prefetch address CompAddr in response to the replay indication signal PfReplay. This address PfComAddr is the previous prefetch address CompAddr that flowed to the U-level in the previous cycle, and this previous prefetch address CompAddr that flowed to the U-level in the previous cycle was stored in the backup data Backup (not shown) in the previous cycle. In addition, multiplexer 308 can also initialize the previous prefetch address CompAddr with an initial address Start in response to an initialization signal INI, such as an initial address where every bit is 0.

[0043] And, as Figure 3 As shown, the U-level valid number Valid_U indicates the state transition between fetch and prefetch at the U-level, and similarly, the C-level valid number Valid_C also indicates the state transition between fetch and prefetch at the C-level. Multiplexer 316, under the control of the initialization signal INI (which is also the initialization signal INI received by multiplexer 308), selects when to start using the fetch valid number FetValid_C as the C-level valid number Valid_C. Multiplexer 318, also under the control of the initialization signal INI, selects when to start using the fetch valid number FetValid_U (the fetch valid number FetValid_C that flows to the U-level) as the U-level valid number Valid_U. In other words, when the initialization signal INI needs to switch from prefetch to fetch operation, it selects the fetch valid number FetValid_C as the C-level valid number Valid_C and the fetch valid number FetValid_U as the U-level valid number Valid_U to support the fetch operation.

[0044] It is also important to note that the instruction prefetching operation includes checking in advance whether the cache line corresponding to the instruction address is already cached in the instruction cache area `ic_cores`. Therefore, for the same cache line, the instruction prefetching operation must precede the instruction fetching operation; otherwise, it is meaningless. In the aforementioned embodiments of this invention, the instruction prefetching operation is performed independently of the instruction fetching operation, and there may be situations where the instruction prefetching operation lags behind the instruction fetching operation. Therefore... Figure 3A prefetch pointer control circuit 308 is also designed to set the prefetch pointer PfRdPtr1 of the instruction fetch target queue FTQ, so as to ensure that the instruction prefetch operation implemented by the instruction fetch target queue FTQ according to the prefetch address PfAddr supplied by the prefetch pointer PfRdPtr1 does not lag behind the instruction fetch operation implemented according to the instruction fetch address AddrL1i supplied by the instruction fetch pointer RdPtr.

[0045] In one implementation, instruction prefetching is initiated based on an alignment signal Strobe. Based on the pulse generated by the alignment signal Strobe, the prefetch read pointer PfRdPtr1 is aligned with the current fetch read pointer RdPtr. The following describes three events that can cause the alignment signal Strobe to generate a pulse, all of which can be implemented by the prefetch read pointer control circuit 308. How the pulse of the alignment signal Strobe aligns the prefetch read pointer PfRdPtr1 with the current fetch read pointer RdPtr will be discussed later. Figure 4 Please provide an explanation.

[0046] In the first scenario, as the instruction address is filled into the fetch target queue (FTQ), the alignment signal Strobe pulses. If the FTQ does not have an instruction to support prefetching, instruction prefetching pauses. Once the FTQ has an instruction to support prefetching, prefetching resumes, and the alignment signal Strobe pulses again, aligning the prefetch read pointer PfRdPtr1 with the fetch read pointer RdPtr.

[0047] The second scenario occurs when a prefetch miss (represented by the PfMiss signal) event occurs, meaning the target line for prefetching has not yet been loaded into the instruction cache `ic_cores`, but all response buffers (RBs) are occupied. It should be noted that, as... Figure 3As shown, the instruction cache 204 includes a response buffer RB. When a prefetch miss event (represented by the signal PfMiss) occurs, and a prefetch target line LoadData corresponding to the prefetch address PfAddr is loaded from memory into the instruction cache 204, the response buffer RB is used to temporarily store the prefetch target line LoadData. Furthermore, the response buffer RB needs to receive the load request LoadReq generated by the multiplexer 304 and the destination entry LoadWay generated by the multiplexer 306, so that the loaded prefetch target line LoadData is filled into the instruction cache area ic_cores as the backfill target line DataFill, and the records in the cache list it_cores are updated accordingly. In one embodiment, multiple (e.g., four) response buffers (RBs) can be designed to handle multiple (e.g., four) load requests, such as LoadReq1 to LoadReq4 generated by the multiplexer 304.

[0048] When the target line to be prefetched has not yet been loaded into the instruction cache 204, but all response buffers (RBs) are occupied, the instruction prefetch operation is paused. The prefetch address PfAddr is replayed (indicator signal PfReplay is set) to wait for an RB to become available. At this time, the instruction fetch operation may continue normally, even ahead of the paused instruction prefetch operation. Therefore, when an RB becomes available, the alignment signal Strobe generates a pulse, aligning the prefetch read pointer PfRdPtr1 with the current fetch read pointer RdPtr, so that the instruction prefetch operation starts from the instruction address of the current fetch operation, thus avoiding meaningless instruction prefetch operations.

[0049] The third scenario is a fetch replay event, where a fetch is replayed, which adds a prefetch requirement. Here, we'll explain the reasons for fetch failure and replay, which may include, but are not limited to: 1. A fetch-no-instruction event occurs, meaning the instruction corresponding to fetch address AddrL1i cannot be found in the instruction cache ic_cores (fetch icache miss, or fetch miss for short, represented by the FetMiss signal); 2. The instruction mapping cache itlb cannot find the mapping relationship for fetch address AddrL1i (fetch TLB miss); 3. Malfunction of the front-end hardware (e.g., some queues are full, preventing the storage of fetched instructions).

[0050] As described in the third scenario above, the front-end hardware may malfunction, causing instruction fetching to fail and requiring a pause. In the corresponding stopfetch event, the target fetch queue (FTQ) can be flushed. The fetch read pointer RdPtr points to the first entry of the target fetch queue (FTQ), and the alignment signal Strobe is raised, aligning the prefetch pointer PfRdPtr1 with the reset fetch read pointer RdPtr.

[0051] Furthermore, prefetching does not need to be unlimited in advance. In one implementation, the fetching of the same instruction address is counted using a repetition counter, InstrFetGood. When this repetition counter, InstrFetGood, reaches a critical value, indicating that the same instruction segment is being repeatedly fetched (e.g., executing a loop), instruction prefetching can be paused, and the prefetch read pointer, PfRdPtr1, is forcibly set to zero, not pointing to any entry in the instruction target queue, FTQ. If the instruction target is not in the instruction cache, ic_cores (i.e., a fetch icache miss occurs), the repetition counter, InstrFetGood, is cleared, and instruction prefetching is restarted.

[0052] If the repetition count InstrFetGood does not reach a critical value, the prefetch pointer PfRdPtr1 points to the next address entry in PfRdPtr1 / 2 / 3 based on which address in the target queue FQ is selected as the prefetch address PfAddr. For example, if address 1 is selected as the prefetch address PfAddr among addresses 1, 2, and 3, the prefetch pointer PfRdPtr1 updates the entry pointing to address 2 in the target queue FQ; if address 2 is selected as the prefetch address PfAddr among addresses 1, 2, and 3, the prefetch pointer PfRdPtr1 updates the entry pointing to address 3 in the target queue FQ. These entries for addresses 1, 2, and 3 are adjacent, but the values ​​of addresses 1, 2, and 3 do not need to be adjacent. The following will explain... Figure 4 Please provide a detailed explanation.

[0053] Figure 4 As an implementation circuit of the prefetch pointer control circuit 308, this example illustrates how the aforementioned reset read pointer PfRdPtr_U, alignment signal Strobe, and incrementing repeat count InstrFetGood control the prefetch pointer PfRdPtr1.

[0054] Specifically, the counting circuit that generates the repeat count InstrFetGood according to the corresponding instruction cycle includes multiplexers 402 and 404, a buffer R, and an incrementing circuit "+1". The signal Data_ValidU is an indicator signal used to indicate that the instruction fetch is valid, and the signal ILoadReq is another indicator signal indicating that an instruction fetch miss has occurred. When the load request LoadReq is triggered, multiplexers 402 and 404 output the incrementing repeat count InstrFetGood. When the signal ILoadReq indicates that a new instruction fetch request has been received, multiplexer 404 clears the repeat count InstrFetGood.

[0055] The circuit for setting the prefetch pointer PfRdPtr1 includes a shifter Shift, two multiplexers 406 and 408, and a buffer R. Initially, multiplexer 406 directly selects the fetch pointer RdPtr as the prefetch pointer PfRdPtr1 based on the aforementioned alignment signal Strobe, aligning the prefetch pointer PfRdPtr1 with the fetch pointer RdPtr. Under normal operation, the control signal Pf1 / 2 / 3_C, which displays which prefetch pointer is currently selected, is output via shifter Shift to multiplexer 408, buffer R, and multiplexer 406, setting the prefetch pointer PfRdPtr1 for the next cycle. If a prefetched address is replayed, in response to the indication signal PfReplay, the pointer to the replay prefetch stored in the Backup information (i.e., the reset read pointer PfRdPtr_U) is output via multiplexer 408, register R, and multiplexer 406, and set as the prefetch read pointer PfRdPtr1 for the next cycle to support prefetch replay. If the repetition count InstrFetGood reaches a critical value, indicating that the same instruction segment is being repeatedly fetched (e.g., executing a loop), instruction prefetching can be paused, and the prefetch read pointer PfRdPtr1 is forcibly set to zero.

[0056] In one implementation of the prefetch circuit, the prefetch pointer PfRdPtr2 is generated by shifting the prefetch pointer PfRdPtr1 one bit to the left, and the prefetch pointer PfRdPtr3 is generated by shifting the prefetch pointer PfRdPtr1 two bits to the left. Therefore, it is only necessary to configure the corresponding shift circuit to shift the prefetch pointer PfRdPtr1.

[0057] In one prefetch circuit implementation, there are four pipeline stages: C, I, B, and U. If the third condition, where the alignment signal Strobe is pulled up (i.e., a fetch replay event), occurs, the instruction prefetch is also replayed along with the fetch replay, causing the prefetch state machine to return to stage C. The following will explain... Figure 5This example illustrates the process of replaying a failed instruction fetch.

[0058] Figure 5 The example illustrates a fetch failure replay event. Instruction fetch includes four stages: C, I, B, and U, corresponding to the four-stage pipeline Fet_C, Fet_I, Fet_B, and Fet_U. Instruction prefetch includes four stages: C, I, B, and U, corresponding to the four-stage pipeline Pf_C, Pf_I, Pf_B, and Pf_U. In cycles T0 and T1, the fetch target queue FTQ is empty, and no prefetch operation occurs. In cycle T2, instruction addresses C, D, and E are prefetch candidates, and a C-stage prefetch operation (Pf_C) is performed. In cycle T3, the fetch of instruction address A fails. In cycle T4, the fetch of instruction address A is replayed up to stage C, thus creating a prefetch requirement for instruction address B. Pipeline status 502 without using the fetch replay adjustment prefetch procedure of this invention shows that if there is no replay fetch adjustment prefetch procedure for fetch address A, cycle T4 at stage C performs prefetch operations (Pf_C) on prefetch candidates E, F, and G, but does not prefetch instruction address B. This invention uses a fetch replay adjustment prefetch procedure for fetch address A, so pipeline status 504 shows that cycle T4 at stage C performs prefetch operations (Pf_C) on prefetch candidates A, B, and C, and the instruction at instruction address B will be successfully prefetched. When fetching fails and replay occurs, this invention raises the alignment signal Strobe, aligning the prefetch read pointer PfRdPtr1 with the current fetch read pointer RdPtr.

[0059] As described in the second scenario above, instruction fetch failure may be due to the instruction mapping buffer (itlb) not finding (i.e., not yet being ready) the mapping for the fetch address AddrL1i (i.e., a fetch TLB miss occurs). In this case, the mapping required for the prefetch address PfAddr usually also does not exist in the instruction mapping buffer (itlb) (i.e., a prefetch TLB miss occurs). One implementation is to stop both instruction prefetching and instruction fetching, and wait for the instruction mapping buffer (itlb) to be ready (either the mapping required for the address to be fetched, AddrL1i, or the mapping required for the address to be prefetched, PfAddr), then raise the alignment signal Strobe, aligning the prefetch read pointer PfRdPtr1 with the current fetch read pointer RdPtr. Upon restart, instruction prefetching is pulled back to the fetch address AddrL1i at the time the fetch stopped and begins.

[0060] Figure 6 The diagram illustrates a prefetch state machine, including states S (Stop), C, I, B, and U. The symbols “&”, “~”, and “|” represent “AND”, “NOT”, and “OR”, respectively.

[0061] In one implementation, when prefetching is not performed, the prefetch state machine is in state C. After determining the prefetch address PfAddr, the prefetch state machine enters state I, then state B, and then state U. If the prefetch address PfAddr is available for consecutive cycles (PfStartDly0), the prefetch state machine remains in state U, prefetching one cache line per cycle. If the cache line has not yet been prefetched in the instruction cache ic_cores, the prefetch state machine, remaining in state U, will print a load request LoadReq to load the cache line from memory.

[0062] If two prefetches are not consecutive, such as having a 1-cycle interval (PfStartDly1) or a 2-cycle interval, the prefetch state machine jumps back to level B or level I state.

[0063] If a prefetch replay event (PfReplay) occurs, the prefetch state machine jumps from state U back to state C.

[0064] In response to the stopfetch event, the prefetch state machine must first jump to the I-level state and then to the S-level state.

[0065] Whenever a prediction error occurs and a flush is triggered, the corresponding... Figure 6 Branch, the prefetch state machine jumps back to the C-level state.

[0066] For the corresponding fetch replay event, the prefetch state machine must first jump to level I state.

[0067] Additionally, the restart prefetch event PfStart and the prefetch and fetch no candidate event PfFTQEmpty enable the prefetch state machine to switch between states.

[0068] The state machine of this invention offers more flexible state transitions. The prefetch address PfAddr does not necessarily need to sequentially switch through all states, resulting in high prefetch efficiency.

[0069] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A microprocessor, comprising: An instruction cache, the contents of which are used for fetching instructions based on an instruction fetch address; One-branch predictor; A fetch target queue, coupled between the branch predictor and the instruction cache, stores at least one instruction address predicted by the branch predictor in the branch direction, to be read as the fetch address, or outputs as multiple prefetch candidate addresses, to be selected as a prefetch address to operate the instruction cache for instruction prefetching; and A comparator compares the multiple prefetch candidate addresses with a previous prefetch address to determine which prefetch candidate address is the prefetch address, thus excluding instructions that are consecutively prefetched from the same cache line.

2. The microprocessor according to claim 1, wherein: The instruction fetch target queue is coupled to the instruction cache, provides the instruction fetch address, and is also coupled to the instruction cache, providing the multiple prefetch candidate addresses for selection as the prefetch address.

3. The microprocessor according to claim 2, wherein: The fetch address is retrieved from the fetch target queue based on a fetch read pointer; These multiple prefetch candidate addresses are retrieved from the fetch target queue based on a prefetch read pointer; The prefetch pointer is aligned to the fetch pointer according to an alignment signal; as well as The alignment signal is raised when the instruction prefetch restarts after stopping, so that the prefetch read pointer is aligned with the fetch read pointer.

4. The microprocessor according to claim 1, wherein: The instruction cache consists of multiple cache lines, and each cache line contains multiple address units. The instruction address stored in the instruction fetch target queue each corresponds to an instruction fetch unit; and Among the multiple prefetch candidate addresses, the comparator determines that the corresponding cache line is different from the previous prefetched cache line, and selects it as the prefetch address. The cache line corresponding to the prefetch address is then set as a prefetch target line.

5. The microprocessor according to claim 4, wherein: If multiple cache lines corresponding to the multiple prefetch candidate addresses are different from the previous cache line, then the one that is earlier in the fetch target queue is selected as the prefetch address.

6. The microprocessor according to claim 4, wherein: If the cache lines corresponding to the multiple prefetch candidate addresses are all the same as the previous cache line, then instruction prefetching will not be performed.

7. The microprocessor according to claim 4, wherein: The instruction cache includes an instruction mapping cache that stores the mapping between logical instruction addresses of a first page and physical instruction addresses in memory, and the mapping between logical instruction addresses of a second page and physical instruction addresses in memory. Each page's instruction address corresponds to multiple cache lines. If the cached line belongs to the first page, and the prefetch target line belongs to the second page, the instruction mapping cache is accessed to provide the mapping for the second page for the instruction prefetch.

8. The microprocessor according to claim 7, wherein: The instruction mapping cache receives the prefetch address to query the mapping relationship of the second page based on the prefetch address that spans to the second page.

9. The microprocessor according to claim 7, wherein: The instruction mapping cache does not store the mapping relationship between the logical instruction address of the third page and the physical instruction address of the memory; as well as If the prefetch target line belongs to the third page, the instruction prefetch is paused and the prefetch address is replayed until the fetch target line corresponding to the fetch address belongs to the third page, so that the mapping relationship of the third page is loaded from the memory into the instruction mapping relationship cache.

10. The microprocessor according to claim 4, wherein: The instruction cache includes an instruction mapping cache that stores the mapping relationship between the logical instruction addresses of multiple pages and the physical instruction addresses of a memory. The instruction mapping cache receives the fetch address and the prefetch address; Instruction prefetching stops when the instruction mapping cache has not yet prepared the mapping relationship corresponding to the fetch address. Instruction prefetching restarts once the instruction mapping cache has prepared the mapping relationship corresponding to the fetch address.

11. The microprocessor according to claim 1, wherein: The instruction cache includes multi-stage pipelined hardware for parallel instruction fetching and instruction prefetching operations.

12. The microprocessor of claim 1, wherein the instruction cache further comprises: An instruction mapping buffer receives the fetch address and the prefetch address, and stores the mapping relationship between logical instruction addresses and physical instruction addresses for multiple pages.

13. The microprocessor of claim 1, wherein the instruction cache further comprises: A cache list and an instruction cache. The cache list receives the fetch address and the prefetch address to query whether a fetch target line corresponding to the fetch address or a prefetch target line corresponding to the prefetch address has been loaded into the instruction cache.

14. The microprocessor of claim 13, wherein the instruction cache further comprises: A cache substitution logic circuit, when the instruction fetch target line or the prefetch target line has not yet been loaded into the instruction cache, instructs a substitution entry in the instruction cache to be substituted with the instruction fetch target line or the prefetch target line.

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