Excitation control method using registered components

Abstract

The present invention discloses an excitation control method using a register component, creating interfaces and transactions required by a device under test, wherein the transactions correspond to the interfaces; creating a register component in a UVM verification environment, wherein the register component obtains and temporarily stores state information data of the device under test; the register component transmits state information data to other components and objects in the UVM through a UVM transmission component; creating an execution event in an excitation component of the UVM, wherein the excitation component obtains state information data and triggers the execution event through a transmission component; and an execution component in the excitation component generates and controls test excitation using the execution event and state information data. The present invention combines the communication between UVM components and the configuration database to realize the control of the generation and sending of excitation according to the state of the DUT, and provides a new technical route and idea selection for the generation and control of excitation to meet the working habits of different developers.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to an excitation control method for an application register component. Background Art

[0002] Usually, in order to verify the DUT (Device Under Test) designed in RTL (Register Transfer Level), it is necessary to apply corresponding input stimulus to it and verify the DUT by monitoring and comparing its output results. However, in the verification process, it is necessary to be able to decide what kind of stimulus to apply to it next based on the internal state of the DUT. Therefore, the internal state of the DUT needs to be known in the sequence to generate sequence_item.

[0003] In the prior art, there are the following Figure 1 and Figure 2 Two ways to achieve this:

[0004] Figure 1 This is the first implementation method, which is to encapsulate the internal state signal in the DUT into an interface, and then pass it to the verification environment through config_db. At this time, since the sequence stimulus is mounted on the corresponding sequencer, the virtual interface handle of the DUT internal state signal can be obtained in the sequence. The sequence can monitor the value on the interface, and finally decide what kind of stimulus to apply to the DUT next based on the DUT internal state signal.

[0005] Figure 2 This is the second implementation method. In order to verify the correctness of the DUT operation function, a corresponding reference model is usually written, and then the same stimulus is applied to both to compare the output results of the two. If they are consistent, it is considered that the function is in line with expectations. Otherwise, there may be a problem somewhere, which requires further debugging and determination. In simple terms, there should also be an internal state signal corresponding to the DUT in the reference model, so the handle of the reference model is directly passed to the sequencer. Then, since the sequence is mounted on the sequencer, the sequence can get the handle of the reference model, so it can finally decide what kind of stimulus to apply to the DUT next based on the internal state signal of the DUT corresponding to the reference model. Summary of the invention

[0006] According to an embodiment of the present invention, a method for controlling an excitation of an application register component is provided, comprising the following steps:

[0007] Create the interfaces and transactions required by the device under test, where the transactions correspond to the interfaces;

[0008] Create a register component in the UVM verification environment, and the register component obtains and temporarily stores the status information data of the device under test;

[0009] The register component transmits status information data to other components and objects in UVM through the transfer component of UVM;

[0010] Create an execution event in the stimulus component of UVM, and the stimulus component obtains status information data through the transmission component and triggers the execution event;

[0011] The execution component in the stimulus component uses execution events and status information data to generate and control test stimulus.

[0012] Furthermore, the interface includes: an input interface and an output interface, and the input interface and the output interface respectively include a clock control block.

[0013] Furthermore, the storage component obtains and temporarily stores the status information data, including the following sub-steps:

[0014] The UVM package component obtains the status information of the device under test;

[0015] The packaging component packages the state information of the device under test and obtains the state information data;

[0016] The register component obtains and temporarily stores the status information data from the encapsulated component.

[0017] Furthermore, the excitation component obtains the status information data through the transmission component, including the following sub-steps:

[0018] Create a get method in the storage component;

[0019] The stimulus component obtains the handle of the storage component through the transfer component;

[0020] The stimulus component uses the handle of the registered component to call the acquisition method, and the stimulus component uses the acquisition method to obtain status information data.

[0021] According to the excitation control method of the application storage component of the embodiment of the present invention, the generation and sending of the excitation are controlled according to the state of the DUT in combination with the communication between UVM components and the configuration database, which provides a new technical route and idea selection for the generation and control of the excitation to meet the working habits of different developers.

[0022] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic diagram of the principle of one of the excitation control methods using a register component in the prior art;

[0024] Figure 2 It is a schematic diagram of the principle of the second excitation control method using a register component in the prior art;

[0025] Figure 3 A flowchart of an excitation control method using a register component according to an embodiment of the present invention;

[0026] Figure 4 is a flowchart of the sub-steps of step S2 according to an embodiment of the present invention;

[0027] Figure 5 is a flowchart of the sub-steps of step S4 according to an embodiment of the present invention;

[0028] Figure 6 Abstracted DUT example block diagram using the precise matching module as an example;

[0029] Figure 7 A schematic diagram of the principle of an excitation control method using a register component according to an embodiment of the present invention;

[0030] Figure 8 for Figure 7 Schematic diagram of the principle of applying uvm_tlm_analysis_fifo communication. DETAILED DESCRIPTION

[0031] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings to further illustrate the present invention.

[0032] First, combine Figures 3~8 The present invention describes an excitation control method based on UVM (Universal Verification Methodology) according to an embodiment of the present invention, which is used in chip verification and has a wide range of application scenarios.

[0033] like Figure 3 As shown, the excitation control method of the application storage component of the embodiment of the present invention comprises the following steps:

[0034] In S1, Figure 3 , 7 As shown, the interfaces and transactions required by the device under test (DUT) are created, and the transactions correspond to the interfaces.

[0035] Furthermore, the interface includes: an input interface and an output interface, and the input interface and the output interface respectively include a clock control block to facilitate driving and monitoring.

[0036] In S2, if Figure 3 , 7 As shown, a register component (tlm_analysis_fifo) is created in the verification environment (env) of UVM, and the register component (tlm_analysis_fifo) obtains and temporarily stores the status information data of the device under test (DUT).

[0037] Further, the register component (tlm_analysis_fifo) obtains and temporarily stores the status information data including the following sub-steps:

[0038] In S21, if Figure 4 As shown, the packaging component (monitor) of UVM obtains the status information of the device under test (DUT).

[0039] In S22, if Figure 4 As shown, the packaging component (monitor) encapsulates the status information of the device under test (DUT) to obtain status information data.

[0040] In S23, if Figure 4 As shown, the register component (tlm_analysis_fifo) obtains and temporarily stores status information data from the encapsulation component (monitor).

[0041] In S3, such as Figure 3 As shown, the register component (tlm_analysis_fifo) transmits status information data to other components and objects in UVM through the transmission component (config_db) of UVM.

[0042] In S4, Figure 3 As shown, an execution event is created in the stimulus component (sequencer) of UVM, and the stimulus component (sequencer) obtains status information data through the transfer component (config_db) and triggers the execution event.

[0043] Furthermore, the stimulus component (sequencer) obtains the status information data through the transfer component (config_db) including the following sub-steps:

[0044] In S41, if Figure 5 As shown, create an acquisition method in the storage component (tlm_analysis_fifo).

[0045] In S42, if Figure 5 As shown, the stimulus component (sequencer) obtains the handle of the register component (tlm_analysis_fifo) through the transfer component (config_db).

[0046] In S43, if Figure 5 As shown, the stimulus component (sequencer) uses the handle of the storage component (tlm_analysis_fifo) to call the acquisition method, and the stimulus component (sequencer) uses the acquisition method to obtain status information data.

[0047] In S5, Figure 3 As shown, the execution component (sequencer) in the stimulus component (sequencer) generates and controls test stimulus using execution events and status information data, so as to provide more implementation method options for verification personnel in actual chip verification work.

[0048] This embodiment generates and controls the test stimulus for the DUT as follows:

[0049] First, a write request is sent to fill the internal storage space until a write failure occurs, that is, the storage space is full. At this time, the total amount of data written is monitored to see if it is consistent with expectations, thereby helping to determine whether the storage space and write request operations are executed successfully. Then a read request is sent to read (delete) the previously written data until a read (delete) failure occurs, that is, the storage space has been cleared. At this time, the total amount of data written is monitored to see if it is consistent with expectations, and the read data is monitored and compared to see if it is consistent with the previously written data, thereby helping to determine whether the read and write functions are correct.

[0050] like Figure 7 As shown, based on the excitation control method of the application register component of the embodiment of the present invention, it can be known that in the UVM verification platform, this embodiment adds the register component (tlm_analysis_fifo) to the verification environment (env), and obtains the status information data broadcasted by the packaging component (monitor) through the UVM component communication port, and these status information data contain the status information of the DUT, and then gives these status information data to the execution component (sequence), so as to finally realize the generation and control of the input excitation by the execution component (sequence).

[0051] The present invention takes the precise matching module as an example of DUT for illustrative explanation. The precise matching module is used to complete the mapping between key (addr) and pointer (data). The module is often instantiated and used in Ethernet switching chips. For the sake of example, the precise matching module can be simply understood as a typical database with basic write and read (delete) functions.

[0052] Therefore, after abstracting the DUT, its block diagram is as follows Figure 6 As shown, the verification platform corresponding to the DUT is built as follows Figure 6 shown.

[0053] Its input ports are:

[0054] clk: clock signal;

[0055] rst_n: low level reset signal;

[0056] vld: data valid signal;

[0057] cmd: 1'b0: write request signal;

[0058] 1'b1: read (delete) request signal;

[0059] addr: address signal; data: data signal.

[0060] Its output ports are:

[0061] vld: data valid signal;

[0062] rslt: request execution success or failure signal; 1'b0, execution failed; 1'b1, execution successful;

[0063] data: the data corresponding to the previous read (delete) request.

[0064] It can be seen that this patent is still built based on the typical UVM verification platform, but it mainly adds uvm_tlm_analysis_fifo in the env verification environment for communication connection, and uses the UVM configuration database for transmission.

[0065] Further, if Figure 8 As shown, the implementation principle of the present invention is the fifo communication of UVM, and the circular and square mark communication ports in the figure are utilized to complete the communication between component A and component B, so uvm_tlm_analysis_fifo mainly plays a role of data temporary storage and communication connection.

[0066] Further, if Figure 8As shown, component A and uvm_tlm_analysis_fifo are connected through the put series port. Component A calls the interface methods related to the put series port (put, try_put, can_put) to send the transaction data to uvm_tlm_analysis_fifo, and then uvm_tlm_analysis_fifo uses its internally implemented put series interface methods to receive the data sent by component A and cache it in uvm_tlm_analysis_fifo, and uses the put_ap port to broadcast the received data outward; component B and uvm_tlm_analysis_fifo are connected through the get or peek series port. Component B calls the get or peek series method to obtain the transaction data from uvm_tlm_analysis_fifo, and then uvm_tlm_analysis_fifo uses its internally implemented get or peek series interface method to take the data in the cache to component B, and uses the get_ap port to broadcast the data taken out of the cache outward.

[0067] Above, refer to Figures 3~8 The present invention describes an excitation control method for an application register component according to an embodiment of the present invention. The method combines the communication between UVM components and the configuration database to control the generation and sending of excitations according to the state of the DUT, and provides a new technical route and idea selection for the generation and control of excitations to meet the working habits of different developers.

[0068] It should be noted that, in this specification, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprises..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0069] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. An excitation control method using a register component, characterized in that: The following steps are included: Creating interfaces and transactions required by the device under test, wherein the transactions correspond to the interfaces; Creating a register component in a UVM verification environment, wherein the register component obtains and temporarily stores the state information data of the device under test; The register component transmits the status information data to other components and objects in UVM through the transmission component of UVM; Creating an execution event in an excitation component of UVM, wherein the excitation component obtains the state information data through the transmission component and triggers the execution event; The execution component in the stimulus component generates and controls the test stimulus using the execution event and the status information data; The storage component obtains and temporarily stores the status information data, including the following sub-steps: The packaging component of UVM obtains the status information of the device under test; The packaging component encapsulates the state information of the device under test to obtain the state information data; The storage component obtains and temporarily stores the status information data from the packaging component.

2. The method for controlling the excitation of the application register component according to claim 1, characterized in that: The interface includes: an input interface and an output interface, and the input interface and the output interface respectively include a clock control block.

3. The method for controlling the excitation of the application register component according to claim 1, characterized in that: The excitation component obtains the status information data through the transmission component, including the following sub-steps: Creating a get method in the hosting component; The excitation component obtains the handle of the storage component through the transmission component; The excitation component uses the handle of the storage component to call the acquisition method, and the excitation component uses the acquisition method to acquire the status information data.

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