Automatic parameter synchronization method between RTL design and verification environment

Abstract

The present invention discloses a method for automatic parameter synchronization between an RTL design and a verification environment, comprising the following steps: creating an interface package, creating a second parameter with the same name in the interface package according to a first parameter to be synchronized in a DUT; creating a structure variable in the interface package, the structure variable obtaining the first parameter and passing it to a verification environment; binding the interface package and the DUT, specifying parameter connection; before the top-level test build of the verification environment runs, the verification environment obtains the first parameter; obtaining the first parameter in the structure variable in the verification environment, and using the structure variable according to actual project needs. The present invention adopts an improved scheme, automatically synchronizing with RTL design parameters through an interface method in the interface package, thereby saving a lot of debugging time and improving development efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and in particular to a method for automatic parameter synchronization between an RTL design and a verification environment. Background Art

[0002] as follows Figure 1 As shown in the figure, there are usually some design parameters in the RTL (register transfer level) design (DUT in the figure, i.e. design under test). These design parameters are usually used for the logic function design inside the RTL, and these design parameters are also needed in the verification environment to implement the reference model and some check logic. Therefore, in the actual chip verification work, these design parameters in the RTL design are often required to be passed to the verification environment for use. The parameters needed in the RTL design are often not fixed, that is, they will be used as IP (Intellectual Property, a kind of RTL design code that can be commercialized and reused) to pass parameters to instantiate multiple copies for use by different top-level modules. Then the designer usually passes them by defining parameter parameters. Then when the top-level module instantiates the RTL design module, it only needs to specify different parameters when instantiating. However, in some cases, these parameters in the RTL design will not be instantiated multiple times, that is, they will not be set to different parameter values ​​when used as IP. It may be that the local parameter parameters defined by the designer are used for internal fixed designs, but in the early stage, due to the performance considerations of the functional interactors with other modules, the design parameters have not been finalized. The existing solution is to directly define parameter parameters in the verification environment with the same name and value as those in the RTL design, and then use them in the verification environment.

[0003] If the parameter value in the RTL design is modified, the corresponding parameter in the verification environment must also be manually modified. In this case, it is very likely that the designer modified a parameter but forgot to inform the verifier, which caused problems in the verification and debugging process for the verifier, and a lot of debugging time was spent. The result was that the design and verification communication were not synchronized, which reduced the development efficiency. Summary of the invention

[0004] According to an embodiment of the present invention, a method for automatic synchronization of parameters between an RTL design and a verification environment is provided, comprising the following steps:

[0005] Create an interface package, and create a second parameter with the same name in the interface package according to the first parameter to be synchronized in the DUT;

[0006] Create a structure variable in the interface package, the structure variable obtains the first parameter and passes it to the verification environment;

[0007] Bind interface package and DUT, specify parameter connection;

[0008] Before the top-level test build of the verification environment runs, the verification environment obtains the first parameter;

[0009] Get the first parameter in the structure variable in the verification environment and use the structure variable according to the actual project needs.

[0010] Further, the structure variable obtains the first parameter and passes it to the verification environment through the UVM configuration database.

[0011] Further, the parameter connection is specifically designated as follows: a first parameter to be synchronized in the DUT is designated as a second parameter.

[0012] Further, creating a structure variable in the interface package specifically includes: defining the structure variable in the package file of the verification environment, and importing the defined structure variable into the interface package.

[0013] According to the method for automatic parameter synchronization between the RTL design and the verification environment of the embodiment of the present invention, an improved solution is adopted to automatically synchronize with the RTL design parameters through the interface method in the interface package, thereby saving a lot of debugging time and improving development efficiency.

[0014] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the technology as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of transferring design parameters from an RTL design to a verification environment in the prior art.

[0016] Figure 2 The flowchart is a method for automatic synchronization of parameters between RTL design and verification environment according to an embodiment of the present invention.

[0017] Figure 3 Schematic diagram of a method for automatic parameter synchronization between an RTL design and a verification environment according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings to further illustrate the present invention.

[0019] First, combine Figure 2~3A method for automatic parameter synchronization between an RTL design and a verification environment according to an embodiment of the present invention is described, which is used to synchronize parameters in a verification environment and has a wide range of application scenarios.

[0020] like Figure 2~3 As shown, the automatic parameter synchronization method between the RTL design and the verification environment of the embodiment of the present invention has the following steps:

[0021] In S1, Figure 2 As shown, create an interface wrapper, and create a second parameter with the same name in the interface wrapper according to the first parameter that needs to be synchronized in the DUT.

[0022] In S2, if Figure 2 As shown, a structure variable (struct) is created in the interface package, and the structure variable obtains the first parameter and is passed to the verification environment. In this embodiment, creating a structure variable in the interface package is specifically: defining the structure variable in the package file of the verification environment, and importing the defined structure variable into the interface package. Pay attention to the scope of the above structure variable. If the structure variable defined in the package file of the example verification environment is not imported into the interface package, but defined in the interface package, the different scopes of the two will cause errors in obtaining parameters from the UVM configuration database later. And the structure variable obtains the first parameter and is passed to the verification environment through the UVM configuration database.

[0023] In S3, such as Figure 2 As shown, the interface package and the DUT are bound and the parameter connection is specified. In this embodiment, the parameter connection is specifically specified as follows: the first parameter to be synchronized in the DUT is specified to the second parameter.

[0024] In S4, Figure 2 As shown, before the top test build of the verification environment runs, the verification environment obtains the first parameter.

[0025] In S5, Figure 2 As shown, the first parameter in the structure variable is obtained in the verification environment, and the structure variable is used according to the actual project needs.

[0026] Above, refer to Figure 2~3 The present invention describes an automatic parameter synchronization method between an RTL design and a verification environment according to an embodiment of the present invention. An improved scheme is adopted to automatically synchronize with the RTL design parameters through the interface method in the interface package, thereby saving a lot of debugging time and improving development efficiency.

[0027] It should be noted that, in this specification, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprises..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0028] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.

Claims

1. A method for automatic synchronization of parameters between RTL design and verification environment, characterized in that: The following steps are included: Create an interface package, and create a second parameter with the same name in the interface package according to the first parameter to be synchronized in the DUT; Creating a structure variable in the interface package, wherein the structure variable obtains the first parameter and passes it to the verification environment; Binding the interface package and the DUT, and specifying parameter connections; Before a top-level test build of the verification environment is run, the verification environment obtains the first parameter; The first parameter in the structure variable is obtained in the verification environment, and the structure variable is used according to actual project needs.

2. The method for automatic parameter synchronization between RTL design and verification environment as claimed in claim 1, characterized in that: The structure variable obtains the first parameter and passes it to the verification environment through the UVM configuration database.

3. The method for automatic synchronization of parameters between RTL design and verification environment as claimed in claim 1, characterized in that: The designated parameter connection specifically includes: designating the first parameter to be synchronized in the DUT to the second parameter.

4. The method for automatic parameter synchronization between RTL design and verification environment as claimed in claim 1, characterized in that: Creating a structure variable in the interface package specifically includes: defining a structure variable in a package file of the verification environment, and importing the defined structure variable into the interface package.

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