Storage device and operating method thereof

Abstract

Various embodiments of the present disclosure relate to a storage device and an operating method thereof. The storage device includes a memory controller and multiple memory banks, each of which includes multiple memory devices. Each of the multiple memory devices includes: a data selector for selecting and outputting data of a memory device included in any one of the multiple memory banks based on a memory bank select signal; a latch unit for storing data output from the data selector; and a transmission control signal generator for generating a memory bank select signal so that the data stored in the latch unit is sequentially output.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2020-0110504 filed on August 31, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to electronic devices, and more particularly to storage devices and methods of operating the same. Background Art

[0004] A storage device is a device configured to store data and is based on a host device such as a computer, smartphone, or smart tablet. Storage devices include devices configured to store data on a magnetic disk, such as a hard disk drive (HDD), and devices configured to store data in semiconductor memory, particularly non-volatile memory, such as a solid-state drive (SSD) or memory card.

[0005] A storage device may include a memory device configured to store data and a memory controller configured to control the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices. Non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Summary of the Invention

[0006] According to one aspect of the present disclosure, a memory device having a memory controller and a plurality of memory banks is provided, each of the plurality of memory banks including a plurality of memory devices, wherein each of the plurality of memory devices includes: a data selector configured to select and output data of a memory device included in any one of the plurality of memory banks based on a memory bank selection signal; a latch unit configured to store data output from the data selector; and a transmission control signal generator configured to generate a memory bank selection signal so that the data stored in the latch unit is output sequentially.

[0007] According to another aspect of the present disclosure, a method for operating a memory device having a memory controller and multiple memory banks is provided, each of the multiple memory banks including multiple memory devices, the method including: generating a memory bank selection signal, the memory bank selection signal controlling a data selector to select and output data of a memory device included in any one of the multiple memory banks; and based on the memory bank selection signal, storing the data in a latch unit, and then outputting the data to the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art.

[0009] In the accompanying drawings, for clarity of illustration, dimensions may be exaggerated. It will be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements, or one or more intermediate elements may also be present. Throughout the text, identical reference numerals refer to identical elements.

[0010] Figure 1 is a block diagram illustrating a storage device.

[0011] Figure 2 It's a picture Figure 1 A diagram showing the structure of a memory device.

[0012] Figure 3 It's a picture Figure 2 A diagram of one embodiment of a memory cell array is shown.

[0013] Figure 4 is a diagram illustrating a structure in which a plurality of memory banks are connected to a memory controller.

[0014] Figure 5 is a diagram illustrating a process of outputting data with the aid of three stages.

[0015] Figure 6 is a diagram illustrating signals and clocks that control data to be output by means of three stages.

[0016] Figure 7 is a diagram illustrating a process of outputting data with the aid of two stages.

[0017] Figure 8 is a diagram illustrating signals and clocks for controlling data output by two stages.

[0018] Figure 9is a diagram illustrating a process of generating a control signal for outputting data via three stages.

[0019] Figure 10 is a diagram illustrating a process of generating a control signal for outputting data via two stages.

[0020] Figure 11 is a diagram illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0021] Figure 12 is a diagram illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0022] Figure 13 It's a picture Figure 1 A diagram of another embodiment of a memory controller is shown.

[0023] Figure 14 is a block diagram exemplarily illustrating a memory card system to which a storage device is applied according to an embodiment of the present disclosure.

[0024] Figure 15 is a block diagram exemplarily illustrating a solid-state drive (SSD) system to which a storage device is applied according to one embodiment of the present disclosure.

[0025] Figure 16 is a block diagram exemplarily illustrating a user system to which a storage device is applied according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The specific structural or functional descriptions disclosed herein are merely illustrative and are intended to describe embodiments of the concepts of the present disclosure. Embodiments of the concepts of the present disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein.

[0027] It will be understood that although the terms "first," "second," "third," etc. are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of the present disclosure.

[0028] Furthermore, it will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements.

[0029] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily realize the technical spirit of the present disclosure.

[0030] Embodiments provide a memory device capable of reducing transmission time and the amount of current consumed in data transmission, and an operating method of the memory device.

[0031] Figure 1 is a block diagram illustrating a storage device.

[0032] refer to Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 .

[0033] The storage device 50 may be a device that stores data based on the host 300 , such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a television, a tablet computer, or an in-vehicle infotainment system.

[0034] The storage device 50 may be manufactured as any of various types of storage devices based on a host interface (the host interface is a communication scheme with the host 300). For example, the storage device 50 may be implemented using any of a plurality of types of storage devices, such as a solid-state drive device (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro MMC (micro MMC), a secure digital (SD) card, a mini SD card, a micro SD card, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a compact flash (CF) card, a smart media card (SMC), a memory stick, and the like.

[0035] The memory device 50 may be manufactured in any of a variety of package types. For example, the memory device 50 may be manufactured in any of a variety of package types, such as package on package (POP), system-in-package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level fabricated package (WFP), and wafer-level stacked package (WSP).

[0036] In one embodiment, the storage device 50 may include multiple memory banks. The multiple memory banks may include multiple memory devices. Each of the multiple memory banks may be connected to the memory controller 200 via a channel. That is, in the structure of the storage device 50 having multiple memory devices, each of the memory devices may belong to any memory bank and may be connected to the memory controller 200 via a channel.

[0037] The memory device 100 can store data. The memory device 100 operates based on a memory controller 200. The memory device 100 may include a memory cell array having a plurality of memory cells for storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells, and the plurality of memory cells may constitute a plurality of pages. In one embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0038] In one embodiment, the memory device 100 may be a double data rate synchronous dynamic random access memory (DDR SDRAM), a low power double data rate 4 (LPDDR4) SDRAM, a graphics double data rate (GDDR) SRAM, a low power DDR (LPDDR), a Rambus dynamic random access memory (RDRAM), a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a spin transfer torque random access memory (STT-RAM), etc. In this specification, for ease of description, it is assumed and described that the memory device 100 is a NAND flash memory.

[0039] In one embodiment, the memory device 100 can be implemented in a two-dimensional array structure or a three-dimensional array structure. Hereinafter, although the case where the memory device 100 is implemented in a three-dimensional array structure is described as an embodiment, the present disclosure is not limited to the three-dimensional array structure. The present disclosure can be applied not only to a flash memory device in which a charge storage layer is configured with a floating gate (FG), but also to a charge trap flash memory (CTF) in which a charge storage layer is configured with an insulating layer.

[0040] In one embodiment, the memory device 100 may be operated using a single-level cell (SLC) method in which one data bit is stored in one memory cell. Alternatively, the memory device 100 may be operated using a method in which at least two data bits are stored in one memory cell. For example, the memory device 100 may be operated using a multi-level cell (MLC) method in which two data bits are stored in one memory cell, a triple-level cell (TLC) method in which three data bits are stored in one memory cell, or a quad-level cell (QLC) method in which four data bits are stored in one memory cell.

[0041] The memory device 100 can be configured to receive commands and addresses from the memory controller 200 and can access the area selected by the address in the memory cell array. That is, the memory device 100 can perform operations corresponding to the commands on the area selected by the address. For example, the memory device 100 can perform write (program) operations, read operations, and erase operations based on the received commands. For example, when a program command is received, the memory device 100 can program data in the area selected by the address. When a read command is received, the memory device 100 can read data from the area selected by the address. When an erase command is received, the memory device 100 can erase data stored in the area selected by the address.

[0042] In one embodiment, the memory device 100 may include a data selector 171, a latch unit 173, and a data output unit 175. The data selector 171, the latch unit 173, and the data output unit 175 may be connected to each other via a bus.

[0043] The data selector 171 may selectively output data received from the serializer based on a bank select signal. The serializer may be a device that controls data to be sequentially output.

[0044] The latch unit 173 may store data output from the data selector 171, and the data stored in the latch unit 173 may be transmitted to the input / output pin DQ and output to the memory controller 200 via the data output unit 175. In a structure of multiple memory banks, some of the multiple memory banks may share the latch unit 173 and the data output unit 175.

[0045] In one embodiment, the memory device 100 may transmit data to the memory controller 200 via three stages. That is, data may be output to the memory controller 200 by going through three steps. The three steps may mean data output in the data selector 171, the latch unit 173, and the data output unit 175.

[0046] For example, data stored in the memory cell array of the memory device 100 may be transmitted to a serializer to sequentially output the data, and the data output from the serializer may be transmitted from the data selector 171 to the latch unit 173 (first stage) based on a bank select signal. The data stored in the latch unit 173 may be transmitted as input / output data to the data output unit 175 (second stage). The data transmitted to the data output unit 175 may be sequentially output to the memory controller 200 (third stage) based on a received clock.

[0047] However, since data is transferred via three stages, the amount of current consumed by passing through each stage may increase, and output of data may be delayed.

[0048] Therefore, in the present disclosure, a method for merging a plurality of stages to reduce the amount of current consumed in the memory device 100 and prevent output delay of data is proposed.

[0049] In one embodiment, the memory device 100 may include a transmission control signal generator 190. The transmission control signal generator 190 may generate a control signal to output data in a merged-level structure.

[0050] When data is output via three stages, the data is sequentially output based on an external clock. However, in a merged stage structure, data can be output based only on a bank select signal, and thus it may be necessary to generate a bank select signal that outputs data in each stage.

[0051] Therefore, the transmission control signal generator 190 may generate a bank selection signal that outputs data in each stage. In the merged stage structure, data may be sequentially output based on the bank selection signal generated by the transmission control signal generator 190.

[0052] The memory controller 200 may control overall operations of the memory device 50 .

[0053] When the power supply voltage is applied to the memory device 50, the memory controller 200 may execute firmware (FW). When the memory device 100 is a flash memory device, the memory controller 200 may execute FW such as a flash translation layer (FTL) that controls communication between the host 300 and the memory device 100.

[0054] In one embodiment, the memory controller 200 may include firmware (not shown) that receives data and a logical block address LBA from the host 300 and may convert the logical block address LBA into a physical block address PBA, where the physical block address PBA represents an address of a memory cell in the memory device 100 where data is to be stored. In addition, the memory controller 200 may store a logical-physical address mapping table in a buffer memory (not shown), where the logical-physical address mapping table establishes a mapping relationship between the logical block address LBA and the physical block address PBA.

[0055] The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, an erase operation, etc. based on a request from the host 300. For example, when a program request is received from the host 300, the memory controller 200 may change the program request into a program command and may provide the program command, a physical block address PBA, and data to the memory device 100. When a read request and a logical block address LBA are received from the host 300, the memory controller 200 may change the read request into a read command, may select a physical block address PBA corresponding to the logical block address LBA, and may then provide the read command and the physical block address PBA to the memory device 100. When an erase request and a logical block address LBA are received from the host 300, the memory controller 200 may change the erase request into an erase command, may select a physical block address PBA corresponding to the logical block address LBA, and may then provide the erase command and the physical block address PBA to the memory device 100.

[0056] In one embodiment, the memory controller 200 may autonomously generate program commands, addresses, and data without any request from the host 300, and transmit the program commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide the commands, addresses, and data to the memory device 100 to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0057] In one embodiment, the storage device 50 may further include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 300 and the buffer memory. Alternatively, the memory controller 200 may temporarily store system data for controlling the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 300 in the buffer memory, and then transmit the data temporarily stored in the buffer memory to the memory device 100.

[0058] In various embodiments, the buffer memory may be used as a working memory or cache memory of the memory controller 200. The buffer memory may store codes or commands executed by the memory controller 200. Alternatively, the buffer memory may store data processed by the memory controller 200.

[0059] In one embodiment, the buffer memory may be implemented using dynamic random access memory (DRAM), such as double data rate synchronous DRAM (DDR SDRAM), DDR4 SDRAM, low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SRAM, low power DDR (LPDDR), or Rambus dynamic random access memory (RDRAM) or static random access memory (SRAM).

[0060] In various embodiments, a buffer memory may be externally connected to the storage device 50. Thus, a volatile memory device externally connected to the storage device 50 may perform the function of a buffer memory.

[0061] In one embodiment, the memory controller 200 may control at least two memory devices. The memory controller 200 may control the memory devices based on an interleaving technique to improve operation performance.

[0062] The host 300 can communicate with the storage device 50 by using at least one of various communication methods, such as universal serial bus (USB), serial AT attachment (SATA), high-speed inter-chip (HSIC), small computer system interface (SCSI), Firewire, peripheral component interconnect (PCI), PCI Express (PCIe), non-volatile memory express (NVMe), universal flash memory (UFS), secure digital (SD), multimedia card (MMC), embedded MMC (eMMC), dual in-line memory module (DIMM), registered DIMM (RDIMM) and load-reduced DIMM (LRDIMM).

[0063] Figure 2 It's a picture Figure 1 A diagram showing the structure of a memory device.

[0064] refer to Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0065] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 via row lines RL. The plurality of memory blocks BLK1 to BLKz are connected to a page buffer group 123 via bit lines BL1 to BLn. Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. In one embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells connected to the same word line may be defined as a page. Therefore, a memory block may include a plurality of pages.

[0066] The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0067] Each memory cell included in the memory cell array 110 may be configured as a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0068] The peripheral circuit 120 may perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 based on the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn based on the control logic 130, or may discharge the applied voltages.

[0069] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0070] The row decoder 121 can be connected to the memory cell array 110 via row lines RL. The row lines RL can include at least one source select line, a plurality of word lines, and at least one drain select line. In one embodiment, the word lines can include normal word lines and dummy word lines. In one embodiment, the row lines RL can also include pipe select lines.

[0071] The row decoder 121 decodes the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block from the memory blocks BLK1 to BLKz based on the decoded address. In addition, the row decoder 121 may select at least one word line of the selected memory block based on the decoded address and apply the voltage generated by the voltage generator 122 to the at least one word line WL.

[0072] For example, in a program operation, the row decoder 121 may apply a program voltage to a selected word line and a program pass voltage having a level lower than the program voltage level to unselected word lines. In a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a level higher than the verification voltage level to unselected word lines.

[0073] In a read operation, the row decoder 121 may apply a read voltage to a selected word line and apply a read pass voltage having a level higher than the read voltage level to unselected word lines.

[0074] In one embodiment, the erase operation of the memory device 100 can be performed in memory blocks. In the erase operation, the row decoder 121 can select a memory block based on the decoded address. In the erase operation, the row decoder 121 can apply a ground voltage to the word line connected to the selected memory block.

[0075] The voltage generator 122 operates based on the control logic 130. The voltage generator 122 generates a plurality of voltages by using an external power supply voltage supplied to the memory device 100. Specifically, the voltage generator can generate various operating voltages Vop used in programming, reading, and erasing operations based on the operation signal OPSIG. For example, the voltage generator 122 can generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. based on the control logic 130.

[0076] In one embodiment, the voltage generator 122 may generate an internal power supply voltage by regulating an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory device 100.

[0077] In one embodiment, the voltage generator 122 may generate a plurality of voltages by using an external power supply voltage or an internal power supply voltage.

[0078] For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving an internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pumping capacitors based on the control logic 130 .

[0079] The generated plurality of voltages may be provided to the memory cell array 110 through the row decoder 121 .

[0080] The page buffer group 123 may include first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to the memory cell array 110 via first to nth bit lines BL1 to BLn, respectively. The first to nth bit lines BL1 to BLn operate based on the control logic 130. Specifically, the first to nth bit lines BL1 to BLn may operate based on the page buffer control signal PBSIGNALS. For example, the first to nth page buffers PB1 to PBn may temporarily store data received via the first to nth bit lines BL1 to BLn, or sense the voltage or current of the bit lines BL1 to BLn during a read or verify operation.

[0081] Specifically, in a program operation, when a program voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn can transmit data DATA received via the input / output circuit 125 to a selected memory cell via the first to nth bit lines BL1 to BLn. The memory cells of the selected page are programmed based on the transmitted data DATA. In a program verification operation, the first to nth page buffers PB1 to PBn read page data by sensing a voltage or current received from the selected memory cell via the first to nth bit lines BL1 to BLn.

[0082] In a read operation, the first to nth page buffers PB1 to PBn read data DATA from memory cells of a selected page through the first to nth bit lines BL1 to BLn and output the read data DATA to the input / output circuit 125 based on the column decoder 124 .

[0083] In an erase operation, the first to nth page buffers PB1 to PBn may float or apply an erase voltage to the first to nth bit lines BL1 to BLn.

[0084] The column decoder 124 may communicate data between the input / output circuit 125 and the page buffer group 123 based on the column address CADD. For example, the column decoder 124 may communicate data with the first to nth page buffers PB1 to PBn via the data lines DL, or may communicate data with the input / output circuit 125 via the column lines CL.

[0085] The input / output circuit 125 can transfer the data from the memory controller ( Figure 1 The command CMD and the address ADDR received by the control logic 130 as shown in FIG. 200 are transmitted to the control logic 130 , or data DATA is exchanged with the column decoder 124 .

[0086] In a read operation or a verification operation, the sensing circuit 125 may generate a reference current based on the enable bit VRYBIT signal and may output a pass or fail signal PASS / FAIL by comparing the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current.

[0087] The control logic 130 can control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT based on a command CMD and an address ADDR. For example, the control logic 130 can control a read operation of a selected memory block based on a sub-block read command and address. Furthermore, the control logic 130 can control an erase operation of a selected sub-block included in a selected memory block based on a sub-block erase command and address. Furthermore, the control logic 130 can determine whether a verification operation has passed or failed based on a pass or fail signal PASS or FAIL.

[0088] Figure 3 It's a picture Figure 2 A diagram of one embodiment of a memory cell array is shown.

[0089] refer to Figure 2 and Figure 3 , Figure 3 It's a picture Figure 2 1 and 2. A circuit diagram of any one memory block BLKa among a plurality of memory blocks BLK1 to BLKz included in the memory cell array 110 is shown.

[0090] In the memory block BLKa, the first selection line, the word line, and the second selection line arranged in parallel may be connected to each other. For example, the word line may be arranged in parallel between the first selection line and the second selection line. The first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL.

[0091] More specifically, the memory block BLKa may include a plurality of strings connected between bit lines BL1 to BLn and source lines SL. The bit lines BL1 to BLn may be connected to the strings individually, and the source line SL may be commonly connected to the strings. The strings may be configured identically to one another, and thus the string ST connected to the first bit line BL1 will be described in detail as an example.

[0092] The string ST may include a source select transistor SST, a plurality of memory cells F1 to F16, and a drain select transistor DAT connected in series between a source line SL and a first bit line BL1. At least one source select transistor SST and at least one drain select transistor DST may be included in one string ST, and a plurality of memory cells may be included in one string ST, and the number of the plurality of memory cells may be greater than the number of the memory cells F1 to F16 shown in the figure.

[0093] The source of the source select transistor SST may be connected to the source line SL, and the drain of the drain select transistor DAT may be connected to the first bit line BL1. The memory cells F1 to F16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings may be connected to the source select line SSL, and the gates of the drain select transistors DST included in different strings may be connected to the drain select line DSL. The gates of the memory cells F1 to F116 may be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings may be referred to as a physical page PPG. Therefore, a physical page corresponding to the number of word lines WL1 to WL16 may be included in the memory block BLKa.

[0094] A memory cell can store one bit of data. Memory cells are often referred to as single-level cells (SLCs). A physical page PG can store one logical page (LPG) of data. An LPG can include data bits, with the number of data bits corresponding to the number of cells included in a physical page PPG. Alternatively, a memory cell MC can store two or more bits of data. Memory cells are often referred to as multi-level cells (MLCs). A physical page PPG can store two or more LPGs of data.

[0095] A memory cell that stores two or more bits of data is called an MLC. As the number of data bits stored in one memory cell increases, MLC has recently become a memory cell that stores two bits of data. A memory cell that stores three or more bits of data is called a triple-level cell (TLC), and a memory cell that stores four or more bits of data is called a quad-level cell (QLC). In addition, a memory cell that stores multiple bits of data has been developed, and this embodiment can be applied to a memory system that stores two or more bits of data.

[0096] In another embodiment, each of the plurality of memory blocks may have a three-dimensional structure. Each memory block may include a plurality of memory cells stacked on a substrate. The plurality of memory cells may be arranged along +X, +Y, and +Z directions.

[0097] Figure 4 is a diagram illustrating a structure in which a plurality of memory banks are connected to a memory controller.

[0098] refer to Figure 4 , Figure 4 The diagram shows a storage device comprising a plurality of storage banks ( Figure 1 50) structure shown. Figure 4 The first to fourth banks 70_1 to 70_4 shown in FIG may be connected to the memory controller 200 via first to fourth channels CH1 to CH4. That is, the memory devices respectively included in the first to fourth banks 70_1 to 70_4 may communicate with the memory controller 200 via the first to fourth channels CH1 to CH4.

[0099] In one embodiment, each of the first to fourth memory banks 70_1 to 70_4 may include a plurality of memory devices that may store data or output the stored data.

[0100] For example, the first memory bank 70_1 may include first and second memory devices 100_1 and 100_2, the second memory bank 70_2 may include third and fourth memory devices 100_3 and 100_4, the third memory bank 70_3 may include fifth and sixth memory devices 100_5 and 100_7, and the fourth memory bank 70_4 may include seventh and eighth memory devices 100_7 and 100_8.

[0101] Despite Figure 4 , each memory bank includes two memory devices, but each memory bank may include one memory device or three or more memory devices. In addition, the number of memory devices included in the respective memory banks may be different from each other.

[0102] In one embodiment, data stored in the first to fourth memory banks 70_1 to 70_4 may be output to the memory controller 200 via the first to fourth channels CH1 to CH4. Data stored in the first memory bank 70_1 may be output via the first channel CH1, data stored in the second memory bank 70_2 may be output via the second channel CH2, data stored in the third memory bank 70_3 may be output via the third channel CH3, and data stored in the fourth memory bank 70_4 may be output via the fourth channel CH4.

[0103] In one embodiment, since data stored in the first to fourth banks 70_1 to 70_4 cannot be simultaneously output to the memory controller 200 , data stored in the first to fourth banks 70_1 to 70_4 may be sequentially output to the memory controller 200 through three stages.

[0104] First, data stored in the first to eighth memory devices 100_1 to 100_8 included in the first to fourth memory banks 70_1 to 70_4, respectively, may be output to the latch unit (first stage) based on the bank select signal. The data stored in the latch unit may be transmitted as input / output data to the data output unit (second stage), and the data transmitted to the data output unit may be output to the memory controller 200 (third stage) in synchronization with the clock signal.

[0105] However, the amount of current consumed in the process of transmitting data through multiple stages increases. In addition, data may be transmitted through multiple stages, and thus transmission delay may be problematic.

[0106] Therefore, in the present disclosure, a method for merging the above-mentioned stages is proposed.

[0107] Figure 5 is a diagram illustrating a process of outputting data with the aid of three stages.

[0108] refer to Figure 4 and Figure 5 , Figure 5 The output is stored in the first to fourth memory banks ( Figure 4 The process of processing the data in 70_1 to 70_4 shown in FIG. Figure 5 The output is stored in the first to eighth memory devices ( Figure 4 The data in the first to eighth memory devices ( 100_1 to 100_8 ) are stored in the process. Figure 4 The data in 100_1 to 100_8 shown in FIG. 1 can be outputted via three stages, which may represent data output in a data selector, a latch unit, and a data output unit.

[0109] exist Figure 5 In the embodiment, the data selector may be configured as an amplifier, the latch unit may be configured as a latch circuit having an inverter (NOT gate), and the data output unit may be configured as a D flip-flop.

[0110] In one embodiment, the first bank low bit data DATA_B1_LB may represent the first bank ( Figure 4 The first memory device ( 70_1 ) included in Figure 41) and the first bank high bit data DATA_B1_HB may represent data output from the first bank ( Figure 4 The second memory device ( Figure 4 The serializer 100_2 shown in FIG. 100_2 may be a device that controls data to be output sequentially.

[0111] The second memory bank low bit data DATA_B2_LB may indicate that the second memory bank ( Figure 4 The third memory device ( 70_2 ) included in Figure 4 The data output by the serializer 100_3) shown in FIG, and the second memory bank upper data DATA_B2_HB can represent the data output from the second memory bank ( Figure 4 The fourth memory device ( Figure 4 The data output by the serializer 100_4) is shown.

[0112] The third memory bank low bit data DATA_B3_LB may indicate that the data is from the third memory bank ( Figure 4 The fifth memory device ( 70_3 ) included in Figure 4 The data output by the serializer 100_5) shown in FIG, and the third memory bank upper data DATA_B3_HB can represent the data output from the third memory bank ( Figure 4 The sixth memory device ( Figure 4 The data output by the serializer 100_6) is shown.

[0113] The fourth memory bank low bit data DATA_B4_LB may indicate that the fourth memory bank ( Figure 4 The seventh memory device ( 70_4 ) included in Figure 4 100_7) shown in the serializer output data, and the fourth memory bank upper data DATA_B4_HB can represent the fourth memory bank ( Figure 4 The eighth memory device ( Figure 4 The data output by the serializer 100_8) is shown.

[0114] In one embodiment, first bank low-bit data DATA_B1_LB can be output based on a first bank low select signal SEL_B1_LB, and first bank high-bit data DATA_B1_HB can be output based on a first bank high select signal SEL_B1_HB. Furthermore, second bank low-bit data DATA_B2_LB can be output based on a second bank low select signal SEL_B2_LB, and second bank high-bit data DATA_B2_HB can be output based on a second bank high select signal SEL_B2_HB. Third bank low-bit data DATA_B3_LB can be output based on a third bank low select signal SEL_B3_LB, and third bank high-bit data DATA_B3_HB can be output based on a third bank high select signal SEL_B3_HB. Furthermore, fourth bank low-bit data DATA_B4_LB can be output based on a fourth bank low select signal SEL_B4_LB, and fourth bank high-bit data DATA_B4_HB can be output based on a fourth bank high select signal SEL_B3_HB.

[0115] The first bank low selection signal SEL_B1_LB may correspond to the first memory device ( Figure 4 100_1), the first bank high selection signal SEL_B1_HB may correspond to the second memory device ( Figure 4 100_2), the second bank low selection signal SEL_B2_LB may correspond to the third memory device ( Figure 4 100_3 shown), the second bank high selection signal SEL_B2_HB may correspond to the fourth memory device ( Figure 4 100_4 shown), the third bank low selection signal SEL_B3_LB may correspond to the fifth memory device ( Figure 4 100_5), the third bank high selection signal SEL_B3_HB may correspond to the sixth memory device ( Figure 4 100_6), the fourth bank low selection signal SEL_B4_LB may correspond to the seventh memory device ( Figure 4 100_7 shown in FIG), and the fourth bank high selection signal SEL_B4_HB may correspond to the eighth memory device ( Figure 4 100_8 shown in ).

[0116] For example, when the first bank low select signal SEL_B1_LB is received in a high state, the (1_1)th data selector 171_11 may output the first bank low bit data DATA_B1_LB to the fifteenth latch unit 173_15. When the first bank high select signal SEL_B1_HB is received in a high state, the (1_2)th data selector 171_12 may output the first bank high bit data DATA_B1_HB to the twenty-sixth latch unit 173_26.

[0117] In addition, when the second bank low select signal SEL_B2_LB in a high state is received, the (2_3)th data selector 171_23 may output the second bank low bit data DATA_B2_LB to the thirty-seventh latch unit 173_37. When the second bank high select signal SEL_B2_HB in a high state is received, the (2_4)th data selector 171_24 may output the second bank high bit data DATA_B2_HB to the forty-eighth latch unit 173_48.

[0118] When the third bank low select signal SEL_B3_LB is received in a high state, the (3_5)th data selector 171_35 may output the third bank low bit data DATA_B3_LB to the fifteenth latch unit 173_15. When the third bank high select signal SEL_B3_HB is received in a high state, the (3_6)th data selector 171_36 may output the third bank high bit data DATA_B3_HB to the twenty-sixth latch unit 173_26.

[0119] Additionally, when the fourth bank low select signal SEL_B4_LB is received in a high state, the (4_7)th data selector 171_47 may output the fourth bank low-bit data DATA_B4_LB to the thirty-seventh latch unit 173_37. When the fourth bank high select signal SEL_B4_HB is received in a high state, the (4_8)th data selector 171_48 may output the fourth bank high-bit data DATA_B4_HB to the forty-eighth latch unit 173_48.

[0120] exist Figure 5 In the example, since the first memory bank and the third memory bank ( Figure 41 and 70_3) share a latch unit and a data output unit, so either the (1_1)th data selector 171_11 or the (3_5)th data selector 171_35 is selected so that the first bank low-bit data DATA_B1_LB or the third bank low-bit data DATA_B3_LB can be output to the fifteenth latch unit 173_15. The first bank low-bit selection signal SEL_B1_LB and the third bank low-bit selection signal SEL_B3_LB cannot be in a high state at the same time. That is, since only either the first bank low-bit data DATA_B1_LB or the third bank low-bit data DATA_B3_LB can be output, the first bank low-bit selection signal SEL_B1_LB and the third bank low-bit selection signal SEL_B3_LB cannot be in a high state at the same time.

[0121] As described above, any one of the (1_2)th data selector 171_12 and the (3_6)th data selector 171_36 can be selected so that the first bank upper data DATA_B1_HB or the third bank upper data DATA_B3_HB can be output to the twenty-sixth latch unit 173_26. The first bank upper select signal SEL_B1_HB and the third bank upper select signal SEL_B3_HB cannot be in a high state at the same time. That is, since only any one of the first bank upper data DATA_B1_HB and the third bank upper data DATA_B3_HB can be output, the first bank upper select signal SEL_B1_HB and the third bank upper select signal SEL_B3_HB cannot be in a high state at the same time.

[0122] exist Figure 5 In the example, since the second memory bank and the fourth memory bank ( Figure 4 70_2 and 70_4) shown in the shared latch unit and the data output unit, any one of the (2_3) data selector 171_23 and the (4_7) data selector 171_47 can be selected so that the second bank low-bit data DATA_B2_LB or the fourth bank low-bit data DATA_B4_LB can be output to the thirty-seventh latch unit 173_37. The second bank low selection signal SEL_B2_LB and the fourth bank low selection signal SEL_B4_LB cannot be in a high state at the same time. That is, since only any one of the second bank low-bit data DATA_B2_LB and the fourth bank low-bit data DATA_B4_LB can be output, the second bank low selection signal SEL_B2_LB and the fourth bank low selection signal SEL_B4_LB cannot be in a high state at the same time.

[0123] As described above, any one of the (2_4)th data selector 171_24 and the (4_8)th data selector 171_48 is selected, so that the second bank upper data DATA_B2_HB or the fourth bank upper data DATA_B4_HB can be output to the forty-eighth latch unit 173_48. The second bank high selection signal SEL_B2_HB and the fourth bank high selection signal SEL_B4_HB cannot be in a high state at the same time. That is, since only any one of the second bank upper data DATA_B2_HB and the fourth bank upper data DATA_B4_HB can be output, the second bank high selection signal SEL_B2_HB and the fourth bank high selection signal SEL_B4_HB cannot be in a high state at the same time.

[0124] As described above, data selected based on the bank low selection signal or the bank high selection signal is output to the latch unit and may correspond to the first stage among the three stages.

[0125] After the first stage, the data stored in the fifteenth latch unit 173_15, the twenty-sixth latch unit 173_26, the thirty-seventh latch unit 173_37, and the forty-eighth latch unit 173_48 are input / output data, respectively, and the thirteenth lower-bit data IOB13_LB, the thirteenth upper-bit data IOB13_HB, the twenty-fourth lower-bit data IOB24_LB, and the twenty-fourth upper-bit data IOB24_HB can be output to the data output unit, respectively. The data stored in the latch units are output to the data output unit, respectively, which may correspond to the second stage of the three stages.

[0126] After the second stage, the fifteenth data output unit 175_15 can output the thirteenth reference output data DOUT_R_B13 based on the thirteenth low-bit data IOB13_LB and the B13 clock CLK4D_B13, the twenty-sixth data output unit 175_26 can output the thirteenth feedback output data DOUT_F_B13 based on the thirteenth high-bit data IOB13_HB and the B13 clock CLK4D_B13, the thirty-seventh data output unit 175_37 can output the twenty-fourth reference output data DOUT_R_B24 based on the twenty-fourth low-bit data IOB24_LB and the B24 clock CLK4D_B24, and the forty-eighth data output unit 175_48 can output the twenty-fourth feedback output data DOUT_F_B24 based on the twenty-fourth high-bit data IOB24_HB and the B24 clock CLK4D_B24.

[0127] That is, since the data output from the corresponding memory devices are sequentially output to the memory controller ( Figure 4As shown in FIG200 , the fifteenth data output unit 175_15, the twenty-sixth data output unit 175_26, the thirty-seventh data output unit 175_37, and the forty-eighth data output unit 175_48 can sequentially output data based on the clock signal. Data output to each data output unit can correspond to the third stage of the three stages.

[0128] The first to third stages are used to store the data in the first to fourth banks ( Figure 4 The data in 70_1 to 70_4) shown in FIG can be sequentially output to the memory controller ( Figure 4 200 shown).

[0129] Figure 6 is a diagram illustrating signals and clocks that control data output via three stages.

[0130] refer to Figure 5 and Figure 6 , Figure 6 The diagram shows that when data is Figure 5 The data selector, latch unit and data output unit shown in the figure show the status of each signal and output data. Figure 6 , it is assumed that each of the first bank low select signal SEL_B1_LB and the first bank high select signal SEL_B1_HB, the second bank low select signal SEL_B2_LB and the second bank high select signal SEL_B2_HB, the third bank low select signal SEL_B3_LB and the third bank high select signal SEL_B3_HB, and the fourth bank low select signal SEL_B4_LB and the fourth bank high select signal SEL_B4_HB is in the same state. That is, since the selection signal is divided for each bank, it is assumed that the signals SEL_B1_LB and SEL_B1_HB corresponding to the first bank are both in the same state, the signals SEL_B2_LB and SEL_B2_HB corresponding to the second bank are both in the same state, the signals SEL_B3_LB and SEL_B3_HB corresponding to the third bank are both in the same state, and the signals SEL_B4_LB and SEL_B4_HB corresponding to the fourth bank are both in the same state. The first bank low selection signal SEL_B1_LB may correspond to the first memory device ( Figure 4 100_1), the first bank high selection signal SEL_B1_HB may correspond to the second memory device ( Figure 4 100_2), the second bank low selection signal SEL_B2_LB may correspond to the third memory device ( Figure 4100_3 shown), the second bank high selection signal SEL_B2_HB may correspond to the fourth memory device ( Figure 4 100_4 shown), the third bank low selection signal SEL_B3_LB may correspond to the fifth memory device ( Figure 4 100_5), the third bank high selection signal SEL_B3_HB may correspond to the sixth memory device ( Figure 4 100_6), the fourth bank low selection signal SEL_B4_LB may correspond to the seventh memory device ( Figure 4 100_7 shown), and the fourth bank high selection signal SEL_B4_HB may correspond to the eighth memory device ( Figure 4 100_8 shown).

[0131] In one embodiment, in the initial setting, the first bank low select signal SEL_B1_LB and the first bank high select signal SEL_B1_HB may be in a high state. Therefore, the (1_1)th data selector 171_11 may output and store the first bank low bit data DATA_B1_LB in the fifteenth latch unit 173_15 based on the first bank low select signal SEL_B1_LB in a high state. In addition, the (1_2)th data selector 171_12 may output and store the first bank high bit data DATA_B1_HB in the twenty-sixth latch unit 173_26 based on the first bank high select signal SEL_B1_HB in a high state.

[0132] As described above, in the initial setting, the second bank low select signal SEL_B2_LB and the second bank high select signal SEL_B2_HB may be in a high state. Therefore, the (2_3)th data selector 171_23 may output and store the second bank low bit data DATA_B2_LB in the thirty-seventh latch unit 173_37 based on the second bank low select signal SEL_B2_LB in a high state. In addition, the (2_4)th data selector 171_24 may output and store the second bank high bit data DATA_B2_HB in the forty-eighth latch unit 173_48 based on the second bank high select signal SEL_B2_HB in a high state.

[0133] In one embodiment, since the first bank low selection signal SEL_B1_LB, the first bank high selection signal SEL_B1_HB, the second bank low selection signal SEL_B2_LB and the second bank high selection signal SEL_B2_HB are in a high state, the third bank low selection signal SEL_B3_LB, the third bank high selection signal SEL_B3_HB, the fourth bank low selection signal SEL_B4_LB and the fourth bank high selection signal SEL_B4_HB can be in a low state.

[0134] That is, since the (1_1)th data selector 171_11 is selected from the (1_1)th data selector 171_11 and the (3_5)th data selector 171_35, the third bank low select signal SEL_B3_LB may be in a low state. Similarly, since the (1_2)th data selector 171_12 is selected from the (1_2)th data selector 171_12 and the (3_6)th data selector 171_36, the third bank high select signal SEL_B3_HB may be in a low state. In addition, since the (2_3)th data selector 171_23 is selected from the (2_3)th data selector 171_23 and the (4_7)th data selector 171_47, the fourth bank low select signal SEL_B4_LB may be in a low state. Similarly, since the (2_4)th data selector 171_24 is selected from among the (2_4)th data selector 171_24 and the (4_8)th data selector 171_48, the fourth bank high selection signal SEL_B4_HB may be in a low state.

[0135] Since the (1_1)th data selector 171_11 is selected, the first bank lower-bit data DATA_B1_LB stored in the fifteenth latch unit 173_15 can be output as the thirteenth lower-bit data IOB13_LB via the bus, and "F0" can be output to the fifteenth data output unit 175_15. Similarly, since the (1_2)th data selector 171_12 is selected, the first bank upper-bit data DATA_B1_HB stored in the twenty-sixth latch unit 173_26 can be output as the thirteenth upper-bit data IOB13_HB via the bus, and "E1" can be output to the twenty-sixth data output unit 172_26. In addition, since the (2_3)th data selector 171_23 is selected, the second memory bank lower-bit data DATA_B2_LB stored in the thirty-seventh latch unit 173_37 can be output via the bus as the twenty-fourth lower-bit data IOB24_LB, and "D2" can be output to the thirty-seventh data output unit 175_37. Similarly, since the (2_4)th data selector 171_24 is selected, the second memory bank upper-bit data DATA_B2_HB in the forty-eighth latch unit 173_48 can be output via the bus as the twenty-fourth upper-bit data IOB24_HB, and "C3" can be output to the forty-eighth data output unit 175_48.

[0136] Subsequently, when the B13 clock CLK4D_B13 changes from a low state to a high state, the fifteenth data output unit 175_15 may output "F0" as the thirteenth reference output data DOUT_R_B13, and when the B13 clock CLK4D_B13 changes from a high state to a low state, the twenty-sixth data output unit 175_26 may output "E1" as the thirteenth feedback output data DOUT_F_B13. In addition, when the B24 clock CLK4D_B24 changes from a low state to a high state, the thirty-seventh data output unit 175_37 may output "D2" as the twenty-fourth reference output data DOUT_R_B24, and when the B24 clock CLK4D_B24 changes from a high state to a low state, the forty-eighth data output unit 175_48 may output "C3" as the twenty-fourth feedback output data DOUT_F_B24. Therefore, the fifteenth data output unit 175_15, the twenty-sixth data output unit 175_26, the thirty-seventh data output unit 175_37, and the forty-eighth data output unit 175_48 may sequentially output data to the memory controller.

[0137] In one embodiment, the (3_5)th data selector may be selected from the (1_1)th data selector 171_11 and the (3_5)th data selector 171_35, and the (3_6)th data selector 171_36 may be selected from the (1_2)th data selector 171_12 and the (3_6)th data selector 171_36. The third bank low select signal SEL_B3_LB and the third bank high select signal SEL_B3_HB may be in a high state, and the first bank low select signal SEL_B1_LB and the first bank high select signal SEL_B1_HB may be in a low state.

[0138] Since the (3_5)th data selector 171_35 is selected, the third bank lower-bit data DATA_B3_LB stored in the fifteenth latch unit 173_15 can be output as the thirteenth lower-bit data IOB13_LB via the bus, and "B4" can be output to the fifteenth data output unit 175_15. Similarly, since the (3_6)th data selector 171_36 is output, the third bank upper-bit data DATA_B3_HB stored in the twenty-sixth latch unit 173_26 can be output as the thirteenth upper-bit data IOB13_HB via the bus, and "A5" can be output to the twenty-sixth data output unit 175_26.

[0139] In one embodiment, the (4_7)th data selector 171_47 may be selected from the (2_3)th data selector 171_23 and the (4_7)th data selector 171_47, and the (4_8)th data selector 171_48 may be selected from the (2_4)th data selector 171_24 and the (4_8)th data selector 171_48. The fourth bank low select signal SEL_B4_LB and the fourth bank high select signal SEL_B4_HB may be in a high state, and the second bank low select signal SEL_B2_LB and the second bank high select signal SEL_B2_HB may be in a low state.

[0140] Since the (4_7)th data selector 171_47 is selected, the fourth bank lower-bit data DATA_B4_LB stored in the thirty-seventh latch unit 173_37 can be output as the twenty-fourth lower-bit data IOB243_LB via the bus, and "96" can be output to the thirty-seventh data output unit 175_37. Similarly, since the (4_8)th data selector 171_48 is selected, the fourth bank upper-bit data DATA_B4_HB stored in the forty-eighth latch unit 173_48 can be output as the twenty-fourth upper-bit data IOB24_HB via the bus, and "87" can be output to the forty-eighth data output unit 175_48.

[0141] Subsequently, when the B13 clock CLK4D_B13 changes from a low state to a high state, the fifteenth data output unit 175_15 may output "B4" as the thirteenth reference output data DOUT_R_B13, and when the B13 clock CLK4D_B13 changes from a high state to a low state, the twenty-sixth data output unit 175_26 may output "A5" as the thirteenth feedback output data DOUT_F_B13. In addition, when the B24 clock CLK4D_B24 changes from a low state to a high state, the thirty-seventh data output unit 175_37 may output "96" as the twenty-fourth reference output data DOUT_R_B24, and when the B24 clock CLK4D_B24 changes from a high state to a low state, the forty-eighth data output unit 175_48 may output "87" as the twenty-fourth feedback output data DOUT_F_B24. Therefore, the fifteenth data output unit 175_15, the twenty-sixth data output unit 175_26, the thirty-seventh data output unit 175_37, and the forty-eighth data output unit 175_48 may sequentially output data to the memory controller.

[0142] In one embodiment, when the first bank low select signal SEL_B1_LB goes high again, "78" may be output as the thirteenth low-bit data IOB13_LB, and when the third bank low select signal SEL_B3_LB goes high again, "3C" may be output as the thirteenth low-bit data IOB13_LB. Furthermore, when the first bank low select signal SEL_B1_LB goes high again, "F0" may be output as the thirteenth low-bit data IOB13_LB, and when the third bank low select signal SEL_B3_LB goes high again, "B4" may be output as the thirteenth low-bit data IOB13_LB. When the read clock POUT_CLK(RE_N) goes from low to high, the thirteenth low-bit data IOB13_LB may be output in synchronization with the read clock POUT_CLK(RE_N).

[0143] In one embodiment, when the first bank high select signal SEL_B1_HB goes high again, "69" may be output as the thirteenth upper data IOB13_HB, and when the third bank high select signal SEL_B3_HB goes high again, "2D" may be output as the thirteenth upper data IOB13_HB. Additionally, when the first bank high select signal SEL_B1_HB goes high again, "E1" may be output as the thirteenth upper data IOB13_HB, and when the third bank high select signal SEL_B3_HB goes high again, "A5" may be output as the thirteenth upper data IOB13_HB. When the read clock POUT_CLK(RE_N) goes from low to high, the thirteenth upper data IOB13_HB may be output in synchronization with the read clock POUT_CLK(RE_N).

[0144] In one embodiment, when the second bank low select signal SEL_B2_LB goes high again, "5A" may be output as the 24th low-bit data IOB24_LB, and when the fourth bank low select signal SEL_B4_LB goes high again, "1E" may be output as the 24th low-bit data IOB24_LB. Furthermore, when the second bank low select signal SEL_B2_LB goes high again, "D2" may be output as the 24th low-bit data IOB24_LB. When the read clock POUT_CLK(RE_N) goes from low to high, the 24th low-bit data IOB24_LB may be output in synchronization with the read clock POUT_CLK(RE_N).

[0145] In one embodiment, when the second bank high select signal SEL_B2_HB goes high again, "4B" may be output as the 24th upper data IOB24_HB, and when the fourth bank high select signal SEL_B4_HB goes high again, "0F" may be output as the 24th upper data IOB24_HB. Additionally, when the second bank high select signal SEL_B2_HB goes high again, "C3" may be output as the 24th upper data IOB24_HB. When the read clock POUT_CLK(RE_N) goes from low to high, the 24th upper data IOB24_HB may be output in synchronization with the read clock POUT_CLK(RE_N).

[0146] Subsequently, the thirteenth lower bit data IOB13_LB, the thirteenth upper bit data IOB13_HB, the twenty-fourth lower bit data IOB24_LB, and the twenty-fourth upper bit data IOB24_HB may be sequentially output based on the B13 clock CLK4D_B13 and the B24 clock CLK4D_B24.

[0147] For example, when the B13 clock CLK4D_B13 changes from a low state to a high state, the thirteenth lower-bit data IOB13_LB'B4' can be output as the thirteenth reference output data DOUT_R_B13, and when the B13 clock CLK4D_B13 changes from a high state to a low state, the thirteenth upper-bit data IOB13_HB'A5' can be output as the thirteenth feedback output data DOUT_F_B13. Subsequently, when the B24 clock IOB24_LB changes from a low state to a high state, the twenty-fourth lower-bit data IOB24_LB'96' can be output as the twenty-fourth reference output data DOUT_R_B24, and when the B24 clock CLK4D_B24 changes from a high state to a low state, the twenty-fourth upper-bit data IOB24_HB'87' can be output as the twenty-fourth feedback output data DOUT_F_B24.

[0148] When the B13 clock CLK4D_B13 changes from a low state to a high state again, the thirteenth lower-bit data IOB13_LB'78' can be output as the thirteenth reference output data DOUT_R_B13, and when the B13 clock CLK4D_B13 changes from a high state to a low state again, the thirteenth upper-bit data IOB13_HB'69' can be output as the thirteenth feedback output data DOUT_F_B13. Subsequently, when the B24 clock CLK4D_B24 changes from a low state to a high state again, the twenty-fourth lower-bit data IOB24_LB'5A' can be output as the twenty-fourth reference output data DOUT_R_B24, and when the B24 clock IOB24_HB changes from a high state to a low state again, the twenty-fourth upper-bit data IOB24_HB'4B' can be output as the twenty-fourth feedback output data DOUT_F_B24.

[0149] Through the above process, the thirteenth reference output data DOUT_R_B13, the thirteenth feedback output data DOUT_F_B13, the twenty-fourth reference output data DOUT_R_B24, and the twenty-fourth feedback output data DOUT_F_24 can be sequentially output to the memory controller. That is, the selected data can be stored in the fifteenth latch unit 173_15, the twenty-sixth latch unit 173_26, the thirty-seventh latch unit 173_37, and the forty-eighth latch unit 173_48 based on the bank select signal, and the data stored in the fifteenth latch unit 173_15, the twenty-sixth latch unit 173_26, the thirty-seventh latch unit 173_37, and the forty-eighth latch unit 173_48 can be sequentially output to the memory controller based on the B13 clock CLK4D_B13 and the B24 clock CLK4D_B24.

[0150] Figure 7 is a diagram illustrating a process of outputting data with the aid of two stages.

[0151] refer to Figure 5 and Figure 7 , Figure 7 The diagram shows the Figure 5 In the three-stage data output process, the second stage is omitted and the data stored in the latch unit is output as the method of outputting data. The data stored in the latch unit is output to the data output unit by means of the second stage. Figure 7 In the Figure 5 The description of the parts is repeated for the parts shown.

[0152] exist Figure 5 In the embodiment, since data is output via three stages, the amount of current consumed in the process of outputting data increases, and data transmission delay may be caused.

[0153] Therefore, in Figure 7 , a method for merging two stages among three stages, that is, a method for immediately outputting data stored in a latch unit as output data is proposed.

[0154] In one embodiment, when the (1_1)th data selector 171_11 is selected based on the first memory bank low selection signal SEL_B1_LB, the first memory bank low-bit data DATA_B1_LB may be output to the fifteenth latch unit 173_15, and when the (1_2)th data selector 171_12 is selected based on the first memory bank high selection signal SEL_B1_HB, the first memory bank high-bit data DATA_B1_HB may be output to the twenty-sixth latch unit 173_26.

[0155] In addition, when the (2_3)th data selector 171_23 is selected based on the second storage body low selection signal SEL_B2_LB, the second storage body low-bit data DATA_B2_LB can be output to the thirty-seventh latch unit 173_37, and when the (2_4)th data selector 171_24 is selected based on the second storage body high selection signal SEL_B2_HB, the second storage body high-bit data DATA_B2_HB can be output to the forty-eighth latch unit 173_48.

[0156] Similarly, when the (3_5)th data selector 171_35 is selected based on the third storage body low selection signal SEL_B3_LB, the third storage body low-bit data DATA_B3_LB can be output to the fifteenth latch unit 173_15, and when the (3_6)th data selector 171_36 is selected based on the third storage body high selection signal SEL_B3_HB, the third storage body high-bit data DATA_B3 can be output to the twenty-sixth latch unit 173_26.

[0157] In addition, when the (4_7)th data selector 171_47 is selected based on the fourth storage body low selection signal SEL_B4_LB, the fourth storage body low-bit data DATA_B4_LB can be output to the thirty-seventh latch unit 173_37, and when the (4_8)th data selector 171_48 is selected based on the fourth storage body high selection signal SEL_B4_HB, the fourth storage body high-bit data DATA_B4_HB can be output to the forty-eighth latch unit 173_48.

[0158] However, with Figure 5Unlike, data stored in the fifteenth latch unit 173_15 , the twenty-sixth latch unit 173_26 , the thirty-seventh latch unit 173_37 , and the forty-eighth latch unit 173_48 are not transferred to the data output unit but may be immediately output as output data.

[0159] That is, the data stored in the fifteenth latch unit 173_15 may be output to the memory controller as the thirteenth reference output data DOUT_R_B13 ( Figure 4 200 shown), the data stored in the twenty-sixth latch unit 173_26 can be output to the memory controller ( Figure 4 200 shown), the data stored in the thirty-seventh latch unit 173_37 can be output to the memory controller ( Figure 4 200 shown), and the data stored in the forty-eighth latch unit 173_48 can be output to the memory controller ( Figure 4 200 shown).

[0160] However, since the data is not output by the data output unit, the data stored in the fifteenth latch unit 173_15, the twenty-sixth latch unit 173_26, the thirty-seventh latch unit 173_37 and the forty-eighth latch unit 173_48 can be output sequentially based on the first storage body low selection signal SEL_B1_LB, the first storage body high selection signal SEL_B1_HB, the second storage body low selection signal SEL_B2_LB, the second storage body high selection signal SEL_B2_HB, the third storage body low selection signal SEL_B3_LB, the third storage body high selection signal SEL_B3_HB, the fourth storage body low selection signal SEL_B4_LB and the fourth storage body high selection signal SEL_B4_HB.

[0161] Figure 8 is a diagram illustrating signals and clocks that control data output via two stages.

[0162] refer to Figure 7 and Figure 8 , Figure 8 The diagram shows when Figure 7 The status of each signal and output data when data is selected and output in the data selector shown. Figure 8 , the first bank low selection signal SEL_B1_LB may correspond to the first memory device ( Figure 4100_1), the first bank high selection signal SEL_B1_HB may correspond to the second memory device ( Figure 4 100_2), the second bank low selection signal SEL_B2_LB may correspond to the third memory device ( Figure 4 100_3 shown), the second bank high selection signal SEL_B2_HB may correspond to the fourth memory device ( Figure 4 100_4 shown), the third bank low selection signal SEL_B3_LB may correspond to the fifth memory device ( Figure 4 100_5), the third bank high selection signal SEL_B3_HB may correspond to the sixth memory device ( Figure 4 100_6), the fourth bank low selection signal SEL_B4_LB may correspond to the seventh memory device ( Figure 4 100_7) and the fourth bank high selection signal SEL_B4_HB may correspond to the eighth memory device ( Figure 4 100_8 shown).

[0163] In the initial setting, since the first bank low select signal SEL_B1_LB and the first bank high select signal SEL_B1_HB are in a high state, the (1_1)th data selector 171_11 and the (1_2)th data selector 171_12 may be selected.

[0164] Therefore, when the read clock POUT_CLK(RE_N) changes from a low state to a high state, the data output from the (1_1)th data selector 171_11 may be output as the thirteenth reference output data DOUT_R_B13 ('F0'), and when the read clock POUT_CLK(RE_N) changes from a high state to a low state, the data output from the (1_2)th data selector 171_12 may be output as the thirteenth feedback output data DOUT_F_B13 ('E1').

[0165] Subsequently, when the second bank low select signal SEL_B2_LB and the second bank high select signal SEL_B2_HB become a high state, the (2_3)th data selector 171_23 and the (2_4)th data selector 171_24 may be selected.

[0166] Therefore, when the read clock POUT_CLK(RE_N) changes from a low state to a high state, the data output from the (2_3)th data selector 171_23 may be output as the twenty-fourth reference output data DOUT_R_B24('D2'), and when the read clock POUT_CLK(RE_N) changes from a high state to a low state, the data output from the (2_4)th data selector 171_24 may be output as the twenty-fourth feedback output data DOUT_F_B24('C3').

[0167] When the initial setup is completed, when the read clock POUT_CLK (RE_N) changes from a low state to a high state, the third bank low select signal SEL_B3_LB may change to a high state in synchronization with the read clock POUT_CLK (RE_N), and when the read clock POUT_CLK (RE_N) changes from a high state to a low state, the third bank high select signal SEL_B3_HB may change to a high state in synchronization with the read clock POUT_CLK (RE_N). That is, the third bank low select signal SEL_B3_LB and the third bank high select signal SEL_B3_HB may sequentially change to a high state in synchronization with the read clock POUT_CLK (RE_N).

[0168] In addition, when the third storage body low selection signal SEL_B3_LB changes to a high state, the second storage body low selection signal SEL_B2_LB changes to a low state, and when the third storage body high selection signal SEL_B3_HB changes to a high state, the second storage body high selection signal SEL_B2_HB changes to a low state, so that the (4_7)th data selector 171_47 and the (4_8)th data selector 171_48 can be changed to a state in which the (4_7)th data selector 171_47 and the (4_8)th data selector 171_48 can be selected.

[0169] When the third bank low select signal SEL_B3_LB and the third bank high select signal SEL_B3_HB become a high state, the (3_5)th data selector 171_35 and the (3_6)th data selector 171_36 may be selected.

[0170] Therefore, when the read clock POUT_CLK(RE_N) changes from a low state to a high state, the data output from the (3_5)th data selector 171_35 can be output as the thirteenth reference output data DOUT_R_B13('B4'), and when the read clock POUT_CLK(RE_N) changes from a high state to a low state, the data output from the (3_6)th data selector 171_36 can be output as the thirteenth feedback output data DOUT_F_B13('A5').

[0171] Subsequently, when the third bank low select signal SEL_B3_LB changes from a high state to a low state, the fourth bank low select signal SEL_B4_LB may change to a high state, and when the third bank high select signal SEL_B3_HB changes from a high state to a low state, the fourth bank high select signal SEL_B4_HB may change to a high state. That is, in order to sequentially output data, when the third bank low select signal SEL_B3_LB changes to a low state, the fourth bank low select signal SEL_B4_LB may change to a high state, and when the third bank high select signal SEL_B3_HB changes to a low state, the fourth bank high select signal SEL_B4_HB may change to a high state.

[0172] When the fourth bank low select signal SEL_B4_LB and the fourth bank high select signal SEL_B4_HB become a high state, the (4_7)th data selector 171_47 and the (4_8)th data selector 171_48 may be selected.

[0173] Therefore, when the read clock POUT_CLK(RE_N) changes from a low state to a high state, the data output from the (4_7)th data selector 171_47 can be output as the twenty-fourth reference output data DOUT_R_B24('96'), and when the read clock POUT_CLK(RE_N) changes from a high state to a low state, the data output from the (4_8)th data selector 171_48 can be output as the twenty-fourth feedback output data DOUT_F_B24('87').

[0174] Subsequently, when the fourth bank low select signal SEL_B4_LB changes from a high state to a low state, the first bank low select signal SEL_B1_LB may change to a high state, and when the fourth bank high select signal SEL_B4_HB changes from a high state to a low state, the first bank high select signal SEL_B1_HB may change to a high state. That is, in order to sequentially output data, when the fourth bank low select signal SEL_B4_LB changes to a low state, the first bank low select signal SEL_B1_LB may change to a high state, and when the fourth bank high select signal SEL_B4_HB changes to a low state, the first bank high select signal SEL_B1_HB may change to a high state.

[0175] Since the first bank low select signal SEL_B1_LB and the first bank high select signal SEL_B1_HB become the high state again, the (1_1)th data selector 171_11 and the (1_2)th data selector 171_12 may be selected.

[0176] Therefore, when the read clock POUT_CLK(RE_N) changes from a low state to a high state, the data output from the (1_1)th data selector 171_11 can be output as the thirteenth reference output data DOUT_R_B13('78'), and when the read clock POUT_CLK(RE_N) changes from a high state to a low state, the data output from the (1-2)th data selector 171_12 can be output as the thirteenth feedback output data DOUT_F_B13('69').

[0177] Subsequently, when the first bank low select signal SEL_B1_LB changes from a high state to a low state, the second bank low select signal SEL_B2_LB may change to a high state, and when the first bank high select signal SEL_B1_HB changes from a high state to a low state, the second bank high select signal SEL_B2_HB may change to a high state.

[0178] Therefore, when the second bank low selection signal SEL_B2_LB and the second bank high selection signal SEL_B2_HB become high, the (2_3)th data selector 171_23 and the (2_4)th data selector 171_24 may be selected again. When the read clock POUT_CLK (RE_N) changes from a low state to a high state, the data output from the (2_3)th data selector 171_23 may be output as the twenty-fourth reference output data DOUT_R_B24 ('5A'), and when the read clock POUT_CLK (RE_N) changes from a high state to a low state, the data output from the (2_4)th data selector 171_24 may be output as the twenty-fourth feedback output data DOUT_F_B24 ("4B").

[0179] As described above, in the subsequent data output process, the thirteenth reference output data DOUT_R_B13, the thirteenth feedback output data DOUT_F_B13, the twenty-fourth reference output data DOUT_R_B24, and the twenty-fourth feedback output data DOUT_F_B24 can be sequentially output. That is, after "4B" is output as the twenty-fourth feedback output data DOUT_F_B24, '3C', '2D', '1E', '0F', 'F0', 'E1', 'D2', and 'C3' can be sequentially output. The thirteenth reference output data DOUT_R_B13, the thirteenth feedback output data DOUT_F_B13, the twenty-fourth reference output data DOUT_R_B24 and the twenty-fourth feedback output data DOUT_F_B24, which are output sequentially, can be output sequentially based on the first storage bank low selection signal SEL_B1_LB, the first storage bank high selection signal SEL_B1_HB, the second storage bank low selection signal SEL_B2_LB, the second storage bank high selection signal SEL_B2_HB, the third storage bank low selection signal SEL_B3_LB, the third storage bank high selection signal SEL_B3_HB, the fourth storage bank low selection signal SEL_B4_LB and the fourth storage bank high selection signal SEL_B4_HB.

[0180] That is, since the bank low select signal is generated based on the read clock POUT_CLK(RE_N), when any one bank low select signal becomes a low state, the other bank low select signal may become a high state.

[0181] exist Figure 8, after the first bank low selection signal SEL_B1_LB changes to a low state, the second bank low selection signal SEL_B2_LB may change to a high state; after the second bank low selection signal SEL_B2_LB changes to a low state, the third bank low selection signal SEL_B3_LB may change to a high state; and after the third bank low selection signal SEL_B3_LB changes to a low state, the fourth bank low selection signal SEL_B4_LB may change to a high state.

[0182] Similarly, since the bank high select signal is generated by using a clock obtained by inverting the read clock POUT_CLK(RE_N) as a clock input, when any one bank high select signal becomes a low state, the other bank high select signal can become a high state.

[0183] exist Figure 8 , after the first bank high selection signal SEL_B1_HB changes to a low state, the second bank high selection signal SEL_B2_HB may change to a high state; after the second bank high selection signal SEL_B2_HB changes to a low state, the third bank high selection signal SEL_B3_HB may change to a high state; and after the third bank high selection signal SEL_B3_HB changes to a low state, the fourth bank high selection signal SEL_B4_HB may change to a high state.

[0184] Additionally, since the bank high select signal is generated based on the inverted read clock, the bank high signal changes to a high state after 1 / 2 clock has passed after the bank low signal changes to a high state, and thus data can be sequentially output based on the bank low select signal and the bank high select signal. That is, data can be output when the bank low select signal and the bank high select signal change from a low state to a high state, or when the bank low select signal and the bank high select signal change from a high state to a low state. Therefore, data can be output sequentially.

[0185] That is, after the read clock POUT_CLK (RE_N) has passed 1 / 2 clock after the first storage body low selection signal SEL_B1_LB changes to a high state, the first storage body high selection signal SEL_B1_HB can become a high state, and after the read clock POUT_CLK (RE_N) has passed 1 / 2 clock after the first storage body high selection signal SEL_B1_HB changes to a high state, the second storage body low selection signal SEL_B2_LB can change to a high state.

[0186] In the above manner, the bank low selection signal and the bank high selection signal can be changed to a high state within 1 / 2 clock cycle.

[0187] Therefore, the first to fourth bank low select signals SEL_B1_LB to SEL_B4_LB are generated based on the read clock POUT_CLK (RE_N), and the first to fourth bank high select signals SEL_B1_HB to SEL_B4_HB are generated based on a clock obtained by inverting the read clock POUT_CLK (RE_N). Therefore, data can be sequentially output to the memory controller (based on the first to fourth bank low select signals SEL_B1_LB to SEL_B4_LB and the first to fourth bank high select signals SEL_B1_HB to SEL_B4_HB). Figure 4 200 shown).

[0188] That is, data can be sequentially output based on only the first to fourth bank low selection signals SEL_B1_LB to SEL_B4_LB and the first to fourth bank high selection signals SEL_B1_HB to SEL_B4_HB without generating the B13 clock CLK4D_B13 and the B24 clock CLK4D_B24. Figure 9 Shown in.

[0189] Figure 9 is a diagram illustrating a process of generating a control signal for outputting data via three stages.

[0190] refer to Figure 1 and Figure 9 , transmission control signal generator ( Figure 1 190) shown may include Figure 9 The selection signal generator 191, the clock signal delay unit 193 and the step clock generator 195 are shown. Figure 1 The components in 190) shown in FIG can control the signals to be generated for sequentially outputting the signals from the first to the fourth memory banks ( Figure 5 The data signal output by each memory device included in 70_1 to 70_4 shown in FIG. Figure 9 In the embodiment, the read clock POUT_CLK(RE_N) can be received from the outside.

[0191] In one embodiment, the selection signal generator 191 may be configured with first to fourth flip-flops 191_1 to 191_4. Each of the first to fourth flip-flops 191_1 to 191_4 may be configured as a D flip-flop. The D flip-flop may output data input based on a clock input. The clock signal delay unit 193 may delay and output the clock input, and the step clock generator 195 may generate a clock signal based on the delayed clock input to sequentially output the data stored in the first to fourth memory banks ( Figure 5Furthermore, the step clock generator 195 may be configured with a D flip-flop, an inverter (NOT gate), and an AND gate.

[0192] In one embodiment, the first to fourth flip-flops 191_1 to 191_4 can receive a read clock signal POUT_CLK(RE_N) as a clock input. Therefore, the first to fourth flip-flops 191_1 to 191_4 can output, based on the read clock signal POUT_CLK(RE_N), the first and second bank low and high select signals SEL_B1_LB / HB, the second and second bank low and high select signals SEL_B2_LB / HB, the third and third bank low and high select signals SEL_B3_LB / HB, and the fourth and fourth bank low and high select signals SEL_B4_LB / HB, respectively. The fourth and fourth bank low and high select signals SEL_B4_LB / HB can be input to the first flip-flop 191_1 again.

[0193] exist Figure 9 , it is assumed that each of the first bank low selection signal SEL_B1_LB and the first bank high selection signal SEL_B1_HB, each of the second bank low selection signal SEL_B2_LB and the second bank high selection signal SEL_B2_HB, each of the third bank low selection signal SEL_B3_LB and the third bank high selection signal SEL_B3_HB, and each of the fourth bank low selection signal SEL_B4_LB and the fourth bank high selection signal SEL_B4_HB are in the same state. That is, since the selection signal is divided for each storage body, it is assumed that the signals SEL_B1_LB and SEL_B1_HB corresponding to the first storage body are both in the same state, the signals SEL_B2_LB and SEL_B2_HB corresponding to the second storage body are both in the same state, the signals SEL_B3_LB and SEL_B3_HB corresponding to the third storage body are both in the same state, and the signals SEL_B4_LB and SEL_B4_HB corresponding to the fourth storage body are both in the same state.

[0194] For example, the first flip-flop 191_1 may output the first bank low selection signal and the first bank high selection signal SEL_B1_LB / HB by using the read clock POUT_CLK (RE_N) as a clock input and by using the fourth bank low selection signal and the fourth bank high selection signal SEL_B4_LB / HB as feedback inputs.

[0195] The second flip-flop 191_2 may output a second bank low select signal and a second bank high select signal SEL_B2_LB / HB by using the read clock POUT_CLK (RE_N) as a clock input and by using the first bank low select signal and the first bank high select signal SEL_B1_LB / HB as inputs.

[0196] The third flip-flop 191_3 may output a third bank low select signal and a third bank high select signal SEL_B3_LB / HB by using the read clock POUT_CLK (RE_N) as a clock input and by using the second bank low select signal and the second bank high select signal SEL_B2_LB / HB as inputs.

[0197] The fourth flip-flop 191_4 may output the fourth bank low and high select signals SEL_B4_LB / HB by using the read clock POUT_CLK (RE_N) as a clock input and the third bank low and high select signals SEL_B3_LB / HB as inputs.

[0198] In one embodiment, the clock signal delay unit 193 may generate a delayed read clock DEL_POUT_CLK obtained by delaying the read clock POUT_CLK(RE_N), thereby generating a clock signal to be stored in the first to fourth memory banks ( Figure 5 The data in 70_1 to 70_4) shown in FIG are sequentially output to the memory controller ( Figure 4 The generated delayed read clock DEL_POUT_CLK may be output to the step clock generator 195.

[0199] In one embodiment, the step clock generator 195 can generate a B13 clock CLK4D_B13 and a B24 clock CLK4D_B24 for sequentially outputting data based on the delayed read clock DEL_POUT_CLK. As long as the B13 clock CLK4D_B13 and the B24 clock CLK4D_B24 change from a low state to a high state, or the B13 clock CLK4D_B13 and the B24 clock CLK4D_B24 change from a high state to a low state, the data can be output so that the data stored in the first to fourth memory banks ( Figure 5 The data in 70_1 to 70_4) shown in FIG can be sequentially output to the memory controller ( Figure 4 200 shown in FIG).

[0200] However, in Figure 7In the structure in which the stages shown are merged, the B13 clock CLK4D_B13 and the B24 clock CLK4D_B24 may not be generated, and therefore, it may be necessary to generate the first memory bank low selection signal SEL_B1_LB, the first memory bank high selection signal SEL_B1_HB, the second memory bank low selection signal SEL_B2_LB, the second memory bank high selection signal SEL_B2_HB, the third memory bank low selection signal SEL_B3_LB, the third memory bank high selection signal SEL_B3_HB, the fourth memory bank low selection signal SEL_B4_LB and the fourth memory bank high selection signal SEL_B4_HB for sequentially outputting data. The first bank low selection signal SEL_B1_LB, the first bank high selection signal SEL_B1_HB, the second bank low selection signal SEL_B2_LB, the second bank high selection signal SEL_B2_HB, the third bank low selection signal SEL_B3_LB, the third bank high selection signal SEL_B3_HB, the fourth bank low selection signal SEL_B4_LB and the fourth bank high selection signal SEL_B4_HB may be sequentially changed to a high state.

[0201] Figure 10 is a diagram illustrating a process of generating a control signal for outputting data via two stages.

[0202] refer to Figure 1 、 Figure 9 and Figure 10 , transmission control signal generator ( Figure 1 190) shown may include Figure 10 The A-th selection signal generator 191A and the B-th selection signal generator 191B are shown. The A-th selection signal generator 191A may include 1L-th to 4L-th flip-flops 191A_1L to 191A_4L, and the B-th selection signal generator 191B may include 1H-th to 4H-th flip-flops 191B_1H to 191B_4H. Figure 9 different, Figure 10 The clock signal delay unit may not be included ( Figure 9 193) and the step clock generator ( Figure 9 195 shown in ).

[0203] exist Figure 10 In the embodiment, each of the 1Lth to 4Lth flip-flops 191A_1L to 191A_4L and the 1Hth to 4Hth flip-flops 191B_1H to 191B_4H may be configured as a D flip-flop. The D flip-flop may output data input based on a clock input. Figure 10 In the embodiment, the read clock POUT_CLK(RE_N) can be received from the outside.

[0204] In one embodiment, the 1Lth to 4Lth flip-flops 191A_1L to 191A_4L may receive a read clock POUT_CLK(RE_N) as a clock input, and the 1Hth to 4Hth flip-flops 191B_1H to 191B_4H may receive a clock obtained by inverting the read clock POUT_CLK(RE_N) as a clock input. The 1Lth to 4Lth flip-flops 191A_1L to 191A_4L may output a bank low select signal, and the 1Hth to 4Hth flip-flops 191B_1H to 191B_4H may output a bank high select signal.

[0205] In addition, the fourth storage bank low selection signal SEL_B4_LB output from the 4th L flip-flop 191A_4L can be input as the feedback input (feedback) of the 1st L flip-flop 191A_1L, and the fourth storage bank high selection signal SEL_B4_HB output from the 4th H flip-flop 191B_4H can be input as the feedback input (feedback) of the 1st H flip-flop 191B_1H.

[0206] Specifically, the 1st L flip-flop 191A_1L can output the first bank low select signal SEL_B1_LB by using the read clock POUT_CLK (RE_N) as a clock input and by using the fourth bank low select signal SEL_B4_LB as a feedback input. The 2nd L flip-flop 191A_2L can output the second bank low select signal SEL_B2_LB by using the read clock POUT_CLK (RE_N) as a clock input and by using the first bank low select signal SEL_B1_LB as an input. The 3rd L flip-flop 191A_3L can output the third bank low select signal SEL_B3_LB by using the read clock POUT_CLK (RE_N) as a clock input and by using the second bank low select signal SEL_B2_LB as an input. The 4th L flip-flop 191A_4L may output the fourth bank low select signal SEL_B4_LB by using the read clock POUT_CLK(RE_N) as a clock input and using the third bank low select signal SEL_B3_LB as an input.

[0207] In addition, the 1H flip-flop 191B_1H can output the first bank high select signal SEL_B1_HB by using the clock input and the fourth bank high select signal SEL_B4_HB as a feedback input, the clock being obtained by inverting the read clock POUT_CLK(RE_N). The 2H flip-flop 191B_2H can output the second bank high select signal SEL_B2_HB by using the clock input and the first bank high select signal SEL_B1_HB as an input, the clock being obtained by inverting the read clock POUT_CLK(RE_N). The 3H flip-flop 191B_3H can output the third bank high select signal SEL_B3_HB by using the clock input and the second bank high select signal SEL_B2_HB as an input, the clock being obtained by inverting the read clock POUT_CLK(RE_N). The 4th H flip-flop 191B_4H may output the fourth bank high select signal SEL_B4_HB by using a clock input obtained by inverting the read clock POUT_CLK(RE_N) and using the third bank high select signal SEL_B3_HB as an output.

[0208] Therefore, the first to fourth bank low select signals SEL_1B_LB to SEL_4B_LB may be generated based on the read clock POUT_CLK (RE_N), and the first to fourth bank high select signals SEL_b1_HB to SEL_B4_HB may be generated based on a clock obtained by inverting the read clock POUT_CLK (RE_N). Therefore, data may be sequentially output to the memory controller ( based on the first to fourth bank low select signals SEL_1B_LB to SEL_4B_LB and the first to fourth bank high select signals SEL_b1_HB to SEL_B4_HB). Figure 4 200 shown).

[0209] That is, data can be generated without Figure 9 In the case of the B13 clock CLK4D_B13 and the B24 clock CLK4D_B24 shown in FIG, they are sequentially output based on only the first to fourth bank low selection signals SEL_B1_LB to SEL_B4_LB and the first to fourth bank high selection signals SEL_B1_HB to SEL_B4_HB.

[0210] Figure 11 is a diagram illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0211] refer to Figure 11In step S1101, in a structure having a plurality of memory banks, data stored in each memory device may be transmitted to a serializer based on a bank select signal, and the data transmitted to the serializer may be transmitted and stored in a latch unit. The serializer may be a device that controls data to be sequentially output, and the bank select signal may be a bank high select signal or a bank low select signal.

[0212] In step S1103, the data stored in the latch unit can be output to the memory controller based on the bank high select signal or the bank low select signal. The bank low select signal can be generated based on the read clock POUT_CLK (RE_N), and the bank high select signal can be generated based on a clock obtained by inverting the read clock POUT_CLK (RE_N). Therefore, the data can be sequentially output to the memory controller.

[0213] Therefore, since data is output through two steps (ie, steps S1101 and S1103 ), the amount of current consumed in the memory device 100 can be reduced, and data output delay can be prevented.

[0214] Figure 12 is a diagram illustrating the operation of a memory device according to one embodiment of the present disclosure.

[0215] refer to Figure 12 In step S1201, the memory device may generate a bank low select signal based on the read clock POUT_CLK (RE_N). Since the bank low select signal is generated based on the read clock POUT_CLK (RE_N), when any one bank low select signal goes low, the other bank low select signal may go high.

[0216] In step S1203, the memory device may generate a bank high select signal based on a read clock obtained by inverting the read clock POUT_CLK(RE_N). Since the bank high select signal is generated based on the inverted read clock, when any one bank high select signal goes low, the other bank high select signal may go high.

[0217] Furthermore, since the bank high select signal is generated based on the inverted read clock, the bank high select signal can change to a high state after 1 / 2 clock has passed after the bank low select signal can change to a high state. Therefore, in step S1205, data can be sequentially output based on the bank low select signal and the bank high select signal. That is, data is output when the bank low select signal and the bank high select signal change from a low state to a high state, or when the bank low select signal and the bank high select signal change from a high state to a low state. Therefore, data can be output sequentially.

[0218] Figure 13 It's a picture Figure 1 A diagram of another embodiment of a memory controller is shown.

[0219] refer to Figure 13 , the memory controller 1000 is connected to the host and the memory device. The memory controller 1000 is configured to access the memory device based on a request received from the host. For example, the memory controller 1000 is configured to control the read, program, erase, and background operations of the memory device. The memory controller 1000 is configured to provide an interface between the memory device and the host. The memory controller 1000 is configured to drive the firmware that controls the memory device.

[0220] The memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction code (ECC) circuit 1030 , a host interface 1040 , a buffer control circuit 1050 , a memory interface 1060 , and a bus 1070 .

[0221] The bus 1070 may be configured to provide a channel between the components of the memory controller 1000 .

[0222] The processor 1010 may control the overall operation of the memory controller 1000 and may perform logic operations. The processor 1010 may communicate with an external host via a host interface 1040 and may communicate with a memory device via a memory interface 1060. Furthermore, the processor 1010 may communicate with the memory buffer 1020 via a buffer control circuit 1050. The processor 1010 may control the operation of the memory device by using the memory buffer 1020 as a working memory, a cache memory, or a buffer memory.

[0223] Processor 1010 can perform the functions of a flash translation layer (FTL). Processor 1010 can convert logical block addresses (LBAs) provided by the host via the FTL into physical block addresses (PBAs). The FTL can receive logical block addresses (LPAs) using a mapping table and convert them into physical block addresses (PBAs). Based on the mapping unit, there are several FTL address mapping methods. Representative address mapping methods include page mapping, block mapping, and hybrid mapping.

[0224] The processor 1010 may be configured to randomize data received from the host. For example, the processor 1010 may randomize data received from the host using a randomization seed. The randomized data is provided as data to be stored in the memory device being programmed in the memory cell array.

[0225] The processor 1010 may perform randomization and de-randomization through driving software or firmware.

[0226] The memory buffer 1020 may be used as a working memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store codes and commands executed by the processor 1010. The memory buffer 1020 may store data processed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0227] The ECC circuit 1030 can perform ECC operations. The ECC circuit 1030 can perform ECC encoding on data to be written to the memory device via the memory interface 1060. The ECC-encoded data can be transmitted to the memory device via the memory interface 1060. The ECC circuit 1030 can perform ECC decoding on data received from the memory device via the memory interface 1060. For example, the ECC circuit 1030 can be included in the memory interface 1060 as a component of the memory interface 1060.

[0228] The host interface 1040 may communicate with an external host based on the processor 1010. The host interface 1040 may communicate with the host by using at least one of various communication methods, such as a universal serial bus (USB), a serial AT attachment (SATA), a high-speed inter-chip (HSIC), a small computer system interface (SCSI), Firewire, a peripheral component interconnect (PCI), PCI Express (PCIe), a non-volatile memory express (NVMe), a universal flash memory (UFS), a secure digital (SD), a multimedia card (MMC), an embedded MMC (eMMC), a dual in-line memory module (DIMM), a registered DIMM (RDIMM), and a load-reduced DIMM (LRDIMM).

[0229] The buffer control circuit 1050 is configured to control the memory buffer 1020 based on the processor 1010 .

[0230] The memory interface 1060 is configured to communicate with the memory device based on the processor 1010. The memory interface 1060 may communicate commands, addresses, and data with the memory device through a channel.

[0231] For example, the memory controller 1000 may not include the memory buffer 1020 and the buffer control circuit 1050 .

[0232] For example, the processor 1010 may control the operation of the memory controller 1000 by using code. The processor 1010 may load code from a nonvolatile memory device (e.g., a read-only memory (ROM)) provided in the memory controller 1000. In another example, the processor 1010 may load code from the memory device via the memory interface 1060.

[0233] For example, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data in the memory controller 1000, and the control bus can be configured to transmit control information, such as commands and addresses, in the memory controller 1000. The data bus and the control bus are separated from each other and may not interface with each other and affect each other. The data bus can be connected to the host interface 1040, the buffer control circuit 1050, the ECC circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer control circuit 1050, the memory buffer 1020, and the memory interface 1060.

[0234] Figure 14 is a block diagram exemplarily illustrating a memory card system to which a storage device is applied according to an embodiment of the present disclosure.

[0235] refer to Figure 14 , the memory card system 2000 may include a memory controller 2100 , a memory device and a connector 2300 .

[0236] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 is configured to control the read, write, erase, and background operations of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and the host. The memory controller 2100 is configured to drive the firmware that controls the memory device 2200. The memory device 2200 can communicate with the memory device 100 ( Figure 1 100) shown is implemented identically.

[0237] Exemplarily, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector 233 .

[0238] The memory controller 2100 can communicate with an external device via the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) based on a specific communication protocol. For example, the memory controller 2100 can communicate with an external device via at least one of various communication protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), firewire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and NVMe.

[0239] Exemplarily, the memory device 2200 may be implemented using various non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0240] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 may form a memory card such as a PC card (Personal Computer Memory Card Association International (PCMCIA)), a Compact Flash (CF) card, a Smart Media Card (SM and SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, microSD, and SDHC), and a Universal Flash Storage (UFS).

[0241] Figure 15 is a block diagram exemplarily illustrating a solid-state drive (SSD) system to which a storage device is applied according to one embodiment of the present disclosure.

[0242] refer to Figure 15 , an SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 exchanges a signal SIG with the host 3100 via a signal connector 3001 and receives power PWR via a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0243] In one embodiment, the SSD controller 3210 may function as a memory controller ( Figure 1 200 shown).

[0244] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n based on a signal SIG received from the host 3100. For example, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of the following interfaces: a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI Express (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), firewire, a universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe.

[0245] The auxiliary power supply 3230 is connected to the host 3100 via the power connector 3002. When the power supply from the host 3100 is unstable, the auxiliary power supply 3230 can provide power to the SSD 3200. Exemplarily, the auxiliary power supply 3230 can be located in the SSD 3200 or can be located outside the SSD 3200. For example, the auxiliary power supply 3230 can be located on the motherboard and provide auxiliary power to the SSD 3200.

[0246] The buffer memory 3240 serves as a buffer memory for the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 may include a volatile memory (such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM) or a nonvolatile memory (such as FRAM, ReRAM, STT-MRAM, and PRAM).

[0247] Figure 16 is a block diagram exemplarily illustrating a user system to which a storage device is applied according to one embodiment of the present disclosure.

[0248] refer to Figure 16 , the user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0249] The application processor 4100 may drive components included in the user system 4000, an operating system (OS), a user program, etc. Exemplarily, the application processor 4100 may include a controller that controls components, an interface, a graphic engine, etc. included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0250] The memory module 4200 can be used as a main memory, working memory, buffer memory, or cache memory of the user system 4000. The memory module 4200 may include a volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or a non-volatile random access memory such as PRAM, ReRAM, MRAM, and FRAM. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package-on-package (PoP) and provided as one semiconductor package.

[0251] The network module 4300 can communicate with external devices. Exemplarily, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), Wimax, WLAN, UWB, Bluetooth, and Wi-Fi. Exemplarily, the network module 4300 can be included in the application processor 4100.

[0252] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can transmit the data stored therein to the application processor 4100. Exemplarily, the storage module 4400 can be implemented using a non-volatile semiconductor memory device (such as a phase change RAM (PRAM) having a three-dimensional structure, a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory). Exemplarily, the storage module 4400 can be provided as a removable drive device, such as a memory card or an external drive device of the user system 4000.

[0253] Exemplarily, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may be connected to the reference memory. Figure 2 and Figure 3 The memory module 4400 can be used with reference to Figure 1 The described storage device 50 operates identically.

[0254] The user interface 4500 may include an interface for inputting data or commands to the application processor 4100 or outputting data to an external device. Exemplarily, the user interface 4500 may include a user input interface such as a keyboard, a keypad, a button, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric element. The user interface 4500 may include a user output interface such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0255] According to the present disclosure, the number of transmission stages (steps) is reduced in data transmission. Therefore, data transmission delay can be prevented and the amount of current consumed in data transmission can be reduced.

[0256] Although the present disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as defined by the appended claims and their equivalents. Therefore, the scope of the present disclosure should not be limited to the above-described exemplary embodiments but should be determined not only by the appended claims but also by their equivalents.

[0257] In the above embodiments, all steps may be selectively performed or some steps may be omitted. In each embodiment, the steps are not necessarily performed in the order described and may be rearranged. The embodiments disclosed in this specification and the accompanying drawings are merely examples to facilitate understanding of the present disclosure, and the present disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications may be made based on the technical scope of the present disclosure.

[0258] Meanwhile, exemplary embodiments of the present disclosure have been described in the accompanying drawings and the specification. Although specific terms are used herein, these are only for the purpose of explaining the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many variations are possible within the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure.

Claims

1. A storage device comprising a memory controller and a plurality of memory banks, each of the plurality of memory banks comprising a plurality of memory devices, Each of the plurality of memory devices comprises: a data selector configured to select and output data of a memory device included in any one of the plurality of memory banks based on a bank selection signal; a latch unit configured to store the data output from the data selector; as well as a transmission control signal generator configured to generate the bank selection signal so that the data stored in the latch unit is sequentially output, The transmission control signal generator is configured as follows: generating a bank low selection signal in the bank selection signal based on a reference clock; as well as generating a bank high selection signal among the bank selection signals based on a clock obtained by inverting the reference clock, and Wherein, when half a cycle of the reference clock has passed after any one of the memory bank low selection signals changes to a high state, the transmission control signal generator is configured to change any one of the memory bank high selection signals to the high state. 2 . The memory device of claim 1 , wherein the data selector is configured to output data stored in a memory device corresponding to the data selector when the bank select signal is in a high state. 3 . The memory device according to claim 1 , wherein when any one of the bank low select signals is in a high state, the transmission control signal generator is configured to output the other bank low select signal to be in a low state.

4. The storage device according to claim 1, wherein when any one of the storage body low selection signals changes from a high state to a low state, the transmission control signal generator is configured to change any one of the other storage body low selection signals from the low state to the high state. 5 . The memory device according to claim 1 , wherein when any one of the bank high select signals is in a high state, the transmission control signal generator is configured to output the other bank high select signal to be in a low state.

6. The storage device according to claim 1, wherein when any one of the storage body high selection signals changes from a high state to a low state, the transmission control signal generator is configured to change any one of the other storage body high selection signals from the low state to the high state.

7. The storage device according to claim 1, wherein when any one of the storage body low selection signals changes to be in the high state, the data selector is configured to select data output from the memory device corresponding to the corresponding storage body low selection signal, is configured to store the data in the latch unit, and is then configured to output the data to the memory controller.

8. The storage device according to claim 7 , wherein when any one of the bank low selection signals changes to be in the high state and any one of the bank high selection signals changes to be in the high state after half a cycle of the reference clock has passed, the data selector is configured to select data output from the memory device corresponding to the corresponding bank high selection signal, is configured to store the data in the latch unit, and then is configured to output the data to the memory controller.

9. A method for operating a memory device having a memory controller and a plurality of memory banks, each of the plurality of memory banks comprising a plurality of memory devices, the method comprising: generating a bank selection signal that controls a data selector to select and output data of a memory device included in any one of the plurality of banks; storing the data in a latch unit based on the bank selection signal, and then outputting the data to the memory controller; generating a bank low selection signal in the bank selection signal based on a reference clock; as well as generating a bank high selection signal among the bank selection signals based on a clock obtained by inverting the reference clock, and Wherein, when generating the memory high selection signal, when half a cycle of the reference clock has passed after any one of the memory low selection signals changes to a high state, any one of the memory high selection signals is generated to change to the high state. 10 . The method of claim 9 , wherein in outputting the data to the memory controller, when the bank select signal is in a high state, data stored in a memory device corresponding to the data selector is output.

11. The method according to claim 9, wherein in generating the bank low select signals, when any one of the bank low select signals is in a high state, the other bank low select signals are generated to be in a low state.

12. The method according to claim 9, wherein, when generating the memory low selection signal, when any one of the memory low selection signals changes from a high state to a low state, any one of the other memory low selection signals is generated to change from the low state to the high state.

13. The method according to claim 9, wherein in generating the bank high selection signals, when any one of the bank high selection signals is in a high state, the other bank high selection signals are generated to be in a low state.

14. The method according to claim 9, wherein, when generating the memory high selection signal, when any one of the memory high selection signals changes from a high state to a low state, any one of the other memory high selection signals is generated to change from the low state to the high state.

15. A method according to claim 9, wherein, when generating the storage body low selection signal, when half a cycle of the reference clock has passed after any one of the storage body high selection signals changes to be in the high state, any one of the storage body low selection signals is generated to change to the high state.

16. A method according to claim 9, wherein when the data is output to the memory controller, when the corresponding memory low selection signal changes to be in the high state, the data output from the memory device corresponding to any one of the memory low selection signals is selected, stored in the latch unit and then output to the memory controller.

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