Method for manufacturing semiconductor device using stress memory technology

Abstract

The present invention discloses a method for manufacturing a semiconductor device using stress memory technology, comprising: step 1, completing the formation process of a gate structure; step 2, forming a first silicon nitride layer with tensile stress for realizing stress memory technology, comprising: step 21, growing a first silicon nitride sublayer with tensile stress using an ALD process; step 22, growing a second silicon nitride sublayer with tensile stress using a CVD process; forming a first silicon nitride layer by superimposing the first and second silicon nitride sublayers; utilizing the characteristic that the step coverage of the ALD process is better than the step coverage of the CVD process, improving the step coverage of the first silicon nitride layer and thereby avoiding the first silicon nitride layer from sealing at the top of the spacer, so that the thickness of the first silicon nitride layer located on the top surface, side surface and bottom surface of the gate structure reaches the required value. The present invention can improve the thickness of the SMT silicon nitride located on the side surface of the gate structure and the bottom surface of the spacer, thereby increasing the stress in the channel region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a semiconductor device using stress memorization technique (SMT). Background Art

[0002] SMT technology mainly utilizes silicon nitride with tensile stress, namely SMT silicon nitride, to act on semiconductor devices to transfer stress to the channel region of the semiconductor device, so that the channel region forms a stress structure that is conducive to increasing electron mobility, namely a tensile stress structure. This stress structure in the channel region has a memory effect, that is, the stress will still remain after the SMT silicon nitride is removed.

[0003] SMT silicon nitride needs to cover the top surface, side and spacer outside the gate structure. As the technology nodes of semiconductor manufacturing process continue to shrink in proportion, the size of the spacer between gate structures will also continue to shrink. However, in order to meet the requirement of transferring sufficient stress to the channel area, the thickness of SMT silicon nitride must be greater than the required value. When the process node reaches below 28nm, when SMT silicon nitride of the required thickness is deposited by CVD, an overhang is often generated at the top of the spacer. After the overhang is generated at the top of the spacer, the subsequently deposited SMT silicon nitride cannot be filled in the spacer. The side of the spacer is the side of the gate structure. Therefore, the thickness of the SMT silicon nitride on the side of the gate structure and the bottom surface of the spacer will not meet the required value, which will eventually reduce the stress transferred to the channel area, thereby affecting the performance of the device.

[0004] like Figure 1A to Figure 1B FIG. 1 is a schematic diagram of a device structure in each step of a conventional method for manufacturing a semiconductor device using stress memory technology. The conventional method for manufacturing a semiconductor device using stress memory technology includes the following steps:

[0005] Step 1: Figure 1A As shown, a process of forming a gate structure is completed on the surface of a semiconductor substrate 101 . The gate structure includes a plurality of gates. The area covered by the gate structure forms a channel region of a semiconductor device. There are spacing regions between the gate structures.

[0006] Conventionally, the semiconductor substrate 101 includes a silicon substrate.

[0007] The gate structure is formed by stacking a gate dielectric layer 105 and a polysilicon gate 106 .

[0008] The semiconductor device includes NMOS and PMOS, and the NMOS and the PMOS are integrated on the semiconductor substrate 101 at the same time. Figure 1AIn FIG. 1 , the region indicated by the bracket 301 is a PMOS formation region, and the region indicated by the bracket 302 is a NMOS formation region.

[0009] In the NMOS formation region, a P well 103 is formed in the semiconductor substrate 101 ; and in the PMOS formation region, an N well 102 is formed in the semiconductor substrate 101 .

[0010] A shallow trench isolation 104 is also formed on the semiconductor substrate 101 , and an active region is defined by the shallow trench isolation 104 .

[0011] After the gate structure is formed, the method further includes:

[0012] A step of forming a spacer 107 on the side of the gate structure.

[0013] After the sidewall spacer 107 is formed, the process further includes forming a source region and a drain region in the semiconductor substrate 101 on both sides of the gate structure.

[0014] Figure 1A In the embodiment, the sidewall spacer 107 includes a first sidewall spacer 107a and a second sidewall spacer 107b. After the first sidewall spacer 107a is formed, LDD implantation is performed to form an LDD region. The LDD region of PMOS is a P-type LDD region 108a, and the LDD region of NMOS is an N-type LDD region 108b.

[0015] After the second-layer sidewall spacer 107 b is formed, source and drain implantation is performed to form a source region and a drain region. Figure 1A The source region and drain region of the PMOS are respectively composed of P+ regions 109a located on both sides of the gate structure, and the source region and drain region of the NMOS are respectively composed of N+ regions 109b located on both sides of the gate structure.

[0016] Step 2: Using a CVD process to form a first silicon nitride layer 110 with a required thickness and having tensile stress for implementing stress memory technology.

[0017] Usually, if Figure 1B As shown, before forming the first silicon nitride layer 110 , a step of forming a second silicon oxide layer 109 is also included.

[0018] After step 2, an annealing process is further performed to transfer the tensile stress of the first silicon nitride layer 110 to the channel region.

[0019] The annealing process adopts a rapid thermal annealing process.

[0020] As the process technology node continues to shrink proportionally, the width of the spacer will also shrink, so it becomes increasingly difficult for the first silicon nitride layer 101 to fill the spacer. However, in order to transfer sufficient stress to the channel region, the thickness of the first silicon nitride layer 101 needs to meet the required value. When the technology node of the semiconductor device is below 28nm, the thickness of the first silicon nitride layer 110 is required to be above 30nm, and it will be impossible to fill the spacer well. Figure 1B As shown in the dotted circle 112 in the figure, a seal is formed on the top of the spacer during the formation of the first silicon nitride layer 110. After the seal is formed, the silicon nitride material cannot continue to fill the inside of the spacer, which makes the thickness of the first silicon nitride layer 110 on the side of the gate structure as shown in the dotted circle 113 and the bottom surface of the spacer as shown in the dotted circle 114 become thinner, and finally the stress in the channel region becomes smaller, affecting the performance of the NMOS. Summary of the invention

[0021] The technical problem to be solved by the present invention is to provide a method for manufacturing a semiconductor device using stress memory technology, which can prevent the SMT silicon nitride layer from sealing at the top of the spacer between the gate structures, thereby increasing the thickness of the SMT silicon nitride on the side of the gate structure and the top surface of the spacer, and thereby increasing the tensile stress in the channel region.

[0022] In order to solve the above technical problems, the present invention provides a method for manufacturing a semiconductor device using stress memory technology, comprising the following steps:

[0023] Step 1: completing a process of forming a gate structure on the surface of a semiconductor substrate, wherein the gate structure comprises a plurality of gates, and an area covered by the gate structure forms a channel area of ​​a semiconductor device; and a spacing area is provided between each of the gate structures.

[0024] Step 2: forming a first silicon nitride layer with tensile stress for realizing stress memory technology, including the following steps:

[0025] Step 21: grow a first silicon nitride sublayer with tensile stress using an ALD process, wherein the first silicon nitride sublayer covers the top surface, the side surface of the gate structure and the bottom surface of the spacer.

[0026] Step 22: grow a second silicon nitride sublayer with tensile stress using a CVD process, wherein the second silicon nitride sublayer is formed on the surface of the first silicon nitride sublayer; the first silicon nitride sublayer and the second silicon nitride sublayer are stacked to form the first silicon nitride layer; utilize the characteristic that the step coverage of the ALD process is better than the step coverage of the CVD process to improve the step coverage of the first silicon nitride layer and thereby avoid the first silicon nitride layer from sealing at the top of the spacer region, so that the thickness of the first silicon nitride layer located on the top surface, side surface of the gate structure and the bottom surface of the spacer region reaches the required value.

[0027] A further improvement is that in step 2, before forming the first silicon nitride layer, a step of forming a second silicon oxide layer is also included.

[0028] A further improvement is that after step 2, an annealing process is also performed, wherein the annealing process transfers the tensile stress of the first silicon nitride layer to the channel region.

[0029] A further improvement is that the annealing process adopts a rapid thermal annealing process.

[0030] A further improvement is that the semiconductor device includes NMOS and PMOS, and the NMOS and the PMOS are integrated on the semiconductor substrate at the same time.

[0031] A further improvement is that before performing the annealing process, it also includes a step of removing the first silicon nitride layer in the PMOS formation area; or, after step two is completed, the annealing process is performed under the condition that the first silicon nitride layer is retained in the PMOS formation area.

[0032] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0033] A further improvement is that the gate structure is formed by stacking a gate dielectric layer and a polysilicon gate.

[0034] A further improvement is that, in the NMOS formation region, a P well is formed in the semiconductor substrate; and in the PMOS formation region, an N well is formed in the semiconductor substrate.

[0035] A further improvement is that before step 2, a step of forming a sidewall spacer on the side of the gate structure is also included.

[0036] A further improvement is that after the sidewalls are formed, the method further includes forming a source region and a drain region in the semiconductor substrate on both sides of the gate structure.

[0037] A further improvement is that after the annealing process is completed, the method further includes removing the first silicon nitride layer;

[0038] Alternatively, after the annealing process is completed, the first silicon nitride layer is retained and serves as a contact etching stop layer.

[0039] A further improvement is that the technology node of the semiconductor device is below 28nm.

[0040] A further improvement is that the required thickness of the first silicon nitride layer is greater than 30 nm.

[0041] A further improvement is that the thickness of the first silicon nitride sub-layer is 10 nm, and the thickness of the second silicon nitride sub-layer is greater than 20 nm.

[0042] The present invention forms a first silicon nitride layer, namely, an SMT silicon nitride layer, in two steps. The first step is grown by an ALD process, and the second step is grown by a CVD process. Since the step coverage of the ALD process is better than that of the CVD process, the first silicon nitride layer can be prevented from being sealed at the top of the spacer, so that the thickness of the first silicon nitride layer located on the top surface, the side surface and the bottom surface of the spacer of the gate structure can reach the required value. Compared with the prior art, the present invention can make the thickness of the first silicon nitride layer on the side surface of the gate structure and the bottom surface of the spacer reach the required value, so the tensile stress of the channel region can be increased, thereby improving the performance of the NMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0044] Figure 1A-1B It is a schematic diagram of the device structure in each step of the manufacturing method of the existing semiconductor device using stress memory technology;

[0045] Figure 2 is a flow chart of a method for manufacturing a semiconductor device using stress memory technology according to an embodiment of the present invention;

[0046] Figure 3A-3D It is a schematic diagram of the device structure in each step of the method for manufacturing a semiconductor device using stress memory technology according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device using stress memory technology according to an embodiment of the present invention; FIG. 3A to FIG. 3D FIG. 1 is a schematic diagram of a device structure in each step of a method for manufacturing a semiconductor device using stress memory technology according to an embodiment of the present invention; the method for manufacturing a semiconductor device using stress memory technology according to an embodiment of the present invention comprises the following steps:

[0048] Step 1: Figure 3A As shown, a process of forming a gate structure is completed on the surface of a semiconductor substrate 201 . The gate structure includes a plurality of gates. The area covered by the gate structure forms a channel region of a semiconductor device. There are spacing regions between the gate structures.

[0049] In the embodiment of the present invention, the semiconductor substrate 201 includes a silicon substrate.

[0050] The gate structure is formed by stacking a gate dielectric layer 205 and a polysilicon gate 206 .

[0051] The semiconductor device includes NMOS and PMOS, and the NMOS and the PMOS are integrated on the semiconductor substrate 201 at the same time. Figure 3A In the figure, the region indicated by the bracket 401 is a PMOS formation region, and the region indicated by the bracket 402 is a NMOS formation region.

[0052] In the NMOS formation region, a P well 203 is formed in the semiconductor substrate 201 ; and in the PMOS formation region, an N well 202 is formed in the semiconductor substrate 201 .

[0053] A shallow trench isolation 204 is also formed on the semiconductor substrate 201 , and an active region is defined by the shallow trench isolation 204 .

[0054] After the gate structure is formed, the method further includes:

[0055] A step of forming a spacer 207 on the side of the gate structure.

[0056] After the sidewall spacer 207 is formed, the method further includes forming a source region and a drain region in the semiconductor substrate 201 on both sides of the gate structure.

[0057] Figure 3A In the embodiment, the sidewall spacer 207 includes a first sidewall spacer 207a and a second sidewall spacer 207b. After the first sidewall spacer 207a is formed, LDD implantation is performed to form an LDD region. The LDD region of PMOS is a P-type LDD region 208a, and the LDD region of NMOS is an N-type LDD region 208b.

[0058] After the second sidewall spacer 207 b is formed, source and drain implantation is performed to form a source region and a drain region. Figure 3A The source region and drain region of the PMOS are respectively composed of the P+ region 209a located on both sides of the gate structure, and the source region and drain region of the NMOS are respectively composed of the N+ region 209b located on both sides of the gate structure.

[0059] Step 2: forming a first silicon nitride layer 210 with tensile stress for realizing stress memory technology, including the following steps:

[0060] In the embodiment of the present invention, Figure 3B As shown, before forming the first silicon nitride sub-layer 210a, a step of forming a second silicon oxide layer 209 is also included.

[0061] Step 21: Figure 3C As shown, an ALD process is used to grow a first silicon nitride sub-layer 210 a having tensile stress, and the first silicon nitride sub-layer 210 a covers the top surface, the side surface of the gate structure and the bottom surface of the spacer.

[0062] Step 22: Figure 3D As shown, a second silicon nitride sublayer 210b with tensile stress is grown by a CVD process, and the second silicon nitride sublayer 210b is formed on the surface of the first silicon nitride sublayer 210a; the first silicon nitride sublayer 210a and the second silicon nitride sublayer 210b are superimposed to form the first silicon nitride layer 210; by utilizing the characteristic that the step coverage of the ALD process is better than the step coverage of the CVD process, the step coverage of the first silicon nitride layer 210 is improved and thereby the first silicon nitride layer 210 is prevented from sealing at the top of the spacer, so that the thickness of the first silicon nitride layer 210 located on the top surface, the side surface of the gate structure and the bottom surface of the spacer reaches the required value.

[0063] In the embodiment of the present invention, after step 2, an annealing process is further included, wherein the annealing process transfers the tensile stress of the first silicon nitride layer 210 to the channel region.

[0064] The annealing process adopts a rapid thermal annealing process.

[0065] The tensile stress is beneficial only to the channel region of the NMOS, namely, it can improve the electron mobility, but has no benefit to the channel region of the PMOS, namely, it will reduce the hole mobility.

[0066] In an improved embodiment, the method further includes: before performing the annealing process, a step of removing the first silicon nitride layer 210 in the PMOS formation region is included. In other embodiments, the annealing process can also be performed after step 2 is completed while the first silicon nitride layer 210 is retained in the PMOS formation region.

[0067] In the embodiment of the present invention, after the annealing process is completed, the step of removing the first silicon nitride layer 210 is further included. In other embodiments, after the annealing process is completed, the first silicon nitride layer 210 is retained and used as a contact etch stop layer.

[0068] As the process technology node is continuously reduced in proportion, the width of the spacer will also be reduced, so that it becomes increasingly difficult for the first silicon nitride layer 201 to fill the spacer. However, in order to achieve sufficient stress transfer to the channel region, the thickness of the first silicon nitride layer 201 needs to meet the required value. The embodiment of the present invention can achieve good filling of the spacer and make the thickness of the first silicon nitride layer 201 meet the requirements. When the technology node of the semiconductor device is below 28nm, the required value of the thickness of the first silicon nitride layer 210 is above 30nm, the thickness of the first silicon nitride sublayer 210a is 10nm, and the thickness of the second silicon nitride sublayer 210b is above 20nm.

[0069] The embodiment of the present invention forms the first silicon nitride layer 210, i.e., the SMT silicon nitride layer, in two steps. The first step is to grow the first silicon nitride layer using an ALD process, and the second step is to grow the first silicon nitride layer using a CVD process. Since the step coverage of the ALD process is better than that of the CVD process, the first silicon nitride layer 210 can be prevented from being sealed at the top of the spacer region, so that the thickness of the first silicon nitride layer 210 located on the top surface, the side surface of the gate structure, and the bottom surface of the spacer region can reach the required value. Compared with the prior art, the embodiment of the present invention can make the thickness of the first silicon nitride layer 210 on the side surface of the gate structure and the bottom surface of the spacer region also reach the required value, so the tensile stress in the channel region can be increased, thereby improving the performance of the NMOS.

[0070] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device using stress memory technology, characterized in that: The steps include: Step 1: completing a process of forming a gate structure on the surface of a semiconductor substrate, wherein the gate structure comprises a plurality of gate structures, and an area covered by the gate structure forms a channel region of a semiconductor device; and a spacing region is provided between each of the gate structures; Step 2: forming a first silicon nitride layer with tensile stress for realizing stress memory technology, including the following steps: Step 21, growing a first silicon nitride sublayer with tensile stress by using an ALD process, wherein the first silicon nitride sublayer covers the top surface, the side surface of the gate structure and the bottom surface of the spacer; Step 22: grow a second silicon nitride sublayer with tensile stress using a CVD process, wherein the second silicon nitride sublayer is formed on the surface of the first silicon nitride sublayer; the first silicon nitride sublayer and the second silicon nitride sublayer are stacked to form the first silicon nitride layer; utilize the characteristic that the step coverage of the ALD process is better than the step coverage of the CVD process to improve the step coverage of the first silicon nitride layer and thereby avoid the first silicon nitride layer from sealing at the top of the spacer region, so that the thickness of the first silicon nitride layer located on the top surface, side surface of the gate structure and the bottom surface of the spacer region reaches the required value.

2. The method for manufacturing a semiconductor device using stress memory technology according to claim 1, wherein: In step 2, before forming the first silicon nitride layer, a step of forming a second silicon oxide layer is also included.

3. The method for manufacturing a semiconductor device using stress memory technology according to claim 2, wherein: After step 2, an annealing process is further included, wherein the annealing process transfers the tensile stress of the first silicon nitride layer to the channel region.

4. The method for manufacturing a semiconductor device using stress memory technology according to claim 3, characterized in that: The annealing process adopts a rapid thermal annealing process.

5. The method for manufacturing a semiconductor device using stress memory technology according to claim 4, characterized in that: The semiconductor device comprises NMOS and PMOS, and the NMOS and the PMOS are integrated on the semiconductor substrate at the same time.

6. The method for manufacturing a semiconductor device using stress memory technology according to claim 4, characterized in that: Before performing the annealing process, the step of removing the first silicon nitride layer in the PMOS formation region is also included; or, after step 2 is completed, the annealing process is performed under the condition that the first silicon nitride layer is retained in the PMOS formation region.

7. The method for manufacturing a semiconductor device using stress memory technology according to claim 5, characterized in that: The semiconductor substrate includes a silicon substrate.

8. The method for manufacturing a semiconductor device using stress memory technology according to claim 7, characterized in that: The gate structure is formed by stacking a gate dielectric layer and a polysilicon gate.

9. The method for manufacturing a semiconductor device using stress memory technology according to claim 7, wherein: In the NMOS formation region, a P well is formed in the semiconductor substrate; and in the PMOS formation region, an N well is formed in the semiconductor substrate.

10. The method for manufacturing a semiconductor device using stress memory technology according to claim 8, characterized in that: Before step 2, the method further includes the step of forming a sidewall spacer on the side of the gate structure.

11. The method for manufacturing a semiconductor device using stress memory technology according to claim 10, characterized in that: After the sidewall spacer is formed, the method further includes forming a source region and a drain region in the semiconductor substrate on both sides of the gate structure.

12. The method for manufacturing a semiconductor device using stress memory technology according to claim 11, characterized in that: After the annealing process is completed, the step of removing the first silicon nitride layer is also included; Alternatively, after the annealing process is completed, the first silicon nitride layer is retained and serves as a contact etching stop layer.

13. The method for manufacturing a semiconductor device using stress memory technology according to claim 8, wherein: The technology node of the semiconductor device is below 28nm.

14. The method for manufacturing a semiconductor device using stress memory technology according to claim 13, characterized in that: The required thickness of the first silicon nitride layer is greater than 30 nm.

15. The method for manufacturing a semiconductor device using stress memory technology according to claim 14, characterized in that: The thickness of the first silicon nitride sub-layer is 10 nm, and the thickness of the second silicon nitride sub-layer is greater than 20 nm.

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