Semiconductor structure

Abstract

A semiconductor structure is provided. The semiconductor structure includes a wafer and a test structure. The test structure is disposed on the wafer and includes a first element and a second element. The first element includes a first source / drain layer and a first gate layer disposed on the first source / drain layer. The second element includes a second source / drain layer and a second gate layer disposed on the second source / drain layer. The second gate layer is connected to the first gate layer. The first gate layer is disposed along a first direction, and the second gate layer is disposed along a second direction orthogonal to the first direction.

Description

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 008,963, filed September 1, 2020, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0002] The present disclosure relates to a semiconductor structure. In particular, the present disclosure relates to a semiconductor structure with a test structure. BACKGROUND

[0003] In the manufacturing process of a memory device, a plurality of manufacturing steps are required to form the desired device. For example, in the manufacturing process of a DRAM, a capacitor and a transistor are formed through a plurality of steps. To ensure that the device structure is completely formed on a wafer through the plurality of manufacturing steps, a test structure is usually formed on the wafer to test the function of the device during the manufacturing process of the device.

[0004] The above discussion of the background art is provided merely to facilitate more fully understanding of the present disclosure and should not be construed as an admission that any of the above-discussed art was prior art to the present disclosure. SUMMARY

[0005] The present disclosure provides a semiconductor structure including a wafer and a test structure. The test structure is disposed on the wafer and includes a first element and a second element. The first element includes a first source / drain layer and a first gate layer disposed on the first source / drain layer. The second element includes a second source / drain layer and a second gate layer disposed on the second source / drain layer. The second gate layer is connected to the first gate layer. The first gate layer is disposed along a first direction and the second gate layer is disposed along a second direction orthogonal to the first direction.

[0006] In some embodiments, the first source / drain layer and the second gate layer are separated by a first distance, the second source / drain layer and the first gate layer are separated by a second distance, and the first distance is greater than the second distance.

[0007] In some embodiments, the first distance is along a first direction and the second distance is along a second direction.

[0008] In some embodiments, the test structure further includes a third element. The third element is disposed adjacent to the second element and includes a third source / drain layer. The second gate layer is disposed on the third source / drain layer.

[0009] In some embodiments, the first source / drain layer and the second gate layer are separated by a first distance, the second source / drain layer and the third source / drain layer are separated by a second distance, and the first distance is greater than the first distance.

[0010] In some embodiments, the test structure further includes a third element. The third element is disposed adjacent to the first element and includes the third source / drain layer. The first gate layer is disposed on the third source / drain layer.

[0011] In some embodiments, the first source / drain layer and the third source / drain layer are separated by a first distance, the second source / drain layer and the first gate layer are separated by a second distance, and the first distance is greater than the first distance.

[0012] In some embodiments, the test structure is disposed in a scribe line of the wafer.

[0013] The present disclosure also provides a semiconductor structure including a wafer and a test structure. The test structure is disposed on the wafer and includes a first source / drain layer, a second source / drain layer, and a gate layer. The gate layer includes a first portion and a second portion. The first portion is disposed on the first source / drain layer. The second portion is disposed on the second source / drain layer. The first portion is disposed along a first direction and the second portion is disposed along a second direction orthogonal to the first direction.

[0014] In some embodiments, the first source / drain layer and the second portion are separated by a first distance, the second source / drain layer and the first portion are separated by a second distance, and the first distance is greater than the second distance.

[0015] In some embodiments, the first distance is along the first direction and the second distance is along the second direction.

[0016] In some embodiments, the test structure further includes a third source / drain layer. The third source / drain layer is disposed adjacent to the second source / drain layer. The second portion of the gate layer is disposed on the third source / drain layer.

[0017] In some embodiments, the first source / drain layer and the second portion are separated by a first distance, the second source / drain layer and the third source / drain layer are separated by a second distance, and the first distance is greater than the second distance.

[0018] In some embodiments, the test structure further includes a third source / drain layer. The third source / drain layer is disposed adjacent to the first source / drain layer. The first portion of the gate layer is disposed on the third source / drain layer.

[0019] In some embodiments, the first source / drain layer and the third source / drain layer are separated by a first distance, the second source / drain layer and the first portion are separated by a second distance, and the first distance is greater than the second distance.

[0020] In some embodiments, the test structure is disposed in a scribe line of the wafer.

[0021] The present disclosure also provides a semiconductor structure including a wafer and a test structure. The wafer includes a first scribe line and a second scribe line orthogonal to the first scribe line. The test structure is disposed in the first scribe line of the wafer and includes a first element and a second element. The first element includes a first gate layer along a first direction. The second element includes a second gate layer along a second direction orthogonal to the first direction. The second gate layer is connected to the first gate layer.

[0022] In some embodiments, the test structure further includes a third element. The third element is disposed adjacent to the second element. The second gate layer is disposed in the third element.

[0023] In some embodiments, the test structure further includes a third element. The third element is disposed adjacent to the first element. The first gate layer is disposed in the third element.

[0024] In some embodiments, the second element is disposed between the first element and the third element.

[0025] The foregoing has outlined rather broadly the technical features and advantages of the present disclosure so that the detailed description of the present disclosure that follows can be understood. Additional technical features and advantages of the present disclosure will be described below. Those skilled in the art will appreciate that the conception, upon which, the disclosure is based, can be readily utilized as the basis for the designing of other structures, methods, or themselves the same purposes as the present disclosure. It will be appreciated by those skilled in the art that those who have knowledge in the art of the present disclosure can easily utilize the concept disclosed in the following embodiments to modify or design other structures or processes for the same purposes as the present disclosure without departing from the spirit and scope of the present disclosure as defined by the following claims. BRIEF DESCRIPTION OF DRAWINGS

[0026] The disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which like reference numerals refer to like elements throughout the figures, and in which:

[0027] Figure 1 A top-down schematic view of a semiconductor structure illustrating some embodiments of the present disclosure.

[0028] Figure 2 A top-down schematic view of a known semiconductor structure.

[0029] Figure 3A top view schematic of a semiconductor structure illustrating some embodiments of the present disclosure.

[0030] Figure 4 A top view schematic of a semiconductor structure illustrating some embodiments of the present disclosure.

[0031] Figure 5 A top view schematic of a semiconductor structure illustrating some embodiments of the present disclosure.

[0032] Figure 6 A top view schematic of a semiconductor structure illustrating some embodiments of the present disclosure.

[0033] Figure 7 A top view schematic of a semiconductor structure illustrating some embodiments of the present disclosure.

[0034] The following reference signs are used in the drawings:

[0035] 10: semiconductor structure

[0036] 12: wafer

[0037] 14: test structure

[0038] 34: test structure

[0039] 44: test structure

[0040] 54: test structure

[0041] 64: test structure

[0042] 74: test structure

[0043] 121: scribe line

[0044] 122: scribe line

[0045] 141: first element

[0046] 141a: source / drain layer

[0047] 141b: gate layer

[0048] 142: second element

[0049] 142a: source / drain layer

[0050] 142b: gate layer

[0051] 200: semiconductor structure

[0052] 210: wafer

[0053] 220: first test structure

[0054] 230: second test structure

[0055] 240: cutting line

[0056] 250: cutting line

[0057] 341: first element

[0058] 342: second element

[0059] 342b: gate layer

[0060] 441: first element

[0061] 441a: source / drain layer

[0062] 441b: gate layer

[0063] 442: second element

[0064] 442a: source / drain layer

[0065] 442b: gate layer

[0066] 443: third element

[0067] 443a: source / drain layer

[0068] 541: first element

[0069] 541a: source / drain layer

[0070] 542: second element

[0071] 542a: source / drain layer

[0072] 542b: gate layer

[0073] 543: third element

[0074] 543a: source / drain layer

[0075] 641: first element

[0076] 641a: source / drain layer

[0077] 641b: gate layer

[0078] 642: second element

[0079] 642a: source / drain layer

[0080] 642b: gate layer

[0081] 643: third element

[0082] 643a: source / drain layer

[0083] 741: first element

[0084] 741: first element

[0085] 741a: source / drain layer

[0086] 741b: gate layer

[0087] 742: second element

[0088] 742a: source / drain layer

[0089] 742b: gate layer

[0090] 742: second element

[0091] 743: third element

[0092] 743a: source / drain layer

[0093] D1: first distance

[0094] D2: second distance DETAILED DESCRIPTION

[0095] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure. In the drawings:

[0096] "An embodiment," "one embodiment," "an example embodiment," "some embodiments," "another embodiment," "one implementation," "an implementation," "some implementations," "another implementation," and the like, refer to particular embodiments of the present disclosure. However, the present disclosure is not limited to this numbered list of embodiments. It is likely that one or more of the embodiments described below will include one or more of the features of the other embodiments. It is further likely that one or more of the embodiments described below will be omitted from one or more of the other embodiments. The following listed embodiments do not necessarily represent all the implementations of the techniques described in this disclosure. Accordingly, the term "embodiment" should be interpreted as "one embodiment, among others."

[0097] In order that the disclosure can be fully understood, the following description provides detailed steps and structures. It is apparent that the implementation of the present disclosure will not limit the specific details set forth herein, as some steps and structures can involve conventional components that are known to those skilled in the art. In addition, known structures and steps are not described in detail in order to not unnecessarily obscure the disclosure. Preferred embodiments of the present disclosure are described in detail below. However, the present disclosure can also be embodied in other embodiments. The scope of the present disclosure is not limited to the detailed description, but is defined by the claims.

[0098] It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different characteristics of the application. Numerous specific details are set forth in order to provide a thorough understanding of the various embodiments or examples. However, it is recognized that embodiments might be practiced without one or more of the specific details or with perhaps additional details. In other instances, well-known methods, procedures, components, and networks have not been described in detail so as not to unnecessarily obscure aspects of the embodiments.

[0099] Moreover, for ease of explanation, the present application might use spatial relative terms, such as "beneath", "below", "lower", "above", "upper", etc., to describe the relationship between one element or feature in a view and another element or feature. Such spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0100] It is to be understood that, for clarity and simplicity, Figures 3 to 7 In addition, Figures 3 to 7 Similar elements can include similar materials, and therefore repetitive description of these details is omitted for brevity.

[0101] In accordance with some embodiments of the present disclosure, Figure 1 A top view schematic of a semiconductor structure 10 is illustrated to exemplify some embodiments of the present disclosure. Referring to FIG. 1, the semiconductor structure 10 includes a wafer 12 and a test structure 14. Figure 1 In some embodiments, the semiconductor structure 10 includes the wafer 12 and the test structure 14.

[0102] In some embodiments, the wafer 12 can be made of a semiconductor material, and the wafer 12 can be, but is not limited to, a bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) wafer, or a silicon germanium wafer. In addition, the wafer 12 can also use other semiconductor materials including Group III, Group IV, or Group V elements. In some embodiments, the wafer 12 includes a dicing line 121 and a dicing line 122. The dicing line 121 and the dicing line 122 are orthogonal to each other. In some embodiments, the dicing line 121 and the dicing line 122 serve to dice the wafer 12 into a plurality of semiconductor elements (e.g., dies).

[0103] In some embodiments, the test structure 14 is disposed on the wafer 12. In some embodiments, the test structure 14 is disposed in a scribe line 121 of the wafer 12. In other words, when the wafer 12 is cut into a plurality of semiconductor elements, the test structure 14 is removed during the cutting operation.

[0104] The test structure 14 includes a first element 141 and a second element 142. The first element 141 includes a source / drain layer 141a and a gate layer 141b. The gate layer 141b is disposed on the source / drain layer 141a. In some embodiments, the source / drain layer 141a is an N-doped layer or a P-doped layer in the wafer 12. It is to be understood that the source / drain layer 141a can include a source region and a drain region in the wafer 12. In some embodiments, the gate layer 141b is made of a semiconductor material, which can be but is not limited to polysilicon. The gate layer 141b is disposed along a first direction Y.

[0105] The second element 142 includes a source / drain layer 142a and a gate layer 142b. The gate layer 142b is disposed on the source / drain layer 142a. In some embodiments, the source / drain layer 142a is an N-doped layer or a P-doped layer in the wafer 12. It is to be understood that the source / drain layer 142a can include a source region and a drain region in the wafer 12. In some embodiments, the gate layer 142b is made of a semiconductor material, which can be but is not limited to polysilicon. The gate layer 142b is disposed along a second direction X. The first direction Y and the second direction X are orthogonal to each other. In some embodiments, the gate layer 142b is connected to the gate layer 141b. The gate layer 141b and the gate layer 142b can be formed in the same operation. In some embodiments, the gate layer 141b and the gate layer 142b are integrally formed. It is to be understood that when the gate layer is integrally formed, the gate layer 141b refers to a first portion of the integrally formed gate layer, and the gate layer 142b refers to a second portion of the integrally formed gate layer.

[0106] In some embodiments, the source / drain layer 141a and the gate layer 142b are separated by a first distance D1. In some embodiments, the source / drain layer 142a and the gate layer 141b are separated by a second distance D2. The first distance D1 can be greater than the second distance D2. In other embodiments, the first distance D1 can be less than the second distance D2.

[0107] In some embodiments, the gate layer 141b of the first element 141 disposed along the first direction Y can be used to test the effect of the difference in lattice direction between the test gate layer 141b and the wafer 12. In other words, the lattice direction (e.g., along the first direction Y) of the material (e.g., polysilicon) of the gate layer 141b can be different from the lattice direction (e.g., along the second direction X) of the material (e.g., silicon) of the wafer 12. The difference in lattice direction between the gate layer 141b and the wafer 12 can affect the electronic properties of the first element 141.

[0108] In some embodiments, the second element 142 can be used to test the effect of the variation of dopants in the source / drain layer 142a. In contrast to the first element 141, the lattice direction (e.g., along the first direction Y) of the material (e.g., polysilicon) of the gate layer 142b can be the same as the lattice direction (e.g., along the second direction X) of the wafer 12, and thus the effect of the difference in lattice direction can be observed in the second element 142. However, the variation of dopants in the source / drain layer 142a of the second element 142 disposed along the second direction X has a greater effect on the electronic properties of the second element 142 than the effect of the difference in lattice direction.

[0109] Figure 2 An exemplary top view of a known semiconductor structure 200 is illustrated. Referring to Figure 2 , the semiconductor structure 200 includes a wafer 210, a first test structure 220, and a second test structure 230. The first test structure 220 is disposed in a scribe line 240 along a first direction Y. The second test structure 230 is disposed in a scribe line 250 along a second direction X. The scribe line 240 and the scribe line 250 are orthogonal to each other.

[0110] In the semiconductor structure 200, the first test structure 220 can be used to test the effect of the variation of dopants in the source / drain layer 221. The second test structure 230 can be used to test the effect of the difference in lattice direction between the gate layer 231 and the wafer 210. In the semiconductor structure 200, the first test structure 220 and the second test structure 230 are formed in different scribe lines 240 and 250, respectively. Thus, the test operations for different purposes can need to be performed separately. In other words, the test operations for the effect of the variation of dopants and the effect of the difference in lattice direction can need to be performed in separate operations.

[0111] Returning to Figure 1Unlike the known semiconductor structure 200, the test structure 14 of the semiconductor structure 10 of the present disclosure includes a first element 141 and a second element 142. The first element 141 serves as a test of the effect of the lattice direction difference between the gate layer 141b and the wafer 12, while the second element 142 serves as a test of the effect of the doping variation in the source / drain layer 142a. In other words, the test structure 14 of the present disclosure can serve as different test purposes. The test operations of the test structure 14 of the present disclosure can be performed in the same operation. Compared with the known semiconductor structure 200, the test efficiency can be improved.

[0112] According to some embodiments of the present disclosure, Figure 3 is a top view schematic diagram of a test structure 34. Referring to Figure 3 In some embodiments, the test structure 34 includes a first element 341 and a second element 342. The first element 341 is similar to the first element 141 in Figure 1 For brevity, it will not be described here again.

[0113] Figure 3 The difference between the test structure 34 in Figure 1 and the test structure 14 in Figure 1 is that the gate layer 342b of the second element 342 is arranged in the opposite direction to the gate layer 142b of the second element 142 in Figure 3 As shown in Figure 1 , the gate layer 342b is arranged to the right (or positive direction) along the second direction X, while the gate layer 142b is arranged to the left (or negative direction) along the second direction X as shown in

[0114] In summary, the test structure 34 of the present disclosure includes a first element 341 and a second element 342 serving as different test purposes. The test operations of the test structure 34 of the present disclosure can be performed in the same operation. Compared with the known semiconductor structure 200 in Figure 2 , the test efficiency can be improved. In addition, the gate layer 342b of the second element 342 can be arranged in different directions corresponding to the first element 341 to increase the design freedom.

[0115] Figure 4 is a top view schematic diagram of a test structure 44. Referring to Figure 4 In some embodiments, the test structure 44 includes a first element 441, a second element 442, and a third element 443. The first element 441 and the second element 442 are similar to the first element 141 and the second element 142 in Figure 1 For brevity, it will not be described here again.

[0116] Figure 4 The difference between the test structure 44 in Figure 1The difference between the test structure 14 in the and the test structure 44 in the is that the test structure 44 includes a third element 443, which is disposed adjacent to the first element 441 and the second element 442. The third element 443 includes a source / drain layer 443a, and the gate layer 441b of the first element 441 is disposed on the source / drain layer 443a. In some embodiments, the second element 442 is disposed between the first element 441 and the third element 443.

[0117] In some embodiments, the source / drain layer 441a and the source / drain layer 443a are separated by a first distance D1. In some embodiments, the source / drain layer 442a and the gate layer 441b are separated by a second distance D2. In some embodiments, the first distance D1 can be greater than the second distance D2. In other embodiments, the first distance D1 can be less than the second distance D2.

[0118] In summary, the test structure 44 of the present disclosure includes the first element 441, the second element 442, and the third element 443 for different test purposes. The test operations of the test structure 44 of the present disclosure can be performed in the same operation. Compared with the known semiconductor structure 200 in the Figure 2 , the test efficiency can be improved. In addition, the first element 441 and the third element 443 can also be used to test the effect of the difference in lattice direction between adjacent two elements.

[0119] Figure 5 A top view schematic diagram of a test structure 54 illustrating some embodiments of the present disclosure is shown. Referring to Figure 5 , in some embodiments, the test structure 54 includes a first element 541, a second element 542, and a third element 543. The first element 541 and the third element 543 are similar to the first element 441 and the third element 443 in the Figure 4 . For brevity, they will not be described in detail here. In some embodiments, the first distance D1 (i.e., the distance between the source / drain layer 541a and the source / drain layer 543a) is greater than the second distance D2 (i.e., the distance between the source / drain layer 542a and the gate layer 541b). In other embodiments, the first distance D1 can be less than the second distance D2.

[0120] The difference between the test structure 54 and the test structure 44 in the Figure 4 is that the gate layer 542b of the second element 542 is disposed in the opposite direction to the direction of the gate layer 442b of the second element 442 in the Figure 4 . As shown in Figure 5 , the gate layer 542b is disposed to the right (or positive direction) along the second direction X, while as shown in Figure 4 , the gate layer 442b is disposed to the left (or negative direction) along the second direction X.

[0121] In summary, the test structure 54 of the present disclosure includes the first element 541, the second element 542, and the third element 543 for different testing purposes. The testing operations of the test structure 54 of the present disclosure can be performed in the same operation. Compared with the known semiconductor structure 200 in Figure 2 , the testing efficiency can be improved. The first element 541 and the third element 543 can also be used for testing the effect of the difference in lattice direction between adjacent two elements. In addition, the gate layer 542b of the second element 542 can be arranged in different directions corresponding to the first element 541 and the third element 543 to increase the design freedom.

[0122] Figure 6 A top view schematic diagram of a test structure 64 illustrating some embodiments of the present disclosure is shown. Referring to Figure 6 , in some embodiments, the test structure 64 includes a first element 641, a second element 642, and a third element 643. The first element 641 and the second element 642 are similar to the first element 141 and the second element 142 in Figure 1 . For brevity, they will not be described in detail here. In some embodiments, the first distance D1 (i.e., the distance between the source / drain layer 641a and the gate layer 642b) is greater than the second distance D2 (i.e., the distance between the source / drain layer 642a and the source / drain layer 643a). In other embodiments, the first distance D1 can be less than the second distance D2.

[0123] The difference between the test structure 64 and the test structure 14 in Figure 1 is that the test structure 64 includes the third element 643 arranged adjacent to the first element 641 and the second element 642. The third element 643 includes a source / drain layer 643a, and the gate layer 642b of the second element 642 is arranged on the source / drain layer 643a. In other words, the second element 642 and the third element 643 are formed with the same gate layer 642b. In some embodiments, the first element 641 is arranged between the second element 642 and the third element 643.

[0124] In summary, the test structure 64 of the present disclosure includes the first element 641, the second element 642, and the third element 643 for different testing purposes. The testing operations of the test structure 64 of the present disclosure can be performed in the same operation. Compared with the known semiconductor structure 200 in Figure 2 , the testing efficiency can be improved. In addition, the second element 642 and the third element 643 can also be used for testing the change in doping between the source / drain layers 642a and 643a of adjacent two elements.

[0125] Figure 7 A top view schematic diagram of a test structure 74 illustrating some embodiments of the present disclosure is shown. Referring toFigure 7 In some embodiments, the test structure 74 includes a first element 741, a second element 742, and a third element 743. The first element 741 and the second element 742 are similar to the first element 641 and the second element 642 in Figure 6 for brevity. In some embodiments, the first distance Dl (i.e., the distance between the source / drain layer 741a and the gate layer 742b) is greater than the second distance D2 (i.e., the distance between the source / drain layer 742a and the source / drain layer 743a). In other embodiments, the first distance Dl can be less than the second distance D2.

[0126] Figure 7 The difference between the test structure 74 in Figure 1 and the test structure 14 in Figure 6 is that the gate layer 741b of the first element 741 is disposed in the opposite direction from the gate layer 641b of the first element 641 in Figure 7 . The gate layer 741b is disposed along the Y direction upward (or positive direction) in Figure 6 , while the gate layer 641b is disposed along the Y direction downward (or negative direction) in Figure 6 .

[0127] In summary, the test structure 74 of the present disclosure includes the first element 741, the second element 742, and the third element 743 for different testing purposes. The testing operations of the test structure 74 of the present disclosure can be performed in the same operation. Compared with the well-known semiconductor structure 200 in Figure 2 , the testing efficiency can be improved. The second element 742 and the third element 743 can also be used to test the effect of the doping change in the source / drain layer 742a and 743a between two adjacent elements. In addition, the gate layer 741b of the first element 741 can be disposed along different directions corresponding to the second element 742 and the third element 743 to increase the design freedom.

[0128] It should be understood that Figure 1 , Figure 3 , Figure 4 , Figure 5 , Figure 6 and Figure 7 can be combined to form different patterns.

[0129] While the present disclosure and its advantages have been detailed, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the

[0130] Moreover, the scope of the application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the application is open to equivalents and substitutions without departing from the scope of the application. It is expressly intended that all combinations of those elements that are described by the word "comprising" or "having," or any other open-ended term to be within the scope of the application. Where the disclosure describes that functions were performed, it is to be understood that such functions can be performed in one or more of the ways described, and need not be performed by one of only the described ways. Therefore, the scope of the application is not to be determined by limitation of the specification, but only by the claims.

Claims

1. A semiconductor structure, comprising: a wafer; and a test structure disposed on the wafer and comprising: a first element comprising a first source / drain layer and a first gate layer, wherein the first gate layer is disposed on the first source / drain layer; and a second element comprising a second source / drain layer and a second gate layer, wherein the second gate layer is disposed on the second source / drain layer and the second gate layer is connected to the first gate layer; wherein the first gate layer is disposed along a first direction and the second gate layer is disposed along a second direction, the first direction being orthogonal to the second direction; a crystal lattice direction of a material of the first gate layer of the first element disposed along the first direction is different from a crystal lattice direction of a material of the wafer, and a crystal lattice direction of a material of the second gate layer of the second element is the same as the crystal lattice direction of the wafer.

2. The semiconductor structure of claim 1, wherein the first source / drain layer and the second gate layer are separated by a first distance, the second source / drain layer and the first gate layer are separated by a second distance, and the first distance is greater than the second distance.

3. The semiconductor structure of claim 2, wherein the first distance is along the first direction and the second distance is along the second direction.

4. The semiconductor structure of claim 1, wherein the test structure further comprises: a third element disposed adjacent to the second element and comprising a third source / drain layer, wherein the second gate layer is disposed on the third source / drain layer.

5. The semiconductor structure of claim 4, wherein the first source / drain layer and the second gate layer are separated by a first distance, the second source / drain layer and the third source / drain layer are separated by a second distance, and the first distance is greater than the second distance.

6. The semiconductor structure of claim 1, wherein the test structure further comprises: a third element disposed adjacent to the first element and comprising a third source / drain layer, wherein the first gate layer is disposed on the third source / drain layer.

7. The semiconductor structure of claim 6, wherein the first source / drain layer and the third source / drain layer are separated by a first distance, the second source / drain layer and the first gate layer are separated by a second distance, and the first distance is greater than the second distance.

8. The semiconductor structure of claim 5, wherein the test structure is disposed in a scribe line of the wafer.

9. A semiconductor structure, comprising: a wafer; and a test structure disposed on the wafer and comprising: a first source / drain layer; a second source / drain layer; and a gate layer comprising a first portion and a second portion, the first portion being disposed on the first source / drain layer and the second portion being disposed on the second source / drain layer; wherein the first portion is disposed along a first direction and the second portion is disposed along a second direction orthogonal to the first direction. ​ ​ a lattice direction of a material of the first portion of the gate layer is different from a lattice direction of a material of the wafer, and a lattice direction of a material of the second portion of the gate layer is the same as the lattice direction of the wafer.

10. The semiconductor structure of claim 9, wherein the first source / drain layer and the second portion are separated by a first distance, the second source / drain layer and the first portion are separated by a second distance, and the first distance is greater than the second distance.

11. The semiconductor structure of claim 10, wherein the first distance is along the first direction and the second distance is along the second direction.

12. The semiconductor structure of claim 9, wherein the test structure further comprises: a third source / drain layer disposed adjacent to the second source / drain layer, wherein the second portion of the gate layer is disposed on the third source / drain layer.

13. The semiconductor structure of claim 12, wherein the first source / drain layer and the second portion are separated by a first distance, the second source / drain layer and the third source / drain layer are separated by a second distance, and the first distance is greater than the second distance.

14. The semiconductor structure of claim 9, wherein the test structure further comprises: a third source / drain layer disposed adjacent to the first source / drain layer, wherein the first portion of the gate layer is disposed on the third source / drain layer.

15. The semiconductor structure of claim 14, wherein the first source / drain layer and the third source / drain layer are separated by a first distance, the second source / drain layer and the first portion are separated by a second distance, and the first distance is greater than the second distance.

16. The semiconductor structure of claim 9, wherein the test structure is disposed in a scribe line of the wafer.

17. A semiconductor structure, comprising: a wafer including a first scribe line and a second scribe line orthogonal to the first scribe line; and a test structure disposed in the first scribe line of the wafer and including: a first element including a first gate layer along a first direction; and a second element including a second gate layer along a second direction orthogonal to the first direction, wherein the second gate layer connects the first gate layer; a lattice direction of a material of the first gate layer of the first element disposed along the first direction is different from a lattice direction of a material of the wafer, and a lattice direction of a material of the second gate layer of the second element is the same as the lattice direction of the wafer.

18. The semiconductor structure of claim 17, wherein the test structure further comprises: a third element disposed adjacent to the second element, wherein the second gate layer is disposed in the third element.

19. The semiconductor structure of claim 17, wherein the test structure further comprises: a third element disposed adjacent to the first element, wherein the first gate layer is disposed in the third element.

20. The semiconductor structure of claim 19, wherein the second element is disposed between the first element and the third element.

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