Thin film transistor and manufacturing method thereof, array substrate, display panel and device

Abstract

The present invention discloses a thin film transistor and a manufacturing method thereof, an array substrate, a display panel, and a device, wherein the thin film transistor includes: a substrate; a first active layer located on one side of the substrate and having a first middle region and a first edge portion, the first middle portion being located between the first edge portions; a second active layer located at least on the surface of the first middle portion; a first protective layer covering at least the first edge portion of the first active layer; a source and drain electrode located on a side of the second active layer away from the substrate and connected to the second active layer; a gate layer located on a side of the second active layer away from the substrate, or located on a surface of the substrate close to the first active layer; wherein the first active layer and the second active layer are made of different materials. The thin film transistor can have good uniformity and no hump phenomenon when the first active layer and the second active layer are made of materials with any etching selectivity, thereby ensuring good stability of the thin film transistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a thin film transistor and a manufacturing method thereof, an array substrate, a display panel, and a device. Background Art

[0002] Currently, thin-film transistor devices with two active layers are an important development direction in the display technology field. However, during the manufacturing process of existing thin-film transistor structures, if the etching rate of the material used for the lower active layer is much higher than that of the upper active layer, the lower active layer will develop an undercut structure after etching. This undercut structure can lead to poor uniformity of the thin-film transistor and the appearance of a hump.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] The purpose of the present disclosure is to overcome the shortcomings of the above-mentioned prior art thin film transistors with poor uniformity and hump phenomenon, and to provide a thin film transistor with better uniformity and a manufacturing method thereof, an array substrate, a display panel and a device.

[0005] A first aspect of the present disclosure provides a thin film transistor, comprising:

[0006] substrate;

[0007] a first active layer located on one side of the substrate, wherein the first active layer has a first middle portion and a first edge portion, wherein the first middle portion is located between the first edge portions;

[0008] a second active layer located at least on a surface of the first middle portion;

[0009] a first protective layer, covering at least a first edge portion of the first active layer;

[0010] a source and drain electrode, located on a side of the second active layer away from the substrate and connected to the second active layer;

[0011] a gate layer, located on a side of the second active layer away from the substrate, or located on a surface of the substrate close to the first active layer;

[0012] The first active layer and the second active layer are made of different materials.

[0013] In an exemplary embodiment of the present disclosure, the second active layer has a second middle portion and a second edge portion, wherein the second middle portion is located on a surface of the first middle portion, and the second edge portion is located on a surface of the first protective layer away from the first edge portion and a portion of a surface of the second middle portion; the thin film transistor further comprises:

[0014] A first gate insulating layer, wherein the first gate insulating layer at least covers the second active layer, and the gate layer is located on a surface of the first gate insulating layer away from the first active layer.

[0015] In an exemplary embodiment of the present disclosure, the thin film transistor further includes:

[0016] a first interlayer dielectric layer, the first interlayer dielectric layer is located on a surface of the first gate insulating layer away from the second active layer and covers the gate layer, a first through hole is provided on the first interlayer dielectric layer and the first gate insulating layer, the source and drain are located on a surface of the first interlayer dielectric layer away from the second active layer, and are connected to the second active layer through the first through hole.

[0017] In an exemplary embodiment of the present disclosure, the material of the first active layer is crystalline oxide.

[0018] In an exemplary embodiment of the present disclosure, the first protective layer and the second active layer are made of the same material and are connected to each other; the thin film transistor further comprises:

[0019] A second gate insulating layer covers the first protection layer and the second active layer, and the gate layer is located on a surface of the second gate insulating layer.

[0020] In an exemplary embodiment of the present disclosure, a first distance is provided between an edge of the first protection layer away from the first edge portion and the first edge portion, and the first distance is between 0.4 μm and 1.2 μm.

[0021] In an exemplary embodiment of the present disclosure, the thin film transistor further includes:

[0022] a second interlayer dielectric layer, the second interlayer dielectric layer is located on a surface of the second gate insulating layer away from the second active layer and covers the gate layer, the second interlayer dielectric layer and the second gate insulating layer are provided with second through holes, the source and drain are located on a surface of the second interlayer dielectric layer on a side away from the second active layer, and the source and drain are connected to the first protective layer through the second through holes.

[0023] In an exemplary embodiment of the present disclosure, the gate layer is located on a surface of the substrate close to the first active layer, and the thin film transistor further includes:

[0024] A third gate insulating layer covers the gate, and the first active layer is located on a surface of the third gate insulating layer away from the substrate.

[0025] In an exemplary embodiment of the present disclosure, the second active layer has a third middle portion and a third edge portion, wherein the third middle portion is located on the surface of the first middle portion, the third edge portion is located on the surface of the first protective layer away from the first edge portion and part of the surface of the third middle portion, and the source and drain are at least located on the surface of the third edge portion.

[0026] In an exemplary embodiment of the present disclosure, the first protective layer and the second active layer are made of the same material, and the first protective layer and the second active layer are connected to each other, and the source and drain are at least located on the surface of the first protective layer and a portion of the second active layer.

[0027] In an exemplary embodiment of the present disclosure, the thin film transistor further includes:

[0028] A second protective layer at least covers the second active layer and the source and drain electrodes.

[0029] A second aspect of the present disclosure provides a method for manufacturing a thin film transistor, comprising:

[0030] providing a substrate;

[0031] forming a first active layer on one side of the substrate, the first active layer having a first middle portion and a first edge portion, wherein the first middle portion is located between the first edge portions;

[0032] Disposing a first protective layer on a first edge portion of the first active layer so that the first protective layer at least covers the first edge portion, and forming a second active layer on a surface of the first middle portion;

[0033] After forming the first protective layer, forming a gate layer on a side of the second active layer away from the substrate, or before forming the first active layer, forming a gate layer on a surface of the substrate close to the first active layer;

[0034] forming a source and a drain electrode on a side of the second active layer away from the substrate, and connecting the source and the drain electrode to the second active layer;

[0035] The first active layer and the second active layer are made of different materials.

[0036] In an exemplary embodiment of the present disclosure, after forming the first protective layer, a gate layer is formed on a side of the second active layer away from the substrate; and forming the first active layer on one side of the substrate includes:

[0037] depositing a first active layer on one side of the substrate and patterning the first active layer;

[0038] An annealing process is performed on the patterned first active layer to crystallize the patterned first active layer.

[0039] In an exemplary embodiment of the present disclosure, the temperature of the annealing treatment is greater than or equal to 350° C., and the time range of the annealing treatment is between 0.5 hours and 1.5 hours.

[0040] In an exemplary embodiment of the present disclosure, the step of providing a first protective layer on a first edge portion of the first active layer so that the first protective layer covers at least the first edge portion, and forming a second active layer on a surface of the first middle portion includes:

[0041] forming the first protective layer covering the first active layer;

[0042] Etching the first protective layer to expose a first middle portion of the first active layer;

[0043] A second active layer is deposited on a surface of the remaining first protection layer away from the first active layer and a surface of the first middle portion, and the second active layer is patterned.

[0044] In an exemplary embodiment of the present disclosure, after forming the first protection layer, forming a gate layer on a side of the second active layer away from the substrate includes:

[0045] forming a first gate insulating layer covering at least the second active layer;

[0046] A gate layer is formed on a side of the first gate insulating layer away from the second active layer, and the gate layer is patterned.

[0047] In an exemplary embodiment of the present disclosure, the second active layer may have a second middle portion and a second edge portion, the second edge portion being located on a surface of the first protective layer away from the first edge portion and a portion of a surface of the second middle portion, and the source and drain electrodes are formed on a side of the second active layer away from the substrate and connected to the second active layer, including:

[0048] forming a first interlayer dielectric layer on a surface of the first gate insulating layer away from the second active layer, and making the first interlayer dielectric layer cover the gate layer;

[0049] etching the first interlayer dielectric layer and the first gate insulating layer to form a first through hole and expose a surface of the second edge portion;

[0050] A material for forming source and drain electrodes is deposited on the surface of the first interlayer dielectric layer and in the first through hole and patterned to form source and drain electrodes connected to the second edge portion.

[0051] In an exemplary embodiment of the present disclosure, after forming the first protective layer, a gate layer is formed on a side of the second active layer away from the substrate; providing the first protective layer on a first edge portion of the first active layer so that the first protective layer at least covers the first edge portion, and forming the second active layer on a surface of the first middle portion, includes:

[0052] A first protection layer covering the first edge portion and a second active layer located on the surface of the first middle portion are formed by using the same material and adopting the same step, and the first protection layer and the second active layer are connected.

[0053] In an exemplary embodiment of the present disclosure, after forming the first protection layer, forming a gate layer on a side of the second active layer away from the substrate includes:

[0054] forming a second gate insulating layer covering the first protective layer and the second active layer;

[0055] A gate layer is formed on the surface of the second insulating gate layer, and the gate layer is patterned.

[0056] In an exemplary embodiment of the present disclosure, forming a source and a drain on a side of the second active layer away from the substrate and connecting the source and the drain to the second active layer includes:

[0057] forming a second interlayer dielectric layer on a surface of the second gate insulating layer away from the second active layer, and making the second interlayer dielectric layer cover the gate layer;

[0058] etching the second interlayer dielectric layer and the second gate insulating layer to form a second through hole and expose a surface of the first protective layer;

[0059] A material for forming source and drain electrodes is deposited on the surface of the second interlayer dielectric layer and in the second through hole and patterned to form source and drain electrodes connected to the first protection layer.

[0060] In an exemplary embodiment of the present disclosure, before forming the first active layer, a gate layer is formed on a surface of the substrate close to the first active layer, and the forming of the first active layer on one side of the substrate includes:

[0061] forming a gate layer on one side of the substrate and performing patterning on the gate layer;

[0062] forming a third gate insulating layer to cover the patterned gate layer;

[0063] forming the first active layer on a surface of the third gate insulating layer away from the substrate, and performing patterning on the first active layer;

[0064] An annealing process is performed on the patterned first active layer to crystallize the patterned first active layer.

[0065] In an exemplary embodiment of the present disclosure, the step of providing a first protective layer on a first edge portion of the first active layer so that the first protective layer covers at least the first edge portion, and forming a second active layer on a surface of the first middle portion includes:

[0066] forming the first protective layer covering the first active layer;

[0067] Etching the first protective layer to expose a first middle portion of the first active layer;

[0068] A second active layer is deposited on a surface of the remaining first protection layer away from the first active layer and a surface of the first middle portion, and the second active layer is patterned.

[0069] In an exemplary embodiment of the present disclosure, the step of providing a first protective layer on a first edge portion of the first active layer so that the first protective layer covers at least the first edge portion, and forming a second active layer on a surface of the first middle portion includes:

[0070] A first protection layer covering the first edge portion and a second active layer located on the surface of the first middle portion are formed by using the same material and adopting the same step, and the first protection layer and the second active layer are connected.

[0071] In an exemplary embodiment of the present disclosure, the manufacturing method further includes:

[0072] A second protection layer is formed to cover at least the second active layer and the source and drain electrodes.

[0073] A third aspect of the present disclosure provides an array substrate, comprising any one of the thin film transistors described above.

[0074] A fourth aspect of the present disclosure provides a display panel, which includes the array substrate described above.

[0075] A fifth aspect of the present disclosure provides a display device, which includes the display panel described above.

[0076] The technical solution provided by the present disclosure can achieve the following beneficial effects:

[0077] The thin-film transistor provided by the present disclosure includes a first active layer and a second active layer, and a first protective layer covers at least a first edge portion of the first active layer. Thus, the present disclosure can protect the first edge portion of the first active layer through the first protective layer. Consequently, when the present disclosure etches the second active layer located above the first active layer, the first protective layer can prevent the first edge portion of the first active layer from being etched, thereby ensuring the structural integrity of the first and second active layers and the stability of the thin-film transistor.

[0078] At the same time, since the first protective layer can prevent the first edge of the first active layer from being etched, even if the etching selectivity ratio of the material of the first active layer and the material of the second active layer is too small (that is, the etching rate of the first active layer is greater than the etching rate of the second active layer), it is possible to avoid the first edge portion of the first active layer from being inverted when etching the second active layer.

[0079] Therefore, the thin film transistor provided by the present disclosure can have good uniformity when the first active layer and the second active layer are made of materials with any etching selection ratio, and no hump phenomenon will occur, so that the thin film transistor has good stability.

[0080] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0082] Figure 1 is a schematic structural diagram of a thin film transistor according to a first embodiment of the present disclosure;

[0083] Figure 2 is a schematic structural diagram of a thin film transistor according to a second embodiment of the present disclosure;

[0084] Figure 3 is a schematic structural diagram of a thin film transistor according to a third embodiment of the present disclosure;

[0085] Figure 4 is a schematic structural diagram of a thin film transistor according to a fourth embodiment of the present disclosure;

[0086] Figure 5 1 is a flow chart of a method for manufacturing a thin film transistor according to an embodiment of the present disclosure;

[0087] Figures 6-11 1 is a schematic structural diagram of a process of manufacturing a thin film transistor according to the first embodiment of the present disclosure;

[0088] Figures 12-16 1 is a schematic structural diagram of a process of manufacturing a thin film transistor according to a second embodiment of the present disclosure;

[0089] Figures 17-21 1 is a schematic structural diagram of a process of a method for manufacturing a thin film transistor according to a third embodiment of the present disclosure;

[0090] Figures 22-25 4 is a schematic structural diagram of a process for manufacturing a thin film transistor according to the fourth embodiment of the present disclosure.

[0091] Description of reference numerals:

[0092] 1. Substrate; 2. First active layer; 3. Second active layer; 4. First protective layer; 5. Second protective layer; 6. Third protective layer; 7. Fourth protective layer; 8. Fifth protective layer; 9. First gate insulating layer; 10. Second gate insulating layer; 11. Third gate insulating layer; 12. Gate layer; 13. First interlayer dielectric layer; 14. Second interlayer dielectric layer; 15. Source and drain; 16. First buffer layer; 17. Second buffer layer; 18. First through hole; 19. Second through hole; 21. First middle portion; 22. First edge portion; 31. Second middle portion; 32. Second edge portion; 33. Third middle portion; 34. Third edge portion. DETAILED DESCRIPTION

[0093] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0094] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0095] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0096] In the related art, a stacked channel thin film transistor (ie, a thin film transistor having two superimposed active layers) only covers the first active layer with the second active layer, and the first active layer and the second active layer are patterned and etched simultaneously.

[0097] However, the inventors of the present disclosure have discovered that when the structure of a thin film transistor of the prior art is adopted, and when the etching rate of the material used in the lower active layer is much greater than that of the upper active layer, a reverse cut structure will appear in the lower active layer after etching. The surface damage of the reverse cut structure will be very serious, resulting in a high concentration of oxygen vacancies in the reverse cut structure, and in the subsequent manufacturing process, it will make it difficult to replenish the oxygen lost in the reverse cut structure. As a result, the reverse cut structure will eventually lead to poor uniformity of the thin film transistor and the appearance of a hump phenomenon, which in turn leads to poor stability of the thin film transistor. In other words, the structure of the existing thin film transistor cannot make the thin film transistor have good stability when selecting materials with arbitrary etching selectivity ratios in the first active layer and the second active layer.

[0098] Therefore, the inventor of the present disclosure, after careful consideration and extensive creative effort, addressed the technical issues identified above and ultimately invented a new thin-film transistor. This thin-film transistor can achieve good uniformity and avoid humping when fabricated with materials having any etching selectivity ratio for both active layers, thereby ensuring good stability regardless of the materials used for both active layers.

[0099] It should be noted that, since the materials of the two active layers of the stacked channel thin film transistor are different, when the two active layers provided by the present disclosure can be made of any materials, it is necessary to ensure that the materials of the two active layers are different.

[0100] The first aspect of the present disclosure provides a thin film transistor, such as Figures 1 to 4 As shown, the thin film transistor may include: a substrate 1 , a first active layer 2 , a second active layer 3 , a first protective layer 4 , a source and drain electrode 15 , and a gate layer 12 .

[0101] Specifically, the material of the substrate 1 can be glass, but is not limited thereto. The substrate 1 can also have other materials, such as: one of polyolefin, polyetherketone, polyimide, polyethylene terephthalate, polyacrylate, silicone, polyethylene, glass resin, polycarbonate, fluoropolymer, or copolymers, mixtures, laminates, etc. of the above materials, all of which are within the scope of protection of the present disclosure and can be selected according to actual needs.

[0102] The first active layer 2 may be located on one side of the substrate 1, and may have a first middle portion 21 and a first edge portion 22. The first middle portion 21 is located between the first edge portions 22. The second active layer 3 may be located at least on the surface of the first middle portion 21, and the material of the second active layer 3 may be different from that of the first active layer 2. The first protective layer 4 may cover at least the first edge portion 22 of the first active layer 2. The source and drain electrodes 15 may be located on the side of the second active layer 3 away from the substrate 1, and the source and drain electrodes 15 may be connected to the second active layer 3. The gate layer 12 may be located on the side of the second active layer 3 away from the substrate 1, or on the surface of the substrate 1 close to the first active layer 2.

[0103] Since the first protective layer 4 of the present disclosure can at least cover the first edge portion 22 of the first active layer 2, the present disclosure can protect the first edge portion 22 of the first active layer 2 through the first protective layer 4. Therefore, when the present disclosure etches the second active layer 3 located on the first active layer 2, the first protective layer 4 can prevent the first edge portion 22 of the first active layer 2 from being etched, thereby ensuring the structural integrity of the first active layer 2 and the second active layer 3 and the stability of the thin film transistor.

[0104] At the same time, since the first protective layer 4 can prevent the first edge portion 22 of the first active layer 2 from being etched, even if the etching selectivity of the material of the first active layer 2 and the material of the second active layer 3 is too small (that is, the etching rate of the first active layer 2 is greater than the etching rate of the second active layer), it is possible to avoid the first edge portion 22 of the first active layer 2 from having a reverse cut structure when etching the second active layer 3.

[0105] Therefore, the thin film transistor provided by the present disclosure can have good uniformity when the first active layer 2 and the second active layer 3 are made of materials with any etching selection ratio, and no hump phenomenon will occur, so that the thin film transistor has good stability.

[0106] In the first embodiment of the present disclosure, Figure 1 and Figures 6-11 As shown, the second active layer 3 may have a second middle portion 31 and a second edge portion 32. The second middle portion 31 may be located on the surface of the first middle portion 21. It is understood that the second middle portion 31 may be the same size as the first middle portion 21, so that the second middle portion 31 completely covers the first middle portion 21. However, it is not limited thereto. The second middle portion 31 may also be smaller than the first middle portion 21, which is within the scope of protection of the present disclosure. When the size of the second middle portion 31 is smaller than the size of the first middle portion 21, the first protective layer 4 may also cover part of the first middle portion 21, so that the first protective layer 4 is in contact with the second active layer 3, thereby preventing the first active layer 2 from being affected when the second active layer 3 is etched, thereby preventing damage to the performance of the thin film transistor.

[0107] In addition, the second edge portion 32 of the second active layer 3 may be located on a surface of the first protection layer 4 away from the first edge portion 22 and a portion of the surface of the second middle portion 31 for connecting to the source and drain electrodes 15 .

[0108] In this embodiment, the thickness of the second middle portion 31 is the same as the thickness of the second edge portion 32, so that the second active layer 3 has good performance. Therefore, since the thickness of the second middle portion 31 is the same as the thickness of the second edge portion 32, the shape of the second active layer 3 is stepped.

[0109] In this embodiment, since the second edge portion 32 is located on the surface of the first protective layer 4 away from the first edge portion 22, it is necessary to form the first protective layer 4 before forming the second active layer 3. In other words, in this embodiment, it is necessary to first form the first protective layer 4 covering the first active layer 2, then etch the first protective layer 4 to expose the surface of the first middle portion 21 of the first active layer 2, and then form the second active layer 3 on the surface of the first middle portion 21 and the surface of the first protective layer 4 away from the first edge portion 22.

[0110] The first protective layer 4 can be etched using dry etching, but is not limited thereto. Wet etching can also be used. The inventors of the present disclosure have discovered that when the present disclosure uses dry etching to etch the first protective layer 4, the plasma emitted during the dry etching process can damage the first active layer 2, thereby causing the first active layer 2 to become conductive, ultimately causing the thin film transistor to lose its switching characteristics.

[0111] Therefore, after careful consideration, the inventors of this disclosure discovered that crystalline oxide can be used as the material for the first active layer 2. After crystallization, crystalline oxide is less susceptible to the plasma emitted during dry etching, thereby ensuring the switching characteristics of the thin film transistor. Furthermore, after crystallization, crystalline oxide can reduce carrier scattering, thereby significantly improving the mobility of the thin film transistor.

[0112] In this embodiment, the crystalline oxide may be indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium zinc praseodymium oxide (IZYO), etc., and may be selected according to actual needs.

[0113] Furthermore, an annealing process can be used to crystallize the crystalline oxide. Different crystalline oxides require different annealing temperatures, which are usually above 350° C. The annealing time for the crystalline oxide is usually about 1 hour.

[0114] However, the inventors discovered that by changing the ratio of indium, gallium, and zinc in the IGZO material to 1:3:6, the IGZO can be crystallized at room temperature. When the present disclosure uses the IGZO material with this ratio, the annealing step can be omitted, thereby reducing the number of steps in the thin-film transistor manufacturing process and significantly saving manufacturing time.

[0115] In this embodiment, the thin film transistor may further include: a first gate insulating layer 9. The first gate insulating layer 9 may at least cover the second active layer 3, and the gate layer 12 may be located on the surface of the first gate insulating layer 9 away from the first active layer 2. By providing the first gate insulating layer 9, the gate layer 12 can be insulated from the second source layer, and can also be flattened to facilitate the provision of the gate layer 12. The material of the first gate insulating layer 9 may be silicon nitride, but is not limited thereto. The first gate insulating layer 9 may also use other materials with insulating properties, which are all within the scope of protection of the present disclosure and can be selected according to actual needs. In addition, the projection of the gate layer 12 on the substrate 1 may be located within the projection of the second middle portion 31 on the substrate 1.

[0116] In this embodiment, the thin film transistor may further include a first interlayer dielectric layer 13. The first interlayer dielectric layer 13 may be located on a surface of the first gate insulating layer 9 away from the second active layer 3 and cover the gate layer 12. The first interlayer dielectric layer 13 can isolate the gate layer 12 from the source and drain electrodes 15, preventing the gate layer 12 and the source and drain electrodes 15 from interfering with each other.

[0117] In addition, the source and drain electrodes 15 may be located on a surface of the first interlayer dielectric layer 13 away from the second active layer 3. In order to connect the source and drain electrodes 15 to the second active layer 3, first through holes 18 may be provided on the first interlayer dielectric layer 13 and the first gate insulating layer 9, and the source and drain electrodes 15 may be connected to the second active layer 3 through the first through holes 18.

[0118] Furthermore, in order to further isolate the source and drain electrodes 15 from the gate layer 12, the source and drain electrodes 15 can be connected to the second edge portion 32. That is, it can be understood that the projection of the first through hole 18 on the substrate 1 can be located within the projection of the second edge portion 32 on the substrate 1, so that the source and drain electrodes 15 can be connected to the second insulating portion through the first through hole 18.

[0119] In this embodiment, the thin film transistor may further include: a first buffer layer 16 and a third protective layer 6. The first buffer layer 16 may be located on the surface of the substrate 1, and the first active layer 2 may be located on the surface of the first buffer layer 16 away from the substrate 1. Furthermore, the projection of the first active layer 2 on the substrate 1 may be located within the projection of the first buffer layer 16 on the substrate 1. Furthermore, the first protective layer 4 may also cover areas of the first buffer layer 16 where the first active layer 2 is not provided.

[0120] The third protective layer 6 can cover the first interlayer dielectric layer 13 and the source and drain electrodes 15 to protect the source and drain electrodes 15 and prevent damage to the source and drain electrodes 15. The material of the third protective layer 6 can be silicon nitride, but is not limited thereto. The third protective layer 6 can also be other insulating materials, which are all within the scope of protection of the present disclosure and can be selected according to actual needs.

[0121] In the second embodiment of the present disclosure, Figure 2 and Figures 12-16 As shown, the first protective layer 4 and the second active layer 3 can be made of the same material, and the first protective layer 4 and the second active layer 3 can be connected to each other. The first protective layer 4 and the second active layer 3 can be formed simultaneously in the same step through a single process. Thus, the present disclosure can protect the first active layer 2 by forming the first protective layer 4 and the second active layer 3 simultaneously through a single process. For example, the material of the first protective layer 4 and the second active layer 3 can be any one of IGZO, IGTO and IZYO, but is not limited thereto. The first protective layer 4 and the second active layer 3 can also use other oxide semiconductor materials, as long as they are different from the material of the first active layer 2, which is within the scope of protection of the present disclosure.

[0122] Furthermore, in this embodiment, in order to ensure the protective effect of the first protective layer 4 on the first active layer 2, it is necessary to ensure that a first distance exists between the edge of the first protective layer 4 away from the first edge portion 22 and the first edge portion 22. It should be noted that the first distance exists between the edge of the first protective layer 4 away from the first edge portion 22 and the first edge portion 22 mentioned here can be understood as: the first protective layer 4 can extend the length of the first distance relative to the edge of the first edge portion 22. The first distance can be between 0.4μm and 1.2μm, for example, 0.4μm, 0.5μm, 0.8μm, 1μm, 1.2μm, etc. However, this is not limited to this, and the first distance can also be set according to actual needs. For example, the first distance can also be greater than 1.2μm or less than 0.4μm.

[0123] In this embodiment, the thin film transistor provided by the present disclosure may further include a second gate insulating layer 10 , which may cover the first protection layer 4 and the second active layer 3 , and the gate layer 12 may be located on the surface of the second gate insulating layer 10 .

[0124] The second gate insulating layer 10 can be provided to insulate the gate layer 12 from the second source layer and the first protective layer 4, and can also achieve flattening, facilitating the installation of the gate layer 12. The material of the second gate insulating layer 10 can be silicon nitride, but is not limited thereto. The second gate insulating layer 10 can also be made of other materials with insulating properties, all of which are within the scope of the present disclosure and can be selected according to actual needs. In addition, the projection of the gate layer 12 on the substrate 1 can be located within the projection of the second intermediate portion 31 on the substrate 1.

[0125] Since the first protective layer 4 and the second active layer 3 are formed simultaneously in a single process in the present disclosure, the first active layer 2 can be protected. Therefore, the second gate insulating layer 10 cannot come into contact with the first active layer 2. Furthermore, when etching the second gate insulating layer 10, the protection of the first protective layer 4 and the second active layer 3 can prevent the plasma from damaging the first active layer 2. Therefore, since the plasma will not damage the first active layer 2, in this embodiment, the material of the first active layer 2 can be either a crystalline oxide or an amorphous oxide. Therefore, the structure adopted in this embodiment has a higher degree of freedom in material selection and a simpler process than the structure adopted in the first embodiment.

[0126] In this embodiment, the thin film transistor may further include a second interlayer dielectric layer 14. The second interlayer dielectric layer 14 may be located on a surface of the second gate insulating layer 10 away from the second active layer 3 and cover the gate layer 12. The second interlayer dielectric layer 14 can isolate the gate layer 12 from the source and drain electrodes 15, preventing the gate layer 12 and the source and drain electrodes 15 from interfering with each other.

[0127] In addition, the source and drain electrodes 15 may be located on a surface of the second interlayer dielectric layer 14 away from the second active layer 3. In order to connect the source and drain electrodes 15 to the second active layer 3, second through holes 19 may be provided on the second interlayer dielectric layer 14 and the second gate insulating layer 10, and the source and drain electrodes 15 may be connected to the second active layer 3 through the second through holes 19.

[0128] Furthermore, in order to further isolate the source and drain electrodes 15 from the gate layer 12, the source and drain electrodes 15 can be connected to the first protective layer 4 through second through holes 19. Since the material of the first protective layer 4 is the same as that of the second active layer 3 and they are connected to each other, the second through holes 19 can be connected to the second active layer 3 through the first protective layer 4. In other words, it can be understood that the projection of the second through hole 19 on the substrate 1 can be located within the projection of the first protective layer 4 on the substrate 1, so that the source and drain electrodes 15 can be connected to the first protective layer 4 through the second through hole 19.

[0129] In this embodiment, the thin film transistor may further include: a second buffer layer 17 and a fourth protective layer 7. The second buffer layer 17 may be located on the surface of the substrate 1, the first active layer 2 may be located on the surface of the second buffer layer 17 away from the substrate 1, and the projection of the first active layer 2 on the substrate 1 may be located within the projection of the second buffer layer 17 on the substrate 1. Furthermore, the first protective layer 4 may also cover areas of the second buffer layer 17 where the first active layer 2 is not provided, and the second gate insulating layer 10 may also cover areas of the second buffer layer 17 where the first active layer 2 and the first protective layer 4 are not provided.

[0130] The fourth protective layer 7 can cover the second interlayer dielectric layer 14 and the source and drain electrodes 15 to protect the source and drain electrodes 15 and prevent damage to the source and drain electrodes 15. The material of the fourth protective layer 7 can be silicon nitride, but is not limited thereto. The fourth protective layer 7 can also be other insulating materials, which are all within the scope of protection of the present disclosure and can be selected according to actual needs.

[0131] As can be seen from the above, in this embodiment, since the second active layer 3 and the first protective layer 4 are formed simultaneously in a single process, the thin film transistor provided by this embodiment can save one etching step during the fabrication process compared to the first embodiment. Furthermore, since the material of the first active layer 2 in this embodiment can be either a crystalline oxide or an amorphous oxide, the structure adopted in this embodiment has greater freedom in material selection and a simpler process than the structure adopted in the first embodiment.

[0132] In the third embodiment of the present disclosure, Figure 3 and Figures 17-21 As shown, the gate layer 12 can be located on the surface of the substrate 1 close to the first active layer 2. The thin film transistor can also include a third gate insulating layer 11, which can cover the gate, and the first active layer 2 can be located on the surface of the third gate insulating layer 11 away from the substrate 1. At the same time, the first protective layer 4 can also cover the area on the third gate insulating layer 11 where the first active layer 2 is not provided.

[0133] In this embodiment, the second active layer 3 may have a third middle portion 33 and a third edge portion 34. The second active layer 3 in this embodiment is identical to the second active layer 3 in the previous embodiment, namely, the second middle portion 31 and the third middle portion 33 are identical, and the second edge portion 32 and the third edge portion 34 are identical. The third middle portion 33 may be located on the surface of the first middle portion 21. It is understood that the third middle portion 33 may be the same size as the first middle portion 21, so that the third middle portion 33 completely covers the first middle portion 21. However, this is not limiting. The third middle portion 33 may also be smaller than the first middle portion 21, and this is within the scope of protection of the present disclosure. When the third middle portion 33 is smaller than the first middle portion 21, the first protective layer 4 may also partially cover the first middle portion 21, so that the first protective layer 4 is connected to the second active layer 3. This prevents etching of the second active layer 3 from affecting the first active layer 2 and damaging the performance of the thin film transistor.

[0134] In addition, the third edge portion 34 of the second active layer 3 may be located on a surface of the first protection layer 4 away from the first edge portion 22 and a portion of the surface of the third middle portion 33 for connecting to the source and drain electrodes 15 .

[0135] In this embodiment, the thickness of the third middle portion 33 is the same as the thickness of the third edge portion 34, so that the second active layer 3 has good performance. Therefore, since the thickness of the second middle portion 31 is the same as the thickness of the second edge portion 32, the shape of the second active layer 3 in this embodiment is stepped.

[0136] In this embodiment, because the third edge portion 34 is located on the surface of the first protective layer 4 away from the first edge portion 22, it is necessary to form the first protective layer 4 before forming the second active layer 3. In other words, in this embodiment, it is necessary to first form the first protective layer 4 covering the first active layer 2, then etch the first protective layer 4 to expose the surface of the first middle portion 21 of the first active layer 2, and then form the second active layer 3 on the surface of the first middle portion 21 and the surface of the first protective layer 4 away from the first edge portion 22.

[0137] In this embodiment, the first protective layer 4 can be etched by dry etching, but is not limited thereto. Wet etching can also be used. When the present disclosure uses dry etching to etch the first protective layer 4, a crystalline oxide can be used as the material of the first active layer 2. After crystallization, the crystalline oxide is less susceptible to the plasma emitted during dry etching, thereby ensuring the switching characteristics of the thin film transistor. At the same time, after crystallization, the crystalline oxide can reduce carrier scattering, thereby significantly improving the mobility of the thin film transistor.

[0138] Furthermore, an annealing process can be used to crystallize the crystalline oxide. Different crystalline oxides require different annealing temperatures, which are usually above 350° C. The annealing time for the crystalline oxide is usually about 1 hour.

[0139] However, by changing the ratio of indium, gallium, and zinc in the IGZO material to adjust the ratio to 1:3:6, IGZO can be crystallized at room temperature. When the present disclosure uses the IGZO material with this ratio, the annealing step can be omitted, thereby reducing the number of steps in the production of the thin-film transistor and significantly saving the production time.

[0140] In this embodiment, the source and drain electrodes 15 can be located at least on the surface of the third edge portion 34, thereby directly connecting the source and drain electrodes 15 to the third edge portion 34. Therefore, compared with the first and second embodiments, this embodiment does not require an interlayer dielectric layer, nor does it require a through hole connecting the source and drain electrodes 15 and the third edge portion 34. Therefore, compared with the first and second embodiments, this embodiment has a simpler process flow.

[0141] In this embodiment, the thin film transistor may further include a second protective layer 5. The second protective layer 5 may cover at least the second active layer 3 and the source / drain electrode 15 to protect the second active layer 3 and the source / drain electrode 15 from damage. The material of the second protective layer 5 may be silicon nitride, but is not limited thereto. The second protective layer 5 may also be other insulating materials, all of which are within the scope of the present disclosure and may be selected according to actual needs.

[0142] Furthermore, the thin film transistor may further include a fifth protective layer 8, which may be located on the surface of the second protective layer 5 away from the second active layer 3. By providing the fifth protective layer 8, the second protective layer 5 can be supplemented, thereby further ensuring that the second active layer 3 and the source and drain electrodes 15 are not damaged.

[0143] In the fourth embodiment of the present disclosure, Figure 4 and Figures 22-25 As shown, the gate layer 12 can be located on the surface of the substrate 1 close to the first active layer 2. The thin film transistor can also include a third gate insulating layer 11, which can cover the gate, and the first active layer 2 can be located on the surface of the third gate insulating layer 11 away from the substrate 1. At the same time, the first protective layer 4 can also cover the area on the third gate insulating layer 11 where the first active layer 2 is not provided.

[0144] The first protective layer 4 and the second active layer 3 may be made of the same material, and the first protective layer 4 and the second active layer 3 may be connected to each other. The first protective layer 4 and the second active layer 3 may be formed simultaneously through a single process. Thus, the present disclosure can protect the first active layer 2 by forming the first protective layer 4 and the second active layer 3 simultaneously through a single process. For example, the material of the first protective layer 4 and the second active layer 3 may be any one of IGZO, IGTO and IZYO, but is not limited thereto. The first protective layer 4 and the second active layer 3 may also use other oxide semiconductor materials, as long as they are different from the material of the first active layer 2, which is within the scope of protection of the present disclosure.

[0145] Furthermore, in this embodiment, in order to ensure the protective effect of the first protective layer 4 on the first active layer 2, it is necessary to ensure that a first distance exists between the edge of the first protective layer 4 away from the first edge portion 22 and the first edge portion 22. It should be noted that the first distance exists between the edge of the first protective layer 4 away from the first edge portion 22 and the first edge portion 22 mentioned here can be understood as: the first protective layer 4 can extend the length of the first distance relative to the edge of the first edge portion 22. The first distance can be between 0.4μm and 1.2μm, for example, 0.4μm, 0.5μm, 0.8μm, 1μm, 1.2μm, etc. However, this is not limited to this, and the first distance can also be set according to actual needs. For example, the first distance can also be greater than 1.2μm or less than 0.4μm.

[0146] In this embodiment, the source and drain electrodes 15 can be located at least on the surface of the first protective layer 4, thereby directly connecting the source and drain electrodes 15 to the first protective layer 4 and the second active layer 3. Therefore, compared with the first and second embodiments, this embodiment does not require an interlayer dielectric layer, nor does it require a through hole connecting the source and drain electrodes 15 and the third edge portion 34. Therefore, the process flow of this embodiment is simpler than that of the first and second embodiments. Moreover, since the second active layer 3 and the first protective layer 4 of this embodiment are formed simultaneously through a single process, the thin film transistor provided by this embodiment can save one etching step during the manufacturing process compared to the third embodiment. At the same time, in this embodiment, the material of the first active layer 2 can be a crystalline oxide or an amorphous oxide. Therefore, the structure adopted in this embodiment has a higher degree of freedom in material selection and a simpler process than the structure adopted in the third embodiment.

[0147] In this embodiment, the thin film transistor may further include a second protective layer 5. The second protective layer 5 may cover at least the second active layer 3 and the source / drain electrode 15 to protect the second active layer 3 and the source / drain electrode 15 from damage. The material of the second protective layer 5 may be silicon nitride, but is not limited thereto. The second protective layer 5 may also be other insulating materials, all of which are within the scope of the present disclosure and may be selected according to actual needs.

[0148] Furthermore, the thin film transistor may further include a fifth protective layer 8, which may be located on the surface of the second protective layer 5 away from the second active layer 3. By providing the fifth protective layer 8, the second protective layer 5 can be supplemented, thereby further ensuring that the second active layer 3 and the source and drain electrodes 15 are not damaged.

[0149] A second aspect of the present disclosure provides a method for fabricating a thin-film transistor. The thin-film transistor fabricated using this method can exhibit good uniformity and avoid humping when using materials with any etching selectivity ratio for both active layers. This ensures that the thin-film transistor exhibits good stability regardless of the materials used for both active layers. Furthermore, this method can be used to fabricate the thin-film transistor described above. Therefore, for the specific thin-film transistor structure, reference can be made to the above explanation of thin-film transistors.

[0150] like Figure 5 As shown, the method for manufacturing the thin film transistor may include:

[0151] Step S10, providing a substrate 1;

[0152] Step S20: forming a first active layer 2 on one side of the substrate 1, wherein the first active layer 2 has a first middle portion 21 and a first edge portion 22, and the first middle portion 21 may be located between the first edge portions 22;

[0153] Step S30: disposing a first protective layer 4 on the first edge portion 22 of the first active layer 2 so that the first protective layer 4 at least covers the first edge portion 22, and forming a second active layer 3 on the surface of the first middle portion 21;

[0154] Step S40: After forming the first protection layer 4, forming a gate layer 12 on the side of the second active layer 3 away from the substrate 1, or before forming the first active layer 2, forming a gate layer 12 on the surface of the substrate 1 close to the first active layer 2;

[0155] Step S50 , forming source and drain electrodes 15 on a side of the second active layer 3 away from the substrate 1 , and connecting the source and drain electrodes 15 to the second active layer 3 .

[0156] Among them, the first active layer 2 and the second active layer 3 are made of different materials.

[0157] The above steps are described in detail below. Specifically:

[0158] In step S10, a substrate 1 can be provided. The material of the substrate 1 can be glass, but is not limited thereto. The substrate 1 can also have other materials, for example: one of polyolefin, polyetherketone, polyimide, polyethylene terephthalate, polyacrylate, silicone, polyethylene, glass resin, polycarbonate, fluoropolymer, or copolymers, mixtures, laminates, etc. of the above materials, all of which are within the scope of protection of the present disclosure and can be selected according to actual needs.

[0159] In the first embodiment of the present disclosure, Figures 6-11As shown, after forming the first protective layer 4, a gate layer 12 is formed on the side of the second active layer 3 away from the substrate 1. In step S20, a first active layer 2 can be deposited on one side of the substrate 1 and patterned. The patterned first active layer 2 is then annealed to crystallize the patterned first active layer 2.

[0160] In this embodiment, the material of the first active layer 2 can be a crystalline oxide, such as IGZO, IGTO, and IZYO, which can be selected according to actual needs. When the patterned first active layer 2 is annealed, the annealing temperature can be greater than or equal to 350° C., and the annealing time can range from 0.5 hours to 1.5 hours, but is not limited thereto.

[0161] However, by changing the ratio of indium, gallium, and zinc in the IGZO material to adjust the ratio to 1:3:6, IGZO can be crystallized at room temperature. When the present disclosure uses the IGZO material with this ratio, the annealing step can be omitted, thereby reducing the number of steps in the production of the thin-film transistor and significantly saving the production time.

[0162] In this embodiment, step S30 may include forming a first protective layer 4 covering the first active layer 2, and etching the first protective layer 4 to expose the first middle portion 21 of the first active layer 2. Specifically, the first protective layer 4 may be etched using a dry etching method. Because the material of the first active layer 2 is a crystalline oxide, the crystallized first active layer 2 can prevent the first active layer 2 from being affected by plasma emitted during the dry etching of the first protective layer 4. At the same time, the crystallized first active layer 2 can reduce carrier scattering, thereby improving the mobility of the thin film transistor.

[0163] Next, a second active layer 3 may be deposited on the surface of the remaining first protection layer 4 away from the first active layer 2 and the surface of the first middle portion 21 , and the second active layer 3 may be patterned so as to have a stepped shape.

[0164] The second active layer 3 may have a second middle portion 31 and a second edge portion 32. The second edge portion 32 may be located on a surface of the first protective layer 4 away from the first edge portion 22 and a portion of the surface of the second middle portion 31. Through patterning, the thickness of the second edge portion 32 may be made the same as that of the second middle portion 31, thereby enabling the second active layer 3 to have better performance.

[0165] In this embodiment, step S40 may include: forming a first gate insulating layer 9 that at least covers the second active layer 3. Forming a gate layer 12 on a side of the first gate insulating layer 9 away from the second active layer 3, and patterning the gate layer 12 so that a projection of the gate layer 12 on the substrate 1 is located within a projection of the second middle portion 31 on the substrate 1.

[0166] Furthermore, the gate layer 12 can be used as a mask to dope the second active layer 3 to make the second active layer 3 conductive. Specifically, the gate layer 12 can be used as a mask to dope the second active layer 3 with materials such as boron and phosphorus through a doping process to make the second active layer 3 conductive.

[0167] Furthermore, in step S50, a first interlayer dielectric layer 13 can be formed on a surface of the first gate insulating layer 9 away from the second active layer 3, and the first interlayer dielectric layer 13 covers the gate layer 12. The first gate insulating layer and the first gate insulating layer 9 are etched to form a first through hole 18 and expose the surface of the second edge portion 32. A material for forming the source and drain electrodes 15 is deposited on the surface of the first interlayer dielectric layer 13 and in the first through hole 18 and patterned to form the source and drain electrodes 15 connected to the second edge portion 32.

[0168] In this embodiment, the thin film transistor may further include: a first buffer layer 16 and a third protective layer 6. The method for manufacturing the thin film transistor may further include:

[0169] Between steps S10 and S20, a first buffer layer 16 may be formed on the surface of the substrate 1. The first active layer 2 and the first protective layer 4 may be formed on the surface of the first buffer layer 16 away from the substrate 1, and the projection of the first active layer 2 on the substrate 1 may be located within the projection of the first buffer layer 16 on the substrate 1.

[0170] After step S50, a third protective layer 6 may be formed to cover the first interlayer dielectric layer 13 and the source and drain electrodes 15 to protect the source and drain electrodes 15 from damage. The material of the third protective layer 6 may be silicon nitride, but is not limited thereto. The third protective layer 6 may also be other insulating materials, all of which are within the scope of the present disclosure and may be selected according to actual needs.

[0171] Through the manufacturing method of the thin film transistor, the first active layer 2 and the second active layer 3 can be patterned separately, and the first edge portion 22 can be protected by forming a first protective layer 4. Therefore, when the material etching selectivity of the first active layer 2 and the second active layer 3 is too small, the first active layer 2 will not be undercut, thereby effectively solving the problems of poor uniformity and hump phenomenon of the thin film transistor.

[0172] In the second embodiment of the present disclosure, Figures 12-16 As shown, after forming the first protective layer 4, a gate layer 12 is formed on the side of the second active layer 3 away from the substrate 1. In step S20, a first active layer 2 can be formed on one side of the substrate 1 and patterned. The material of the first active layer 2 can be a crystalline oxide or an amorphous oxide. Therefore, compared with the previous embodiment, this embodiment has a wider range of material choices for the first active layer 2 and greater process freedom.

[0173] In step S30 of this embodiment, the first protective layer 4 covering the first edge portion 22 and the second active layer 3 located on the surface of the first middle portion 21 can be formed using the same material and in the same steps, and the first protective layer 4 and the second active layer 3 are connected. Specifically, the material for forming the first protective layer 4 and the second active layer 3 can be deposited on the surface of the first active layer 2, and the material of the first protective layer 4 and the second active layer 3 can be etched to form the first protective layer 4 and the second active layer 3.

[0174] Therefore, in this embodiment, the etching of the first protective layer 4 and the second active layer 3 can be completed in one etching step. Therefore, compared with the first embodiment, this embodiment can reduce one etching step, thereby simplifying the manufacturing process of the thin film transistor and shortening the manufacturing time of the thin film transistor.

[0175] In step S40 of this embodiment, a second gate insulating layer 10 can be formed to cover the first protective layer 4 and the active layer. A gate layer 12 is formed on the surface of the second gate insulating layer 10 and patterned so that the projection of the gate layer 12 on the substrate 1 is located within the projection of the second active layer 3 on the substrate 1. The material of the second gate insulating layer 10 can be silicon nitride, but is not limited thereto. Other materials can also be used, all of which are within the scope of protection of this disclosure.

[0176] Furthermore, in this step, the gate layer 12 can be used as a mask to dope the second active layer 3 and the first protective layer 4, so as to make the second active layer 3 and the first protective layer 4 conductive. Specifically, the gate layer 12 can be used as a mask to dope the second active layer 3 and the first protective layer 4 with materials such as boron and phosphorus through a doping process, so as to make the second active layer 3 and the first protective layer 4 conductive.

[0177] Furthermore, in step S50 of this embodiment, a second interlayer dielectric layer 14 may be formed on a surface of the second gate insulating layer 10 away from the second active layer 3, and the second interlayer dielectric layer 14 may cover the gate layer 12. The second interlayer dielectric layer 14 and the second gate insulating layer 10 are etched to form a second through hole 19 and expose the surface of the first protective layer 4. A material for forming the source and drain electrodes 15 may be deposited on the surface of the second interlayer dielectric layer 14 and in the second through hole 19, and patterned to form the source and drain electrodes 15 connected to the first protective layer 4.

[0178] In addition, in this embodiment, the thin film transistor may further include: a second buffer layer 17 and a fourth protective layer 7. The method for manufacturing the thin film transistor may further include:

[0179] Between steps S10 and S20, a second buffer layer 17 may be formed on the surface of the substrate 1. The first active layer 2 and the first protective layer 4 may be formed on the surface of the second buffer layer 17 away from the substrate 1, and the projection of the first active layer 2 on the substrate 1 may be located within the projection of the second buffer layer 17 on the substrate 1.

[0180] After step S50, a fourth protective layer 7 may be formed covering the second interlayer dielectric layer 14 and the source / drain electrodes 15 to protect the source / drain electrodes 15 from damage. The material of the fourth protective layer 7 may be silicon nitride, but is not limited thereto. The fourth protective layer 7 may also be other insulating materials, all of which are within the scope of the present disclosure and may be selected according to actual needs.

[0181] In the third embodiment of the present disclosure, Figures 17-21 As shown, before forming the first active layer 2, a gate layer 12 is formed on the surface of the substrate 1 close to the first active layer 2. In this embodiment, step S20 and step S40 may include:

[0182] A gate layer 12 is formed on one side of the substrate 1 and patterned. A third gate insulating layer 11 may be formed to cover the patterned gate layer 12. A first active layer 2 may be formed on a surface of the third gate insulating layer 11 away from the substrate 1 and patterned. After the patterning of the first active layer 2, the patterned first active layer 2 may be annealed to crystallize the patterned first active layer 2.

[0183] In this embodiment, the material of the first active layer 2 can be a crystalline oxide, such as IGZO, IGTO, and IZYO, which can be selected according to actual needs. When the patterned first active layer 2 is annealed, the annealing temperature can be greater than or equal to 350° C., and the annealing time can range from 0.5 hours to 1.5 hours, but is not limited thereto.

[0184] However, by changing the ratio of indium, gallium, and zinc in the IGZO material to adjust the ratio to 1:3:6, IGZO can be crystallized at room temperature. When the present disclosure uses the IGZO material with this ratio, the annealing step can be omitted, thereby reducing the number of steps in the production of the thin-film transistor and significantly saving the production time.

[0185] Furthermore, in step S30 of this embodiment, a first protective layer 4 can be formed covering the first active layer 2, and the first protective layer 4 can be etched to expose the first middle portion 21 of the first active layer 2. Specifically, the first protective layer 4 can be etched using a dry etching method. Because the material of the first active layer 2 is a crystalline oxide, the crystallized first active layer 2 can prevent the first active layer 2 from being affected by the plasma emitted during the dry etching of the first protective layer 4. At the same time, the crystallized first active layer 2 can reduce carrier scattering, thereby improving the mobility of the thin film transistor.

[0186] Step S30 may further include: depositing a second active layer 3 on a surface of the remaining first protective layer 4 away from the first active layer 2 and a surface of the first middle portion 21 , and patterning the second active layer 3 so that the second active layer 3 has a stepped shape.

[0187] The second active layer 3 may have a third middle portion 33 and a third edge portion 34. The third edge portion 34 may be located on a surface of the first protective layer 4 away from the first edge portion 22 and a portion of the surface of the second middle portion 31. Through patterning, the thickness of the third edge portion 34 may be made the same as that of the third middle portion 33, thereby enabling the second active layer 3 to have better performance.

[0188] In step S50, the material for forming the source and drain electrodes 15 can be deposited directly on the surface of the third edge portion 34 and then etched to form the source and drain electrodes 15 directly on the surface of the third edge portion 34, thereby directly connecting the third edge portion 34 to the source and drain electrodes 15. Therefore, compared to the first and second embodiments, this embodiment does not require an interlayer dielectric layer or vias connecting the second active layer 3 and the source and drain electrodes 15. Therefore, compared to the first and second embodiments, this embodiment has a simpler process flow.

[0189] Furthermore, in this embodiment, the thin film transistor may further include a second protective layer 5 and a fifth protective layer 8, and the method for manufacturing the thin film transistor may further include:

[0190] The second protection layer 5 is formed to cover the second active layer 3 and the source / drain electrodes 15 , so as to protect the second active layer 3 and the source / drain electrodes 15 from being damaged.

[0191] Furthermore, a fifth protection layer 8 covering the second protection layer 5 may be formed to further protect the second active layer 3 and the source and drain electrodes 15 through the fifth protection layer 8 .

[0192] In the fourth embodiment of the present disclosure, Figures 22-25 As shown, before forming the first active layer 2, a gate layer 12 is formed on the surface of the substrate 1 close to the first active layer 2. In this embodiment, step S20 and step S40 may include:

[0193] A gate layer 12 is formed on one side of the substrate 1 and patterned. A third gate insulating layer 11 may be formed to cover the patterned gate layer 12. A first active layer 2 may be formed on a surface of the third gate insulating layer 11 away from the substrate 1 and patterned.

[0194] In step S30, the first protective layer 4 covering the first edge portion 22 and the second active layer 3 located on the surface of the first middle portion 21 can be formed using the same material and in the same steps, and the first protective layer 4 and the second active layer 3 are connected. Specifically, the material for forming the first protective layer 4 and the second active layer 3 can be deposited on the surface of the first active layer 2, and the material of the first protective layer 4 and the second active layer 3 can be etched to form the first protective layer 4 and the second active layer 3.

[0195] Therefore, in this embodiment, the etching of the first protective layer 4 and the second active layer 3 can be completed in one etching step. Therefore, compared with the third embodiment, this embodiment can reduce one etching step, thereby simplifying the manufacturing process of the thin film transistor and shortening the manufacturing time of the thin film transistor.

[0196] Furthermore, in step S50, the material for forming the source and drain electrodes 15 can be deposited directly on the surface of the first protective layer 4 and etched to form the source and drain electrodes 15 directly on the surface of the first protective layer 4, thereby directly connecting the first protective layer 4 and the source and drain electrodes 15. Since the first protective layer 4 and the second active layer 3 are formed through the same step and are made of the same material and are connected to each other, the source and drain electrodes 15 of the present disclosure can be connected to the second active layer 3 by connecting to the first protective layer 4.

[0197] Therefore, compared to the first and second embodiments, this embodiment does not require an interlayer dielectric layer, nor does it require a through hole connecting the source / drain electrode 15 and the third edge portion 34. Therefore, the process flow of this embodiment is simpler than that of the first and second embodiments. Furthermore, in this embodiment, the material of the first active layer 2 can be either a crystalline oxide or an amorphous oxide. Therefore, compared to the method used in the third embodiment, the manufacturing method used in this embodiment offers greater freedom in material selection and a simpler process.

[0198] In addition, in this embodiment, the thin film transistor may further include a second protective layer 5 and a fifth protective layer 8, and the method for manufacturing the thin film transistor may further include:

[0199] A second protective layer 5 is formed to cover the second active layer 3 and the source / drain electrodes 15 so as to protect the second active layer 3 and the source / drain electrodes 15 from damage. It should be noted that when the source / drain electrodes 15 do not completely cover the surface of the first protective layer 4, the second protective layer 5 may also cover the remaining portion of the first protective layer 4.

[0200] Furthermore, a fifth protection layer 8 covering the second protection layer 5 may be formed to further protect the second active layer 3 and the source and drain electrodes 15 through the fifth protection layer 8 .

[0201] It should be noted that although the steps of the thin film transistor fabrication method disclosed herein are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0202] A third aspect of the present disclosure provides an array substrate that may include the thin-film transistors described above. Consequently, the thin-film transistors in the array substrate can exhibit good uniformity and avoid humping when fabricated using materials with any etching selectivity ratio for the first active layer 2 and the second active layer 3. This ensures that the array substrate 1 exhibits excellent operational stability.

[0203] A fourth aspect of the present disclosure provides a display panel that may include the array substrate described above. Because the thin-film transistors in the array substrate can be fabricated using materials with any etching selectivity ratio for the first active layer 2 and the second active layer 3, they can exhibit good uniformity and avoid humping. This allows the display panel to exhibit excellent operational stability.

[0204] A fifth aspect of the present disclosure provides a display device, which may include the display panel described above. Because the thin-film transistors in the display panel can be fabricated with materials having any etching selectivity ratio for the first active layer 2 and the second active layer 3, they can exhibit good uniformity and avoid humping. This allows the display device to have excellent operational stability.

[0205] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A thin film transistor, characterized in that: include: substrate; a first active layer located on one side of the substrate, wherein the first active layer has a first middle portion and a first edge portion, wherein the first middle portion is located between the first edge portions; a second active layer located at least on a surface of the first middle portion; a first protective layer, covering at least a first edge portion of the first active layer; a source and drain electrode, located on a side of the second active layer away from the substrate and connected to the second active layer; a gate layer, located on a side of the second active layer away from the substrate, or located on a surface of the substrate close to the first active layer; The first active layer and the second active layer are made of different materials, and the second active layer has a second middle portion and a second edge portion, wherein the second middle portion is located on the surface of the first middle portion, and the second edge portion is located on the surface of the first protective layer away from the first edge portion and part of the surface of the second middle portion.

2. The thin film transistor according to claim 1, wherein The thin film transistor further includes: A first gate insulating layer, wherein the first gate insulating layer at least covers the second active layer, and the gate layer is located on a surface of the first gate insulating layer away from the first active layer.

3. The thin film transistor according to claim 2, wherein: The thin film transistor further includes: a first interlayer dielectric layer, the first interlayer dielectric layer is located on a surface of the first gate insulating layer away from the second active layer and covers the gate layer, a first through hole is provided on the first interlayer dielectric layer and the first gate insulating layer, the source and drain are located on a surface of the first interlayer dielectric layer away from the second active layer, and are connected to the second active layer through the first through hole.

4. The thin film transistor according to claim 2, wherein: The material of the first active layer is crystalline oxide.

5. The thin film transistor according to claim 1, wherein The gate layer is located on a surface of the substrate close to the first active layer, and the thin film transistor further includes: A third gate insulating layer covers the gate, and the first active layer is located on a surface of the third gate insulating layer away from the substrate.

6. The thin film transistor according to claim 5, wherein: The source and drain electrodes are at least located on a surface of the second edge portion.

7. The thin film transistor according to claim 6, wherein: The thin film transistor further includes: A second protective layer at least covers the second active layer and the source and drain electrodes.

8. A method for manufacturing a thin film transistor, characterized in that: include: providing a substrate; forming a first active layer on one side of the substrate, the first active layer having a first middle portion and a first edge portion, wherein the first middle portion is located between the first edge portions; Disposing a first protective layer on a first edge portion of the first active layer so that the first protective layer at least covers the first edge portion, and forming a second active layer on a surface of the first middle portion; After forming the first protective layer, forming a gate layer on a side of the second active layer away from the substrate, or before forming the first active layer, forming a gate layer on a surface of the substrate close to the first active layer; forming source and drain electrodes on a side of the second active layer away from the substrate, and connecting the source and drain electrodes to the second active layer; The first active layer and the second active layer are made of different materials, the second active layer has a second middle portion and a second edge portion, and the second edge portion is located on a surface of the first protective layer away from the first edge portion and a portion of a surface of the second middle portion.

9. The method for manufacturing a thin film transistor according to claim 8, wherein: After forming the first protection layer, forming a gate layer on a side of the second active layer away from the substrate; The forming of the first active layer on one side of the substrate comprises: depositing a first active layer on one side of the substrate and patterning the first active layer; An annealing process is performed on the patterned first active layer to crystallize the patterned first active layer.

10. The method for manufacturing a thin film transistor according to claim 9, wherein: The temperature of the annealing treatment is greater than or equal to 350° C., and the time range of the annealing treatment is between 0.5 hours and 1.5 hours.

11. The method for manufacturing a thin film transistor according to claim 9, wherein: The step of providing a first protective layer on a first edge portion of the first active layer so that the first protective layer at least covers the first edge portion, and forming a second active layer on a surface of the first middle portion comprises: forming the first protective layer covering the first active layer; Etching the first protective layer to expose a first middle portion of the first active layer; A second active layer is deposited on a surface of the remaining first protection layer away from the first active layer and a surface of the first middle portion, and the second active layer is patterned.

12. The method for manufacturing a thin film transistor according to claim 11, wherein: After forming the first protection layer, forming a gate layer on a side of the second active layer away from the substrate comprises: forming a first gate insulating layer covering at least the second active layer; A gate layer is formed on a side of the first gate insulating layer away from the second active layer, and the gate layer is patterned.

13. The method for manufacturing a thin film transistor according to claim 12, wherein: The step of forming a source and a drain on a side of the second active layer away from the substrate and connecting the source and the drain to the second active layer comprises: forming a first interlayer dielectric layer on a surface of the first gate insulating layer away from the second active layer, and making the first interlayer dielectric layer cover the gate layer; etching the first interlayer dielectric layer and the first gate insulating layer to form a first through hole and expose a surface of the second edge portion; A material for forming source and drain electrodes is deposited on the surface of the first interlayer dielectric layer and in the first through hole and patterned to form source and drain electrodes connected to the second edge portion.

14. The method for manufacturing a thin film transistor according to claim 8, wherein: Before forming the first active layer, a gate layer is formed on a surface of the substrate close to the first active layer. The forming of the first active layer on one side of the substrate includes: forming a gate layer on one side of the substrate and performing patterning on the gate layer; forming a third gate insulating layer to cover the patterned gate layer; forming the first active layer on a surface of the third gate insulating layer away from the substrate, and performing patterning on the first active layer; An annealing process is performed on the patterned first active layer to crystallize the patterned first active layer.

15. The method for manufacturing a thin film transistor according to claim 14, wherein: The step of providing a first protective layer on a first edge portion of the first active layer so that the first protective layer at least covers the first edge portion, and forming a second active layer on a surface of the first middle portion comprises: forming the first protective layer covering the first active layer; Etching the first protective layer to expose a first middle portion of the first active layer; A second active layer is deposited on a surface of the remaining first protection layer away from the first active layer and a surface of the first middle portion, and the second active layer is patterned.

16. The method for manufacturing a thin film transistor according to claim 15, wherein: The production method further comprises: A second protection layer is formed to cover at least the second active layer and the source and drain electrodes.

17. An array substrate, characterized in that: The array substrate includes the thin film transistor according to any one of claims 1 to 7.

18. A display panel, characterized in that: The display panel includes the array substrate according to claim 17.

19. A display device, characterized in that: The display device includes the display panel according to claim 18.

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