A multi-gear gain adjustment method and device

Abstract

An embodiment of the present invention provides a multi-level gain adjustment method and device, comprising: constructing an asymmetric gain structure including a P-terminal and an N-terminal; wherein the input ports of the P-terminal and the N-terminal are each connected in parallel to n input transconductors, and the input transconductors are respectively connected to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches; and m load resistors are connected in parallel to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches; based on the asymmetric gain structure, the equivalent transconductance of the input port and the equivalent load resistance of the output port of the P-terminal and the N-terminal are respectively obtained; and based on the equivalent transconductance of the input port and the equivalent load resistance of the output port of the P-terminal and the N-terminal, the differential gain of the asymmetric gain structure is obtained. The present invention increases the number of signal gain adjustment levels, thereby significantly reducing the number of operating switches.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency communication integrated circuit gain control, and in particular to a multi-level gain adjustment method and device. Background Art

[0002] In the field of radio frequency communication integrated circuits, traditional differential gain adjustment techniques use a symmetrical circuit structure to select the transconductance and load parameters of the RF transceiver circuit. Here, gain Ga = transconductance gm * load R1. The circuit gain is adjusted by switching switches to change the load and transconductance values. However, to achieve small gain steps and a wide gain adjustment range, a large number of gain steps is required. Therefore, the traditional method requires a large number of selector switches to change the transconductance gm and load R1 values. This not only occupies layout area, but also increases parasitic capacitance and limits the signal operating bandwidth due to the excessive number of switches. Summary of the Invention

[0003] The embodiments of the present invention provide a multi-level gain adjustment method and device to solve the problem in conventional differential gain adjustment technology that a large number of selection switches occupy layout area, increase parasitic capacitance, and limit signal operating bandwidth.

[0004] In a first aspect, an embodiment of the present invention provides a multi-level gain adjustment method, comprising:

[0005] An asymmetric gain structure including a P-terminal and an N-terminal is constructed; wherein the input ports of the P-terminal and the N-terminal are respectively connected in parallel with n input transconductors, and the input transconductors are respectively connected to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches, and m load resistors are respectively connected in parallel with the output port of the N-terminal and the output port of the P-terminal via a plurality of switches;

[0006] Based on the asymmetric gain structure, the equivalent transconductance of the input port and the equivalent load resistance of the output port are obtained respectively at the P terminal and the N terminal;

[0007] The differential gain of the asymmetric gain structure is obtained based on the input equivalent transconductance of the P-terminal and the N-terminal and the output equivalent load resistance.

[0008] Furthermore, the maximum gain level of the asymmetric gain structure is (2 m -1)*2 m *(2 n -1)*2 n / 4; the differential gain of the asymmetric gain structure is obtained based on the equivalent transconductance of the input port of the P terminal and the N terminal and the equivalent load resistance of the output port, and the calculation formula is as follows:

[0009] Ga=(gm_n*Rl_p+gm_p*Rl_n) / 2;

[0010] Where Ga is the differential gain, gm_n is the equivalent transconductance of the input port at the N end, Rl_p is the equivalent load resistance of the output port at the P end, gm_p is the equivalent transconductance of the input port at the P end, and Rl_n is the equivalent load resistance of the output port at the N end.

[0011] Furthermore, based on the asymmetric gain structure, the equivalent transconductance of the input port and the equivalent load resistance of the output port of the P terminal and the N terminal are obtained respectively, including:

[0012] Determine the number of working switches at the input port of the P end, and based on the number of working switches at the input port of the P end, select one of the permutations and combinations of i working switches from n switches as the equivalent transconductance of the input port of the P end; where i traverses from 1 to n, the total number of permutations and combinations of i working switches selected from n switches is 2 n -1;

[0013] Determine the number of working switches of the input port at the N end, and based on the number of working switches of the input port at the N end, select one of the permutations and combinations of j working switches from n switches as the equivalent transconductance of the input port at the N end; where j traverses from 1 to n, and the total number of permutations and combinations of j working switches selected from n switches is 2 n -1.

[0014] Furthermore, based on the asymmetric gain structure, the input equivalent transconductance of the P terminal and the N terminal and the output equivalent load resistance are obtained respectively, which also includes:

[0015] Determine the number of workloads at the output port of the P terminal, and based on the number of workloads at the output port of the P terminal, select one of the permutations and combinations of k workloads from m load resistors as the equivalent load resistor of the output port of the P terminal; wherein k ranges from 1 to m, and the total number of permutations and combinations of k workloads selected from m load resistors is 2 m -1;

[0016] Determine the number of workloads of the output port of the N terminal, and based on the number of workloads of the output port of the N terminal, select one of the permutations and combinations of q workloads from m load resistors as the equivalent load resistance of the output port of the N terminal; wherein q ranges from 1 to m, and the total number of permutations and combinations of q workloads selected from m load resistors is 2 m -1.

[0017] In a second aspect, an embodiment of the present invention provides a multi-level gain adjustment device, comprising:

[0018] A structural unit is constructed to construct an asymmetric gain structure including a P-terminal and an N-terminal; wherein the input ports of the P-terminal and the N-terminal are respectively connected in parallel with n input transconductors, and the input transconductors are respectively connected to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches, and m load resistors are respectively connected in parallel with the output port of the N-terminal and the output port of the P-terminal via a plurality of switches;

[0019] an equivalent selection unit, configured to obtain the equivalent transconductance of the input port of the P terminal and the equivalent load resistance of the output port of the N terminal based on the asymmetric gain structure;

[0020] The gain calculation unit is used to obtain the differential gain of the asymmetric gain structure based on the equivalent transconductance of the input port of the P terminal and the N terminal and the equivalent load resistance of the output port.

[0021] Furthermore, the maximum gain level of the asymmetric gain structure constructed by the construction unit is (2 m -1)*2 m *(2 n -1)*2 n / 4; the gain calculation unit is used to obtain the differential gain of the asymmetric gain structure based on the equivalent transconductance of the input port of the P terminal and the N terminal and the equivalent load resistance of the output port, and the calculation formula is as follows:

[0022] Ga=(gm_n*Rl_p+gm_p*Rl_n) / 2;

[0023] Where Ga is the differential gain, gm_n is the equivalent transconductance of the input port at the N end, Rl_p is the equivalent load resistance of the output port at the P end, gm_p is the equivalent transconductance of the input port at the P end, and Rl_n is the equivalent load resistance of the output port at the N end.

[0024] Furthermore, the equivalent selection unit includes a P-end equivalent transconductance module and an N-end equivalent transconductance module;

[0025] The P-end equivalent transconductance module is used to determine the number of working switches at the input port of the P-end, and based on the number of working switches at the input port of the P-end, select one of the permutations and combinations of i working switches from n switches as the equivalent transconductance of the input port of the P-end; wherein i traverses from 1 to n, and the total number of permutations and combinations of i working switches selected from n switches is 2 n -1;

[0026] The N-terminal equivalent transconductance module is used to determine the number of working switches at the input port of the N-terminal, and based on the number of working switches at the input port of the N-terminal, select one of the permutations and combinations of j working switches from n switches as the equivalent transconductance of the input port of the N-terminal; wherein j traverses from 1 to n, and the total number of permutations and combinations of j working switches selected from n switches is 2 n -1.

[0027] Furthermore, the equivalent selection unit further includes a P-end equivalent load resistance module and an N-end equivalent load resistance module;

[0028] The P-end equivalent load resistance module is used to determine the number of workloads of the output port of the P-end, and based on the number of workloads of the output port of the P-end, select one of the permutations and combinations of k workloads from m load resistors as the output port equivalent load resistance of the P-end; wherein k traverses from 1 to m, and the total number of permutations and combinations of k workloads selected from m load resistors is 2 m -1;

[0029] The N-terminal equivalent load resistance module is used to determine the number of workloads of the output port of the N-terminal, and based on the number of workloads of the output port of the N-terminal, select one of the permutations and combinations of q workloads from m load resistors as the output port equivalent load resistance of the N-terminal; wherein q traverses from 1 to m, and the total number of permutations and combinations of q workloads selected from m load resistors is 2 m -1.

[0030] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of any of the above-described multi-level gain adjustment methods are implemented.

[0031] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of any of the above-mentioned multi-level gain adjustment methods are implemented.

[0032] Embodiments of the present invention provide a multi-level gain adjustment method and device. This method constructs an asymmetric gain structure comprising a P-terminal and an N-terminal. Based on this asymmetric gain structure, the equivalent transconductance of the input port and the equivalent load resistance of the output port are calculated. Furthermore, the differential gain of the asymmetric gain structure is calculated based on the equivalent transconductance of the input port and the equivalent load resistance of the output port. This method reduces the layout area of ​​the gain adjustment circuit, increases the number of gain adjustment levels, and improves the operating bandwidth of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 This is a flow chart of a multi-gear gain adjustment method provided by the present invention;

[0035] Figure 2 Schematic diagram of the asymmetric gain structure provided by the present invention;

[0036] Figure 3 This is a structural diagram of a multi-level gain adjustment device provided by the present invention;

[0037] Figure 4 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION

[0038] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0039] The technical concept of the present invention is as follows: In order to address the problem in traditional differential gain adjustment technology that a large number of selection switches occupy the layout area, increase parasitic capacitance and limit the signal operating bandwidth, the present invention utilizes asymmetry in the selection of transconductance parameters and load parameters of the RF transceiver circuit, thereby increasing the number of gain adjustment gears, which is an improvement on conventional circuit gain adjustment technology.

[0040] The following combination Figure 1-Figure 4 The present invention describes a multi-level gain adjustment method and device.

[0041] An embodiment of the present invention provides a multi-level gain adjustment method. Figure 1 A flow chart of a multi-gear gain adjustment method provided by an embodiment of the present invention is shown as follows: Figure 1 As shown, the method includes:

[0042] Step 110: construct an asymmetric gain structure including a P-terminal and an N-terminal; wherein the input ports of the P-terminal and the N-terminal are respectively connected in parallel with n input transconductors, and the input transconductors are respectively connected to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches, and m load resistors are respectively connected in parallel with the output port of the N-terminal and the output port of the P-terminal via a plurality of switches;

[0043] Specifically, the multi-gear gain adjustment workflow is as follows: Figure 2 As shown, the input port Vin_P at the P-side is connected in parallel with n input transconductors. Transconductor gmi is connected to the output port Vout_N at the N-side via switch SWg1i. m loads Rlj are connected in parallel to the output port Vout_N at the N-side via switch SWR1j. Similarly, the input port Vin_N at the N-side is connected in parallel with n input transconductors. Transconductor gmi is connected to the output port Vout_P at the P-side via switch SWg2i. m loads Rlj are connected in parallel to the output port Vout_P at the P-side via switch SWR2j. The output DC blocking capacitor C removes DC offset.

[0044] Step 120, obtaining the input equivalent transconductance and output equivalent load resistance of the P-terminal and the N-terminal, respectively, based on the asymmetric gain structure;

[0045] Step 130 : Obtain the differential gain of the asymmetric gain structure based on the equivalent transconductance of the input ports of the P-terminal and the N-terminal and the equivalent load resistance of the output ports.

[0046] Compared with the prior art, the method provided in the embodiment of the present invention adopts an asymmetric gain adjustment structure and utilizes independent gain adjustment control of the P-end and the N-end, and increases the number of signal gain adjustment levels through the combined use of differentials, thereby greatly reducing the number of working switches.

[0047] Based on any of the above embodiments, the maximum gain level of the asymmetric gain structure is (2 m -1)*2 m *(2 n -1)*2 n / 4; the differential gain of the asymmetric gain structure is obtained based on the equivalent transconductance of the input port of the P terminal and the N terminal and the equivalent load resistance of the output port, and the calculation formula is as follows:

[0048] Ga=(gm_n*Rl_p+gm_p*Rl_n) / 2; (1)

[0049] Where Ga is the differential gain, gm_n is the equivalent transconductance of the input port at the N end, Rl_p is the equivalent load resistance of the output port at the P end, gm_p is the equivalent transconductance of the input port at the P end, and Rl_n is the equivalent load resistance of the output port at the N end.

[0050] It should be noted that if Figure 2 As shown, the switches on the P and N terminals are not required to operate simultaneously. That is, SWR1x and SWR2x do not need to be used synchronously, and SWg1x and SWg2x do not need to be used synchronously. To ensure that the currents controlled by the input signals on the P and N terminals can be transmitted to the output, SWR1 cannot be fully disconnected. Similarly, SWR2 cannot be fully disconnected, SWg1 cannot be fully disconnected, and SWg2 cannot be fully disconnected.

[0051] Vout_P=Vin_N*gm_n*Rl_p (2)

[0052] Vout_N=Vin_P*gm_p*Rl_n (3)

[0053] Here gm_n is the equivalent transconductance of the input port of the N terminal, Rl_p is the equivalent load resistance of the output port of the P terminal, gm_p is the equivalent transconductance of the input port of the P terminal, and Rl_n is the equivalent load resistance of the output port of the N terminal.

[0054] Since the differential input signal Vin_P = -Vin_N, it can be obtained from equations (2) and (3):

[0055] Differential output Vout = Vout_P - Vout_N

[0056] =Vin_N*gm_n*Rl_p-Vin_P*gm_p*Rl_n

[0057] =Vin_N*(gm_n*Rl_p+gm_p*Rl_n) (4) Therefore, the differential gain Ga=(gm_n*Rl_p+gm_p*Rl_n) / 2 (5)

[0058] From (5), we can see that the traditional symmetrical circuit gm_n=gm_p, Rl_n=Rl_p is a special case of the gain of the present invention.

[0059] Further theoretical calculations can compare the respective gain levels:

[0060] Assume there are m resistors and n transconductors, and there are 2 combinations of resistors. m -1 type, there are 2 cross-duct combinations n -1 species.

[0061] The maximum traditional gain level is (2 m -1)*(2 n -1) pcs. (6) The maximum gain level of the present invention is (2 m -1)*2 m *(2 n -1)*2 n / 4 pcs. (7)

[0062] It can be seen that under the condition that the number of loads and cross-conduits is the same, the present invention greatly increases the number of gears. From another perspective, under the same number of gain gears, the present invention greatly reduces the number of loads and cross-conduits, and reduces the number of switches.

[0063] For a simple example: n=1, m=2, input tube gm1, load resistors Rl1 and Rl2.

[0064] 1.) Input pipe combination has 2 1 -1=1 species: g1=gm1;

[0065] Load resistor combination 2 2 -1=3 types: R1=Rl1, R2=Rl2, R3=Rl1 / / Rl2.

[0066] 2.) Traditional gain levels are (2 1 -1)*(2 2 -1) = 3

[0067] Ga1=g1*R1, Ga2=g1*R2, Ga3=g1*R3;

[0068] 3.) The gain levels of the present invention are (2 1 -1)*2 1 *(2 2 -1)*2 2 / 4=6

[0069] Ga1=g1*R1, Ga2=g1*R2, Ga3=g1*R3, Ga4=g1*(R1+R2) / 2,

[0070] Ga5=g1*(R1+R3) / 2, Ga6=g1*(R2+R3) / 2;

[0071] It can be seen from formula (6) and formula (7) that the larger the n value and the m value are, the more obvious the increase in the gear position of the present invention compared with the traditional one.

[0072] Based on any of the above embodiments, obtaining the input equivalent transconductance and output equivalent load resistance of the P-terminal and the N-terminal, respectively, based on the asymmetric gain structure includes:

[0073] Determine the number of working switches at the input port of the P end, and based on the number of working switches at the input port of the P end, select one of the permutations and combinations of i working switches from n switches as the equivalent transconductance of the input port of the P end; where i traverses from 1 to n, the total number of permutations and combinations of i working switches selected from n switches is 2 n -1;

[0074] Specifically, the input port of the P terminal first determines the number of SWg switches to be selected for operation. For example, i SWgs are selected for operation, and then i switches are selected from n switches through permutations and combinations. There are three choices, one of which is denoted as SWg1a1, ... SWg1ai, and the equivalent transconductance gm_p is obtained; if i is traversed from 1 to n, and then the i is selected from n, then the total equivalent transconductance of the combination is kind.

[0075] Determine the number of working switches of the input port at the N end, and based on the number of working switches of the input port at the N end, select one of the permutations and combinations of j working switches from n switches as the equivalent transconductance of the input port at the N end; where j traverses from 1 to n, and the total number of permutations and combinations of j working switches selected from n switches is 2 n -1.

[0076] Specifically, in the same way as the input port of the P terminal selects the working switch, the input port of the N terminal selects j SWg to work, recorded as SWg2b1, ... SWg2bj, and obtains the equivalent transconductance gm_n; if j traverses from 1 to n, and then the j are selected from n in a permutation and combination, then the total equivalent transconductance of the combination is 2 n -1 species.

[0077] Based on any of the above embodiments, the method further includes: obtaining the input equivalent transconductance of the P-terminal and the output equivalent load resistance of the N-terminal based on the asymmetric gain structure;

[0078] Determine the number of workloads at the output port of the P terminal, and based on the number of workloads at the output port of the P terminal, select one of the permutations and combinations of k workloads from m load resistors as the equivalent load resistor of the output port of the P terminal; wherein k ranges from 1 to m, and the total number of permutations and combinations of k workloads selected from m load resistors is 2 m -1;

[0079] Specifically, the output port of the P terminal selects k SWRs to work, SWR1c1, ... SWR1ck, and obtains the equivalent load resistance Rl_p; if k is traversed from 1 to m, and then these k are selected from m in a permutation and combination, then the total equivalent load resistance of the combination is 2 m -1 species.

[0080] Determine the number of workloads of the output port of the N terminal, and based on the number of workloads of the output port of the N terminal, select one of the permutations and combinations of q workloads from m load resistors as the equivalent load resistance of the output port of the N terminal; wherein q ranges from 1 to m, and the total number of permutations and combinations of q workloads selected from m load resistors is 2m -1.

[0081] Specifically, the output port of the N terminal selects q SWRs to work, SWR2d1, ... SWR2dq, to ​​obtain the equivalent load resistance Rl_n; if q is traversed from 1 to m, and then these q are selected from m in a permutation and combination, then the total equivalent load resistance of the combination is 2 m -1 species.

[0082] It should be noted that the differential gain Ga under the above configuration in the asymmetric gain structure is (gm_n*Rl_p+gm_p*Rl_n) / 2. When gm_n=gm_p and Rl_p=Rl_n, it becomes the traditional method. It can be seen that the traditional method is a special case of the present invention, and the maximum total gain level after the arrangement and combination of the present invention is (2 m -1)*2 m *(2 n -1)*2 n / 4, which is much larger than the traditional gain gear (2 m -1)*(2 n -1) items.

[0083] Furthermore, the maximum gain is achieved when all SWg switches are operating (connected in parallel to form the maximum transconductance) and a maximum load resistance is selected. Therefore, the maximum gain of the conventional method and the method of the present invention is the same. The minimum gain is achieved when the minimum transconductance is selected for both the P and N terminals and all SWR switches are operating (connected in parallel to form the minimum load resistance). Therefore, the minimum gain of the conventional method and the method of the present invention is also the same. From the theoretical analysis of (6) and (7), it can be seen that the present invention adds a large number of gain gears, thereby refining the gain step size within the same gain range.

[0084] A multi-level gain adjustment device provided by the present invention is described below. The multi-level gain adjustment method described below and the multi-level gain adjustment method described above can refer to each other.

[0085] Figure 3 A schematic diagram of the structure of a multi-level gain adjustment device provided by an embodiment of the present invention is shown in FIG. Figure 3 As shown, the device includes a construction unit 310, an equivalent selection unit 320 and a gain calculation unit 330;

[0086] A construction unit 310 is configured to construct an asymmetric gain structure including a P-terminal and an N-terminal; wherein the input ports of the P-terminal and the N-terminal are respectively connected in parallel with n input transconductors, and the input transconductors are respectively connected to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches, and m load resistors are respectively connected in parallel with the output port of the N-terminal and the output port of the P-terminal via a plurality of switches;

[0087] An equivalent selection unit 320 is configured to obtain an input equivalent transconductance and an output equivalent load resistance of the P-terminal and the N-terminal, respectively, based on the asymmetric gain structure;

[0088] The gain calculation unit 330 is configured to obtain the differential gain of the asymmetric gain structure based on the equivalent transconductance of the input ports of the P-terminal and the N-terminal and the equivalent load resistance of the output ports.

[0089] Compared with the prior art, the device provided in the embodiment of the present invention adopts an asymmetric gain adjustment structure and utilizes independent gain adjustment control of the P-end and the N-end, and increases the number of signal gain adjustment levels through the combined use of differentials, thereby greatly reducing the number of working switches.

[0090] Based on any of the above embodiments, the maximum gain level of the asymmetric gain structure constructed by the construction unit is (2 m -1)*2 m *(2 n -1)*2 n / 4; the gain calculation unit is used to obtain the differential gain of the asymmetric gain structure based on the equivalent transconductance of the input port of the P terminal and the N terminal and the equivalent load resistance of the output port, and the calculation formula is as follows:

[0091] Ga=(gm_n*Rl_p+gm_p*Rl_n) / 2; (8)

[0092] Where Ga is the differential gain, gm_n is the equivalent transconductance of the input port at the N end, Rl_p is the equivalent load resistance of the output port at the P end, gm_p is the equivalent transconductance of the input port at the P end, and Rl_n is the equivalent load resistance of the output port at the N end.

[0093] Based on any of the above embodiments, the equivalent selection unit includes a P-end equivalent transconductance module and an N-end equivalent transconductance module;

[0094] The P-end equivalent transconductance module is used to determine the number of working switches at the input port of the P-end, and based on the number of working switches at the input port of the P-end, select one of the permutations and combinations of i working switches from n switches as the equivalent transconductance of the input port of the P-end; wherein i traverses from 1 to n, and the total number of permutations and combinations of i working switches selected from n switches is 2 n -1;

[0095] The N-terminal equivalent transconductance module is used to determine the number of working switches at the input port of the N-terminal, and based on the number of working switches at the input port of the N-terminal, select one of the permutations and combinations of j working switches from n switches as the equivalent transconductance of the input port of the N-terminal; wherein j traverses from 1 to n, and the total number of permutations and combinations of j working switches selected from n switches is 2 n-1.

[0096] Based on any of the above embodiments, the equivalent selection unit further includes a P-end equivalent load resistance module and an N-end equivalent load resistance module;

[0097] The P-end equivalent load resistance module is used to determine the number of workloads of the output port of the P-end, and based on the number of workloads of the output port of the P-end, select one of the permutations and combinations of k workloads from m load resistors as the output port equivalent load resistance of the P-end; wherein k traverses from 1 to m, and the total number of permutations and combinations of k workloads selected from m load resistors is 2 m -1;

[0098] The N-terminal equivalent load resistance module is used to determine the number of workloads of the output port of the N-terminal, and based on the number of workloads of the output port of the N-terminal, select one of the permutations and combinations of q workloads from m load resistors as the output port equivalent load resistance of the N-terminal; wherein q traverses from 1 to m, and the total number of permutations and combinations of q workloads selected from m load resistors is 2 m -1.

[0099] Based on any of the above embodiments, the maximum gain level of the asymmetric gain structure is (2 m -1)*2 m *(2 n -1)*2 n / 4.

[0100] Figure 4 An example of a physical structure diagram of an electronic device is shown below. Figure 4 As shown, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communications bus 440, wherein the processor 410, the communications interface 420, and the memory 430 communicate with each other via the communications bus 440. The processor 410 may call logic instructions in the memory 430 to execute a multi-level gain adjustment method, which includes: constructing an asymmetric gain structure including a P-terminal and an N-terminal; wherein the input ports of the P-terminal and the N-terminal are respectively connected in parallel with n input transconductors, and the input transconductors are respectively connected to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches, and the output ports of the N-terminal and the P-terminal are respectively connected in parallel with m load resistors via a plurality of switches; based on the asymmetric gain structure, the equivalent transconductance of the input port and the equivalent load resistance of the output port of the P-terminal and the N-terminal are respectively obtained; and based on the equivalent transconductance of the input port and the equivalent load resistance of the output port of the P-terminal and the N-terminal, the differential gain of the asymmetric gain structure is obtained.

[0101] In addition, the logic instructions in the above-mentioned memory 430 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0102] On the other hand, the present invention also provides a computer program product, comprising a computer program stored on a non-transitory computer-readable storage medium, the computer program comprising program instructions. When the program instructions are executed by a computer, the computer is capable of executing the multi-level gain adjustment method provided by each of the above methods. The method comprises: constructing an asymmetric gain structure including a P-terminal and an N-terminal; wherein the input ports of the P-terminal and the N-terminal are respectively connected in parallel with n input transconductors, and the input transconductors are respectively connected to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches, and m load resistors are respectively connected in parallel with the output port of the N-terminal and the output port of the P-terminal via a plurality of switches; based on the asymmetric gain structure, an equivalent transconductance of the input port and an equivalent load resistance of the output port of the P-terminal and the N-terminal are respectively obtained; and based on the equivalent transconductance of the input port and the equivalent load resistance of the output port of the P-terminal and the N-terminal, a differential gain of the asymmetric gain structure is obtained.

[0103] In yet another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon. When executed by a processor, the computer program is implemented to perform the above-mentioned multi-level gain adjustment methods, the methods comprising: constructing an asymmetric gain structure including a P-terminal and an N-terminal; wherein the input ports of the P-terminal and the N-terminal are respectively connected in parallel to n input transconductors, and the input transconductors are respectively connected to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches, and m load resistors are respectively connected in parallel to the output port of the N-terminal and the output port of the P-terminal via a plurality of switches; based on the asymmetric gain structure, an equivalent transconductance of the input port and an equivalent load resistance of the output port of the P-terminal and the N-terminal are respectively obtained; and based on the equivalent transconductance of the input port and the equivalent load resistance of the output port of the P-terminal and the N-terminal, a differential gain of the asymmetric gain structure is obtained.

[0104] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0105] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A multi-gear gain adjustment method, characterized in that: include: An asymmetric gain structure including a P-terminal and an N-terminal is constructed; wherein the input ports of the P-terminal and the N-terminal are respectively connected in parallel with n input transconductors, the input transconductor connected to the P-terminal input port is connected to the output port of the N-terminal via a plurality of switches, and the input transconductor connected to the N-terminal input port is connected to the output port of the P-terminal via a plurality of switches, and m load resistors are respectively connected in parallel with the output ports of the N-terminal and the P-terminal via a plurality of switches; Based on the asymmetric gain structure, the equivalent transconductance of the input port and the equivalent load resistance of the output port are obtained respectively at the P terminal and the N terminal; Obtaining the differential gain of the asymmetric gain structure based on the input equivalent transconductance of the P-terminal and the N-terminal and the output equivalent load resistance; The equivalent transconductance of the input port and the equivalent load resistance of the output port of the P-terminal and the N-terminal are obtained based on the asymmetric gain structure, including: Select several working switches from the working switches of the P-end input port as the equivalent transconductance of the P-end input port, select several working switches from the working switches of the N-end input port as the equivalent transconductance of the N-end input port, select several working loads from the working loads of the P-end output port as the equivalent load resistance of the P-end output port, and select several working loads from the working loads of the N-end output port as the equivalent load resistance of the N-end output port.

2. The multi-gear gain adjustment method according to claim 1, characterized in that: The maximum gain level of the asymmetric gain structure is (2 m -1)*2 m *(2 n -1)*2 n / 4; the differential gain of the asymmetric gain structure is obtained based on the equivalent transconductance of the input port of the P terminal and the N terminal and the equivalent load resistance of the output port, and the calculation formula is as follows: Ga=(gm_n*Rl_p+gm_p*Rl_n) / 2; Where Ga is the differential gain, gm_n is the equivalent transconductance of the input port at the N end, Rl_p is the equivalent load resistance of the output port at the P end, gm_p is the equivalent transconductance of the input port at the P end, and Rl_n is the equivalent load resistance of the output port at the N end.

3. The multi-level gain adjustment method according to claim 1, wherein: Based on the asymmetric gain structure, the equivalent transconductance of the input port and the equivalent load resistance of the output port of the P terminal and the N terminal are obtained respectively, including: Determine the number of working switches at the input port of the P end, and based on the number of working switches at the input port of the P end, select one of the permutations and combinations of i working switches from n switches as the equivalent transconductance of the input port of the P end; where i traverses from 1 to n, the total number of permutations and combinations of i working switches selected from n switches is 2 n -1; Determine the number of working switches of the input port at the N end, and based on the number of working switches of the input port at the N end, select one of the permutations and combinations of j working switches from n switches as the equivalent transconductance of the input port at the N end; where j traverses from 1 to n, and the total number of permutations and combinations of j working switches selected from n switches is 2 n -1.

4. The multi-level gain adjustment method according to claim 1, wherein: Based on the asymmetric gain structure, the equivalent transconductance of the input port and the equivalent load resistance of the output port of the P terminal and the N terminal are obtained respectively, and the method further includes: Determine the number of workloads at the output port of the P terminal, and based on the number of workloads at the output port of the P terminal, select one of the permutations and combinations of k workloads from m load resistors as the equivalent load resistor of the output port of the P terminal; wherein k ranges from 1 to m, and the total number of permutations and combinations of k workloads selected from m load resistors is 2 m -1; Determine the number of workloads of the output port of the N terminal, and based on the number of workloads of the output port of the N terminal, select one of the permutations and combinations of q workloads from m load resistors as the equivalent load resistance of the output port of the N terminal; wherein q ranges from 1 to m, and the total number of permutations and combinations of q workloads selected from m load resistors is 2 m -1.

5. A multi-level gain adjustment device, characterized in that: include: A structural unit is constructed to construct an asymmetric gain structure including a P-terminal and an N-terminal; wherein the input ports of the P-terminal and the N-terminal are respectively connected in parallel with n input transconductors, the input transconductor connected to the P-terminal input port is connected to the output port of the N-terminal via a plurality of switches, and the input transconductor connected to the N-terminal input port is connected to the output port of the P-terminal via a plurality of switches, and m load resistors are respectively connected in parallel with the output ports of the N-terminal and the P-terminal via a plurality of switches; an equivalent selection unit, configured to obtain the equivalent transconductance of the input port of the P terminal and the equivalent load resistance of the output port of the N terminal based on the asymmetric gain structure; a gain calculation unit, configured to obtain a differential gain of the asymmetric gain structure based on an equivalent transconductance of the input port of the P terminal and the N terminal and an equivalent load resistance of the output port; Among them, the equivalent selection unit is specifically used to select several working switches from the working switches of the P-end input port as the equivalent transconductance of the P-end input port, select several working switches from the working switches of the N-end input port as the equivalent transconductance of the N-end input port, select several working loads from the working loads of the P-end output port as the equivalent load resistance of the P-end output port, and select several working loads from the working loads of the N-end output port as the equivalent load resistance of the N-end output port.

6. The multi-level gain adjustment device according to claim 5, characterized in that: The maximum gain level of the asymmetric gain structure constructed by the structural unit is (2 m -1)*2 m *(2 n -1)*2 n / 4; The gain calculation unit is used to obtain the differential gain of the asymmetric gain structure based on the equivalent transconductance of the input port of the P terminal and the N terminal and the equivalent load resistance of the output port, and the calculation formula is as follows: Ga=(gm_n*Rl_p+gm_p*Rl_n) / 2; Where Ga is the differential gain, gm_n is the equivalent transconductance of the input port at the N end, Rl_p is the equivalent load resistance of the output port at the P end, gm_p is the equivalent transconductance of the input port at the P end, and Rl_n is the equivalent load resistance of the output port at the N end.

7. The multi-level gain adjustment device according to claim 5, characterized in that: The equivalent selection unit includes a P-end equivalent transconductance module and an N-end equivalent transconductance module; The P-end equivalent transconductance module is used to determine the number of working switches at the input port of the P-end, and based on the number of working switches at the input port of the P-end, select one of the permutations and combinations of i working switches from n switches as the equivalent transconductance of the input port of the P-end; wherein i traverses from 1 to n, and the total number of permutations and combinations of i working switches selected from n switches is 2 n -1; The N-terminal equivalent transconductance module is used to determine the number of working switches at the input port of the N-terminal, and based on the number of working switches at the input port of the N-terminal, select one of the permutations and combinations of j working switches from n switches as the equivalent transconductance of the input port of the N-terminal; wherein j traverses from 1 to n, and the total number of permutations and combinations of j working switches selected from n switches is 2 n -1.

8. The multi-level gain adjustment device according to claim 5, characterized in that: The equivalent selection unit also includes a P-end equivalent load resistance module and an N-end equivalent load resistance module; The P-end equivalent load resistance module is used to determine the number of workloads of the output port of the P-end, and based on the number of workloads of the output port of the P-end, select one of the permutations and combinations of k workloads from m load resistors as the output port equivalent load resistance of the P-end; wherein k traverses from 1 to m, and the total number of permutations and combinations of k workloads selected from m load resistors is 2 m -1; The N-terminal equivalent load resistance module is used to determine the number of workloads of the output port of the N-terminal, and based on the number of workloads of the output port of the N-terminal, select one of the permutations and combinations of q workloads from m load resistors as the output port equivalent load resistance of the N-terminal; wherein q traverses from 1 to m, and the total number of permutations and combinations of q workloads selected from m load resistors is 2 m -1.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the multi-level gain adjustment method according to any one of claims 1 to 4 are implemented.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the multi-level gain adjustment method according to any one of claims 1 to 4 are implemented.

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