A / D conversion circuit

Abstract

The digital / analog converter included in the A / D conversion circuit of the present invention has: a plurality of bit circuits, in which capacitors, first switches, and series circuits are provided corresponding to a plurality of bits. One end of the capacitor outputs a comparison potential, and the capacitance value of the capacitor increases as it moves from the lower-order bit to the higher-order bit among the plurality of bits. The first switch applies an input potential to the other end of the capacitor. The series circuit is a series circuit of a second switch and a current amount control element between the other end of the capacitor and the reference power supply; and a current amount control unit that controls the current amount flowing through the current amount control elements provided in each of the bit circuits of the plurality of bit circuits. When the second switches are sequentially turned on starting from the higher-order bit in each of the bit circuits of the plurality of bit circuits according to the digital value, during the period when the second switch in any bit circuit where the noise current proportional to the charge flowing from the capacitor into the reference power supply reaches or exceeds the allowable value is turned on, the current amount control unit applies a current control potential to the current amount control element in any bit circuit, thereby limiting the noise current to be less than the allowable value.

Description

Technical Field

[0001] The present invention relates to a successive approximation type A / D conversion circuit. Background Art

[0002] As an A / D conversion circuit, a successive approximation type A / D conversion circuit using a capacitive digital-to-analog converter (hereinafter referred to as CDAC) in the generation of a comparison potential is known. As Figure 13 shown, a CDAC (Capacitive Digital-to-Analog Converter) has capacitors C1-C4, whose capacitance values are weighted by 2 as 1C, 2C, 4C n C; and a series circuit composed of switches swA1-swA4, swH1-swH4, swL1-swL4, a reference power supply (VrefH / VrefL), a resistor R1 for generating a 1 / 2 potential of the reference power supply, and a resistor R2. As Figure 14 shown, the switches swA1-swA4, swH1-swH4, swL1-swL4 are analog switches composed of MOS-FETs M1, M2, and an inverter IN1.

[0003] The CDAC has, for example, 3-bit bit circuits D2, D1, D0. To input an input potential to the CDAC, Figure 15 the switches swA1-swA4 shown are turned on. The operation of inputting the input potential is called a "sampling operation". At this time, the input potential and the comparison potential are connected via the capacitors C4-C1 shown as 4C, 2C, 1C, 1C. Charges due to the difference between the input potential and the comparison potential are accumulated in the capacitors C4-C1.

[0004] Even if the switches swA1 to swA4 are turned off using the charges accumulated in the capacitors C4-C1, Figure 16 the potential of the node shown by the thick solid line in

[0005] is preserved. This operation is called a "holding operation". Figure 17 Then, as

[0006] Try combinations of switch closures to retrieve combinations of switches where the comparison potential is consistent with 1 / 2 the potential of the reference power supply during the sampling operation. For example, when the switches swH of bit circuit D2 and the switches swL of bit circuits D1 and D0 are closed, the comparator compares the comparison potential with the reference potential that is 1 / 2 the potential of the reference power supply Vref. When the comparison potential becomes the reference potential that is 1 / 2 the potential of the reference power supply Vref, the digital value corresponding to the input potential of the comparator is 100 (binary). That is, bit circuit D2 outputs "1", bit circuit D1 outputs "0", and bit circuit D0 outputs "0". This is the conversion result of the A / D conversion circuit.

[0007] Prior Art Documents

[0008] Patent Documents

[0009] Patent Document 1: Japanese Patent Laid-Open No. 4-129332 Summary of the Invention

[0010] Problems to be Solved by the Invention

[0011] In order to reduce the error of such an A / D conversion circuit, it is necessary to reduce the error of the output potential of the CDAC. In order to reduce the error of the output potential of the CDAC, the potentials of the reference power supplies VrefH and VrefL need to be the desired correct potentials. The CDAC is configured to inject a noise current into the reference power supply during operation. When a noise current is injected into the reference power supply, a deviation of the reference power supply impedance × noise current = noise voltage is generated in the reference power supply. Therefore, it will introduce an error to the A / D conversion circuit.

[0012] The problem of the present invention is to provide an A / D conversion circuit that can suppress the noise voltage to a small level and reduce the error.

[0013] Means for Solving the Problems

[0014] To solve the above problems, the A / D conversion circuit of the present invention has a digital-to-analog converter that generates a comparison potential based on the potential, digital value, and reference power supply obtained by sampling / holding the input potential. The A / D conversion circuit compares the comparison potential with a reference potential generated based on the reference power supply, converts the comparison potential into the digital value, and outputs the converted digital value to the digital-to-analog converter.

[0015] The digital / analog converter has: a plurality of bit circuits, in which capacitors, first switches, and series circuits are provided corresponding to a plurality of bits. One end of each capacitor outputs a comparison potential, and the capacitance value of the capacitor increases as the bit position moves from the lower-order bit to the higher-order bit among the plurality of bits. The first switch applies the input potential to the other end of the capacitor. The series circuit is a series circuit of a second switch and a current control element between the other end of the capacitor and the reference power supply; and a current control unit that controls the current flowing through the current control elements provided in each of the bit circuits of the plurality of bit circuits. When the second switches are sequentially turned on from the higher-order bit in each bit circuit according to the digital value, during the period when the second switch in any of the bit circuits where the noise current proportional to the charge flowing from the capacitor into the reference power supply reaches or exceeds the allowable value is turned on, the current control unit applies a current control potential to the current control element in any of the bit circuits, thereby limiting the noise current to less than the allowable value.

[0016] Advantages of the Invention

[0017] According to the present invention, when the second switches are sequentially turned on from the higher-order bit in each bit circuit according to the digital value, during the period when the second switch in any of the bit circuits where the noise current reaches or exceeds the allowable value is turned on, a current control potential is applied to the current control element in any of the bit circuits, thereby limiting the noise current to less than the allowable value.

[0018] Thereby, the noise current flowing into the reference power supply can be made less than the allowable value. That is, an A / D conversion circuit capable of suppressing the noise voltage to a small value and reducing errors can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is an overall structural diagram of the A / D conversion circuit according to the first embodiment.

[0020] Figure 2 is a diagram showing the structure of the CDAC in the A / D conversion circuit according to the first embodiment.

[0021] Figure 3 is a diagram of a bit circuit of the CDAC according to the first embodiment in which a series circuit of a capacitor and a switch provided between the reference power supply and the comparison potential is provided for each bit.

[0022] Figure 4 is a diagram showing Figure 3 the change over time of the noise current proportional to the charge flowing from the capacitor into the reference power supply when the switches are sequentially turned on from the higher-order bit in each of the bit circuits shown.

[0023] Figure 5 A diagram showing a plurality of bit circuits of a series circuit in which a switch and a current amount control element are provided between a capacitor and a reference power source.

[0024] Figure 6 A diagram showing Figure 5 the change over time of the noise current when the current flowing through the current amount control element is restricted when the switches are sequentially turned on starting from the most significant bit in the plurality of bit circuits shown.

[0025] Figure 7 A diagram for explaining the problems that occur when a constant current flows when each switch of each bit circuit is turned on.

[0026] Figure 8 A diagram showing a constant current control potential that is applied to the current amount control element only for a certain period when the switch is turned on.

[0027] Figure 9 A diagram showing the case where the setup time becomes longer when a constant current control potential is applied to the current amount control element.

[0028] Figure 10 A structural diagram of the main part of the A / D conversion circuit according to the second embodiment.

[0029] Figure 11 A diagram showing the current control potential when increasing and decreasing with respect to a constant value.

[0030] Figure 12 A diagram showing Figure 11 the case where the setup time becomes shorter when the variable current control potential shown is applied to the current amount control element.

[0031] Figure 13 A diagram showing the structure of an existing CDAC.

[0032] Figure 14 A diagram showing the structure of each switch in an existing CDAC.

[0033] Figure 15 A diagram showing the sampling operation of the input potential when the switch of an existing CDAC is turned on.

[0034] Figure 16 A diagram showing the holding operation of the charge stored in the capacitor of an existing CDAC.

[0035] Figure 17 A diagram showing the result of analog / digital conversion of an existing CDAC. Detailed implementation mode

[0036] Hereinafter, the A / D conversion circuit of the embodiment will be described with reference to the accompanying drawings.

[0037] (First Embodiment)

[0038] Figure 1 is the overall structure diagram of the A / D conversion circuit of the first embodiment. The A / D conversion circuit includes an ADC overall control unit 1, a CDAC 10, a comparator 20, and a successive approximation data generator 30.

[0039] The ADC overall control unit 1 controls the overall ADC and outputs a sampling control signal SCS to the switches swA1 - swA4 of the CDAC 10. The CDAC 10 samples the input potential and generates a comparison potential based on the potential held in the capacitor, the digital value, and the potential of the reference power supply Vref.

[0040] The comparator 20 compares the comparison potential from the CDAC 10 with the reference potential Vref / 2 generated based on the reference power supply Vref, and converts the comparison potential into a digital value. The successive approximation data generator 30 stores the digital value converted by the comparator 20 in a register (not shown), and outputs the digital value stored in the register as switch signals swH and swL to the CDAC 10.

[0041] Figure 2 is a diagram showing the structure of the CDAC in the A / D conversion circuit of the first embodiment. The A / D conversion circuit is a successive approximation type A / D conversion circuit that uses a CDAC including capacitors in the generation of the comparison potential.

[0042] The CDAC is characterized in that, relative to Figure 13 the shown CDAC, switches swH1 - swH4 and current control elements QH1 - QH4 are further provided between the capacitors C1 - C4 and the reference power supply VrefH, and switches swL1 - swL4 and current control elements QL1 - QL4 are provided between the capacitors C1 - C4 and the reference power supply VrefL.

[0043] Regarding the capacitors C2 - C4, one end outputs the comparison potential, and the capacitance value increases as it moves from the lower - order bits to the higher - order bits of multiple bits. The switches swA1 - swA4 apply the input potential to the other ends of the capacitors C1 - C4.

[0044] There are provided: a bit circuit D2 including a capacitor C4, a switch swH4, a current amount control element QH4, a switch swL4, and a current amount control element QL4; a bit circuit D1 including a capacitor C3, a switch swH3, a current amount control element QH3, a switch swL3, and a current amount control element QL3; and a bit circuit D0 including a capacitor C2, a switch swH2, a current amount control element QH2, a switch swL2, and a current amount control element QL2.

[0045] The current amount control unit 11 controls the current amounts flowing through the current amount control elements QH1 - QH4, QL1 - QL4. The current amount control elements QH1 - QH4, QL1 - QL4 are formed of MOSFETs, for example. The current amount control elements QH1 - QH4, QL1 - QL4 are also referred to as current amount control elements Q1 - Q4.

[0046] The switches swH, swL receive the digital values 1 or 0 from the successive approximation data generator 30, and are turned on according to the digital value 1 and turned off according to the digital value 0.

[0047] When the switches swH4, swH3, swH2, swH1 (in the order of switches swL4, swL3, swL2, swL1) are turned on in sequence from the high - order bit in each of the bit circuits D2, D1, D0, during the period when the switch swH4 (swL4) in an arbitrary bit circuit, for example, the bit circuit D2, is turned on and the noise current proportional to the charge flowing from the capacitors C4, C3, C2, C1 into the reference power supply VrefH (VrefL) reaches above the allowable value, the current amount control unit 11 applies a current control potential to the current amount control element QH4 (QL4), thereby limiting the noise current to less than the allowable value.

[0048] In addition, during the period when the switches swH3, swH2 (swL3, swL2) in the bit circuits D1, D0 other than an arbitrary bit circuit D2 are turned on, the current amount control unit 11 turns on the current amount control element QH4 (QL4), thereby not restricting the current amount.

[0049] Figure 3 A bit circuit showing a series circuit of capacitors C4 - C2 and switches sw4 - sw2 provided between the reference power supply Vref and the comparison potential for each bit. Figure 4 Shows the change over time of the noise current proportional to the charge flowing from the capacitors C4, C3, C2 into the reference power supply Vref when the switches sw4, sw3, sw2 are turned on in sequence starting from the high - order bit circuit.

[0050] Regarding the operation of the successive approximation type A / D conversion circuit, first, the CDAC is operated to compare the comparison potential with the reference potential, and the following process of determining the digital value of the CDAC is repeated. In the successive approximation type, since the digital value is obtained starting from the higher-order (larger value) bits, in consideration of the noise of the reference power supply, it is only necessary to consider the model of sequentially turning on Figure 3 the switches sw4, sw3, and sw2 shown.

[0051] When the switches sw4, sw3, and sw2 are sequentially turned on, the charges of 4C, 2C, and 1C flow from the capacitors C4, C3, and C2 into the reference power supply Vref. In the worst-case model of the CDAC, the charge amounts of 4C, 2C, and 1C are 4:2:1.

[0052] If the charge amount flowing into the reference power supply Vref has a proportional relationship with the noise current, then regarding the noise current and noise voltage, when the noise current (noise voltage) is 4 when the switch sw4 is turned on, the noise current (noise voltage) is 2 when the switch sw3 is turned on, and the noise current (noise voltage) is 1 when the switch sw2 is turned on. Therefore, in order to suppress noise, attention is paid to the operation of the higher-order bits.

[0053] In Figure 4 it shows the case where the allowable current is exceeded. When the higher-order bit switch sw4 is turned on at time t1, the noise current exceeds the allowable value and flows, and at time t2, it becomes zero. At time t3, the potential comparison between the comparison potential and the reference potential is performed. When the switch sw3 is turned on at time t4, the noise current becomes below the allowable value and flows, and at time t5, it becomes zero.

[0054] At time t6, the potential comparison between the comparison potential and the reference potential is performed. When the switch sw2 is turned on at time t7, the noise current becomes below the allowable value and flows, and at time t8, it becomes zero. At time t9, the potential comparison between the comparison potential and the reference potential is performed.

[0055] In this way, when the higher-order bit switch sw4 is turned on, since the noise current exceeds the allowable value, the noise error becomes large. Therefore, as Figure 5 shown, current control elements Q4, Q3, and Q2 are provided between the switches sw4, sw3, and sw2 and the reference power supply Vref.

[0056] As Figure 5 shown, in the case of sequentially turning on the switches sw4, sw3, and sw2 in order from the higher-order bits, during the period when the switch sw4 in the bit circuit D2 where the noise current proportional to the charge flowing from the capacitors C4, C3, and C2 into the reference power supply Vref reaches above the allowable value is turned on ( Figure 6At the times t11 - t13 shown, the current amount control unit 11 applies a current control potential to the current amount control element Q4, thereby limiting the noise current from the capacitor C4 to less than the allowable value.

[0057] Thereby, the noise current flowing into the reference power supply Vref can be made less than the allowable value. That is, an A / D conversion circuit capable of suppressing the noise voltage to a small value and reducing errors can be provided.

[0058] In addition, since the establishment time (the time t12 - t13 required to output the correct potential) of the bit circuit D2 to which current limitation is given becomes longer, a process of delaying the potential comparison time of this bit circuit is performed. There is an element in this process that slows down the conversion speed of the A / D conversion circuit. However, since not all bit conversions are slowed down, but only the establishment time of the bit circuit to which current limitation is applied is later, in the case of preferentially solving the noise problem of the reference power supply, this process has a greater advantage compared with the prior art.

[0059] In addition, the reason for current-limiting only the current of the corresponding bit during the switching of the corresponding bit is described below. When turning on each switch of the CDAC, if it is set such that only the switches sw4, sw3, and sw2 that pass a constant current flow, it may be considered that the same effect as the present invention is achieved.

[0060] Suppose the following situation is considered: when the switch sw4 is turned on, the noise current (noise voltage) exceeds the allowable value, and when the switches sw3 and sw2 are turned on, there is no problem. Suppose the on-resistance of the switch sw4 is designed to a value that suppresses the current. This design, like the present invention, can suppress the noise current (noise voltage) caused by the switch sw4 when the switch sw4 is turned on, in exchange for making the establishment time of the bit circuit D2 longer.

[0061] However, there is a problem with this design. As Figure 7 shown, when the on-resistance R of the switch sw4 is large, the establishment time also becomes longer when the switch sw3 or the switch sw2 is turned on and off.

[0062] In Figure 7 , in the case of turning on the switch sw3 and reducing the comparison potential, one end of the capacitor C4 should originally be the reference potential, but due to the presence of the large resistance R, it becomes a potential that temporarily exceeds the reference potential. Therefore, the comparison potential also temporarily becomes an incorrect value. This is eliminated by injecting charge from the reference potential to one end of the capacitor C4, but if the resistance R is large, it takes time to eliminate.

[0063] Therefore, increasing the on-resistance of the switch sw4 for the purpose of suppressing the noise current (noise voltage) will make the establishment time longer when the switches sw3 and sw2 are switched.

[0064] Therefore, in the first embodiment, during the period when the switch SW4 is turned on, the current control unit 11 applies a current control potential to the current control element Q4, thereby limiting the noise current to less than the allowable value. During the period when the switches SW3 and SW2 are turned on, the current of the current control element Q4 is not limited.

[0065] As a result, the increase in the settling time is limited to the current limiting case. By setting it so as not to affect the settling time when the current is not limited, an A / D conversion circuit that achieves both a faster conversion time and smaller noise than the prior art can be provided.

[0066] (Second Embodiment)

[0067] In the A / D conversion circuit of the first embodiment, when the switch of the CDAC is turned on and the CDAC starts to operate, during the period until the operation is completed, as Figure 8 shown, a constant current control potential is applied to the current control elements Q1 - Q4 to suppress the current.

[0068] In this case, the current control elements Q1 - Q4 act like resistors to suppress the current. As a result, no large current flows, but the settling time, that is, the settling time of the CDAC, becomes longer as Figure 9 shown.

[0069] When the current control elements Q1 - Q4 act like resistors after being turned on, as Figure 6 shown, the relationship between the current and time becomes a shape like a right triangle.

[0070] The problem to be solved in the second embodiment is to suppress the peak value of the noise current (noise voltage). Therefore, preferably, the relationship between the current and time becomes a shape like a rectangle, with the same area (charge amount) but a lower height (peak value of the current).

[0071] To solve the above problem, the A / D conversion circuit of the second embodiment includes Figure 10 the constant voltage generation circuit 11a, the falling voltage generation circuit 11b, the rising voltage generation circuit 11c, and the switch 13 shown. The constant voltage generation circuit 11a, the falling voltage generation circuit 11b, and the rising voltage generation circuit 11c are provided inside the current control unit 11. The switch 13 switches and selects the constant voltage generation circuit 11a, the falling voltage generation circuit 11b, and the rising voltage generation circuit 11c.

[0072] Next, the following situation will be described: For the noise current formed into a Figure 6 right triangle as shown, when Figure 11When the current control potential shown is applied to the current amount control element, the peak value of the noise current is reduced.

[0073] First, before time t11, the constant voltage generation circuit 11a applies the Figure 11 constant current control potential Va shown via the switch 13 to the current amount control element Q4. Next, at time t11, the falling voltage generation circuit 11b applies the current control potential Vb which is smaller than the current control potential Va via the switch 13 to the current amount control element Q4.

[0074] Next, at time t12, the rising voltage generation circuit 11c applies the current control potential Vc which is larger than the current control potential Va via the switch 13 to the current amount control element Q4.

[0075] Therefore, the relationship between the current and time becomes a rectangular shape, with the same area (electric charge amount), but the height (peak value of the current) is reduced.

[0076] Thus, as Figure 12 shown, the settling time in the case where the current control potential is constant without variable control becomes approximately the same as the settling time in the case where the current control potential is variably controlled. Therefore, it is possible to realize an A / D conversion circuit with a small noise current (noise voltage) without impairing the settling time of the CDAC and the conversion time of the A / D conversion circuit.

[0077] Industrial Applicability

[0078] The present invention can be applied to a CDAC.

[0079] Reference Numeral Explanation

[0080] 1: ADC overall control unit;

[0081] 10: CDAC;

[0082] 11: Current amount control unit;

[0083] 20: Comparator;

[0084] 30: Successive approximation data generator;

[0085] C1 - C4: Capacitors;

[0086] swA0 - swA4, swH1 - swH4, swL1 - swL4: Switches;

[0087] QH1 - QH4, QL1 - QL4: Current amount control elements;

[0088] VrefH, VrefL: Reference power supplies.

Claims

1. An A / D conversion circuit having a digital / analog converter that generates a comparison potential based on a potential, a digital value, and a reference power supply obtained by sampling / holding an input potential, the A / D conversion circuit comparing the comparison potential with a reference potential generated based on the reference power supply, converting the comparison potential into the digital value, and outputting the converted digital value to the digital / analog converter, wherein, the digital / analog converter includes: a plurality of bit circuits, in which capacitors, first switches, and series circuits are provided corresponding to a plurality of bits. One end of the capacitor outputs the comparison potential, and the capacitance value of the capacitor increases as it moves from the lower-order bit to the higher-order bit of the plurality of bits. The first switch applies the input potential to the other end of the capacitor. The series circuit is a series circuit of a second switch and a current control element between the other end of the capacitor and the reference power supply; and a current control unit that controls the amount of current flowing through the current control elements provided in each bit circuit of the plurality of bit circuits, when the second switches are sequentially turned on from the higher-order bit in each bit circuit according to the digital value, during the period when the second switch in any bit circuit where the noise current proportional to the charge flowing from the capacitor into the reference power supply reaches or exceeds the allowable value is turned on, the current control unit applies a current control potential to the current control element in the any bit circuit, thereby limiting the noise current to less than the allowable value.

2. The A / D conversion circuit according to claim 1, wherein, the current control unit does not limit the amount of current flowing through the current control element in the any bit circuit during the period when the second switch in a bit circuit other than the any bit circuit is turned on.

3. The A / D conversion circuit according to claim 1 or 2, wherein, the current control unit applies, as the current control potential, a potential that makes the relationship between the noise current and time rectangular to the current control element.

4. The A / D conversion circuit according to claim 3, wherein, as the current control potential, the current control unit first applies a current control potential smaller than a constant current control potential to the current control element, and then applies a current control potential larger than the constant current control potential to the current control element.

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