Focal Plane Infrared Sensor and Its Signal Readout Method

Abstract

The present application relates to a focal plane infrared sensor, comprising: an operational amplifier module, whose positive input terminal receives a first voltage reference signal; a blind pixel circuit, including a plurality of blind pixel resistors, the blind pixel circuit generating a dark field current according to the bias of the operational amplifier module; a sensitive pixel circuit, including a plurality of sensitive pixel resistors, the sensitive pixel circuit generating a thermal current according to the bias of the operational amplifier module; a subtraction circuit, whose input terminal is connected to the output terminal of the blind pixel circuit, and whose output terminal is connected to the output terminal of the sensitive pixel circuit, for subtracting the dark field current from the thermal current to generate a current difference, the current difference representing the current change generated by infrared irradiation on the sensitive pixel resistor; and an integration circuit, connected to the output terminal of the subtraction circuit, for integrating the current difference during an integration period. The present application also provides a signal reading method for the focal plane infrared sensor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a focal plane infrared sensor and a method for reading out its signals. Background Art

[0002] The infrared focal plane infrared sensor detector is the core component of a thermal imaging system and is crucial for detecting, identifying, and analyzing the infrared information of objects. It has a wide range of applications in various industries such as military, industry, transportation, security monitoring, meteorology, and medicine. Infrared focal plane infrared sensor detectors can be divided into cooled infrared focal plane infrared sensor detectors and uncooled infrared focal plane infrared sensor detectors. The advantage of cooled infrared focal plane infrared sensor detectors lies in their high sensitivity, ability to distinguish more subtle temperature differences, and longer detection distances, and they are mainly used in high-end military equipment. Uncooled infrared focal plane infrared sensor array detectors can operate at room temperature without a cooling device and have the advantages of light weight, small size, long lifespan, low cost, low power consumption, fast startup, and good stability, meeting the urgent needs of civilian infrared systems and some military infrared systems for long-wave infrared detectors, thus enabling this technology to develop rapidly and be widely applied.

[0003] Uncooled infrared focal plane infrared sensor detectors are mainly based on thermal sensors fabricated by microelectromechanical technology (MEMS) and can be roughly divided into several types such as thermopiles / thermocouples, pyroelectric, optomechanical, and microbolometers. Among them, the technology of microbolometers has developed very rapidly and occupies the largest market share. The core of an uncooled infrared detector based on a microbolometer is a CMOS (Complementary Metal Oxide Semiconductor) readout circuit and a MEMS (Microelectro Mechanical Systems) sensor. The CMOS readout circuit performs signal amplification and readout operations. The readout circuit is one of the key components of an uncooled infrared focal plane infrared sensor array (IRFPA) to preprocess (such as integrate, amplify, filter, sample / hold, etc.) the weak signals sensed by the infrared detector and perform parallel / serial conversion of the array signals. The MEMS sensor performs optoelectronic conversion operations. The microbolometer focal plane infrared sensor array (FPA) has high sensitivity. Its working principle is that the thermosensitive material absorbs the incident infrared radiation and then changes in temperature, thereby causing a change in its own resistance value. The magnitude of the infrared radiation signal is detected by measuring the change in its resistance value.

[0004] In recent years, the array scale of uncooled infrared focal plane infrared sensor detectors has been continuously increasing, the size of sensitive elements has been continuously decreasing, and there have been many new technological development trends in aspects such as the detector unit structure and its optimized design, readout circuit design, packaging form, etc. Summary of the Invention

[0005] This application provides a focal plane infrared sensor and its signal readout method. Through circuit structure design, its output voltage is stabilized to ensure the quality of thermal imaging.

[0006] This application provides a focal plane infrared sensor, including:

[0007] An operational amplifier module, including a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the operational amplifier module receives a first reference voltage signal;

[0008] A blind pixel circuit, including a plurality of blind pixel resistors. The blind pixel circuit is connected to the negative input terminal and the output terminal of the operational amplifier module. The blind pixel circuit generates a dark field current according to the bias of the operational amplifier module;

[0009] A sensitive element circuit, including a plurality of sensitive element resistors. The sensitive element circuit is connected to the negative input terminal and the output terminal of the operational amplifier module. The sensitive element circuit generates a thermal current according to the bias of the operational amplifier module; wherein, the blind pixel resistor and the sensitive element resistor have the same circuit connection structure;

[0010] A subtraction circuit, whose input terminal is connected to the output terminal of the blind pixel circuit, and whose output terminal is connected to the output terminal of the sensitive element circuit, for subtracting the dark field current from the thermal current to generate a current difference, and the current difference represents the current change generated by infrared irradiation on the sensitive element resistor; and

[0011] An integration circuit, connected to the output terminal of the subtraction circuit, for integrating the current difference during the integration period.

[0012] This application provides a signal readout method applied to the above-mentioned focal plane infrared sensor, including the following steps:

[0013] The blind pixel row selection signal of the blind pixel circuit is selected, the integration control switch is turned on, the first operational amplifier biases the blind pixel circuit, and the dark field current generated by the blind pixel circuit flows through the left half of the subtraction circuit, generating a bias voltage and mirroring it to the right half of the subtraction circuit;

[0014] The sensitive element row selection signals of the sensitive element circuit are sequentially selected. The sensitive element circuit is biased by the second operational amplifier to generate a thermal current. When the sensitive element resistor is irradiated by infrared light, its temperature rises, the resistance increases, and the thermal current decreases. The thermal current generated by the sensitive element resistor flows through the right half of the subtraction circuit; and

[0015] The dark current and the thermal current are subtracted in the subtraction circuit to generate a current difference, which is then input to the integration circuit.

[0016] In the focal plane infrared sensor and its signal readout method of the present application, since the blind element circuit and the sensitive element circuit have the same structure and voltage feedback is performed through an operational amplifier, the voltage used to generate current on the sensitive element resistor can be kept stable, greatly suppressing the influence of CMOS process fluctuations and temperature changes on the bias voltage of the blind element / sensitive element resistor, improving the consistency of image signal output, reducing fixed pattern noise, thereby improving the thermal imaging quality, avoiding the need for bias voltage calibration for each sensitive element resistor in terms of design principle, and greatly simplifying the system application; and since the blind element circuit and the sensitive element circuit are respectively connected to an operational amplifier, the dark current and the thermal current can be obtained simultaneously, greatly increasing the dynamic range or measurement range during temperature measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic circuit diagram of a focal plane infrared sensor in an embodiment of the prior art;

[0018] Figure 2 is a schematic circuit diagram of a focal plane infrared sensor in an embodiment of the present application;

[0019] Figure 3 is a working timing diagram of the signal readout of a focal plane infrared sensor in an embodiment of the present application; and

[0020] Figure 4 is a working timing diagram of the signal readout of a focal plane infrared sensor in another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0021] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.

[0022] As used in this application, the term "connection" is defined as follows. "Connection" is used to describe a direct connection or an indirect connection between two circuit elements. For example, two connected elements can be directly connected by a metal wire, or indirectly connected through intermediate circuit elements (such as a capacitor, a resistor, or the source or drain of a transistor).

[0023] As used in this application, the orientation or positional relationship indicated by the terms "upper", "lower", "left", "right", "row direction", "column direction", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the sake of clarity of the technical solution and convenience of description. Therefore, it should not be construed as a limitation to this application.

[0024] The embodiments of this application will be further described in detail below with reference to the drawings.

[0025] Figure 1 It is a schematic diagram of the circuit structure of a focal plane infrared sensor in an embodiment of the prior art. The focal plane infrared sensor includes a plurality of sensitive element resistors R0 - Rn, a blind element resistor Rb, a P-type MOS transistor M10, an N-type MOS transistor M20, a plurality of row selection switch MOS transistors (N-type MOS transistors) MR0 - MRn, an integrating amplifier A0, an integrating capacitor C10, and a reset switch M30. The gate of the P-type MOS transistor M1 receives a control signal GSK, and the gate of the N-type MOS transistor M20 receives a control signal GFID. The gates of the plurality of row selection switch MOS transistors MR0 - MRn respectively receive row selection control signals rs<0> to rs <n>, where n is any integer greater than or equal to 1. The first end of the blind pixel resistor Rb receives the voltage signal VSK, and the second end is connected to the source end of the P-type MOS transistor. The drain of the P-type MOS transistor M10 is connected to the drain of the N-type MOS transistor and the negative input end of the integrating amplifier. The positive input end of the integrating amplifier A0 receives a reference voltage signal Vref. The integrating capacitor C10 and the reset switch M30 are connected between the negative input end and the output end of the integrating amplifier A0. The source of the N-type MOS transistor M20 is connected to the drains of several row selection switch MOS transistors MR0 - MRn, and the sources of the row selection switch MOS transistors MR0 - MRn are respectively grounded through the sensitive element resistors R0 - Rn.

[0026] The sensitive element resistors R0 - Rn change with different infrared radiations received, causing the current Ia flowing through them to change. Ib is the current flowing through the blind pixel resistor Rb, and the integrating current Iint = Ib - Ia. The integrating voltage ΔVint = Iint × Tint / C10, where Tint is the integration time, and the output voltage is Vout = Vref - ΔVint. Therefore, the output voltage Vout changes with the change of the infrared radiation temperature.

[0027] Due to the inconsistent circuit connection structures of the blind pixel resistor and the sensitive element resistor in the circuit structure of the above focal plane infrared sensor, the voltage on the sensitive element resistor is unstable, vulnerable to CMOS process fluctuations and temperature changes, the integrating current is easily interfered, and the fixed pattern noise in the output signal is obvious, affecting the thermal imaging quality. Even if point-by-point correction is performed by adjusting the VSK voltage at the backend, the ideal state cannot be achieved, and at the same time, the system complexity and cost are greatly increased.

[0028] For the focal plane infrared sensor provided by this application, the blind pixel circuit and the sensitive element circuit have the same structure. Through voltage feedback by an operational amplifier, the voltage used to generate current on the sensitive element resistor can be kept stable, greatly suppressing the influence of CMOS process fluctuations and temperature changes on the bias voltage of the blind pixel / sensitive element resistor, improving the consistency of the image signal output, reducing the fixed pattern noise, thereby improving the thermal imaging quality, and avoiding bias voltage calibration for each sensitive element resistor in terms of the design principle, greatly simplifying the system application.

[0029] Figure 2 Schematic diagram of the circuit structure of a focal plane infrared sensor according to an embodiment of the present application. The focal plane infrared sensor includes a first operational amplifier AMP10, a second operational amplifier AMP20, a blind pixel circuit 100, a sensitive pixel circuit 200, a subtraction circuit 300, and an integration circuit 400. The first operational amplifier AMP10 includes a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the first operational amplifier AMP10 receives a first reference voltage signal Vref1. The second operational amplifier AMP20 includes a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the second operational amplifier AMP20 receives the first reference voltage signal Vref1.

[0030] The blind pixel circuit 100 includes a plurality of blind pixel resistors Rd0 to Rdn (n = 1 in this embodiment). The blind pixel circuit 100 is connected to the negative input terminal and the output terminal of the first operational amplifier AMP10. The blind pixel circuit 100 generates a dark field current Id according to the bias of the first operational amplifier AMP10. The dark field current Id includes the current induced by the blind pixel resistors Rd0 to Rdn when there is no infrared irradiation, or the current when the heat dissipates rapidly under infrared irradiation. The blind pixel resistors Rd0 to Rdn can block infrared irradiation through a light shielding structure, or avoid heat accumulation on the resistors through an accelerated heat dissipation structure.

[0031] The sensitive pixel circuit 200 includes a plurality of sensitive pixel resistors Ra0 to Ran. The sensitive pixel circuit 200 is connected to the negative input terminal and the output terminal of the second operational amplifier AMP20. The sensitive pixel circuit 200 generates a thermal current Ia according to the bias of the second operational amplifier AMP20. Among them, the blind pixel resistors Rd0 to Rdn and the sensitive pixel resistors Ra0 to Ran have the same circuit connection structure. The subtraction circuit 300 is connected to the output terminals of the blind pixel circuit 100 and the sensitive pixel circuit 200, and is used to subtract the dark field current Id from the thermal current Ia to generate a current difference, and the current difference represents the current change generated by infrared irradiation on the sensitive pixel resistor. The integration circuit 400 is connected to the subtraction circuit 300, and is used to integrate the current difference during the integration period.

[0032] In other embodiments, only one operational amplifier can be used to provide bias for the blind pixel circuit 100 and the sensitive pixel circuit 200, that is, the second operational amplifier AMP20 is omitted, and only the first operational amplifier AMP10 is used. The blind pixel circuit 100 and the sensitive pixel circuit 200 are both connected to the negative input terminal and the output terminal of the first operational amplifier AMP10, and the first operational amplifier AMP10 provides bias for the blind pixel circuit 100 and the sensitive pixel circuit 200 to generate the dark field current Id or the thermal current Ia.

[0033] In one embodiment, the blind pixel circuit 100 further includes the first switching transistor Ms1, the second switching transistor Ms2, and the first transistor M1. The first ends of the blind pixel resistors Rd0 to Rdn are grounded, and their second ends are connected to the negative input terminal of the first operational amplifier AMP10 through the first switching transistor Ms1 and are also connected to the first end of the first transistor M1. The gate of the first transistor M1 is connected to the output terminal of the first operational amplifier AMP10. The second end of the first transistor M1 is connected to the subtraction circuit 300 through a second switching transistor Ms2. The gates of the first switching transistor Ms1 and the second switching transistor Ms2 receive the blind pixel row selection signals rsd<0> to rsd <n>Control to make the blind element resistors Rd0 to Rdn work or not work. In one embodiment, the first switching transistor Ms1, the second switching transistor Ms2, and the first transistor M1 are NMOS transistors.

[0034] In one embodiment, the sensitive element circuit 200 further includes a third switching transistor Ms3, a fourth switching transistor Ms4, and a second transistor M2. The first ends of the sensitive element resistors Ra0 to Ran are grounded, and their second ends are connected to the negative input terminal of the second operational amplifier AMP20 through the third switching transistor Ms3 and are also connected to the first end of the second transistor M2. The gate of the second transistor M2 is connected to the output terminal of the second operational amplifier AMP20. The second end of the second transistor M2 is connected to the subtraction circuit 300 through the fourth switching transistor Ms4. The gates of the third switching transistor Ms3 and the fourth switching transistor Ms4 are controlled by the sensitive element row selection signals rsa<0> to rsa <n>Control to make the sensitive element resistors Ra0 to Ran work or not work. In one embodiment, the third switching transistor Ms3, the fourth switching transistor Ms4, and the second transistor M2 are NMOS transistors.

[0035] In one embodiment, the subtraction circuit 300 is a mirror bias circuit, including a third transistor M3, a fourth transistor M4, a fifth transistor M5, and a sixth transistor M6. The first ends of the third transistor M3 and the fourth transistor M4 are connected to a voltage source VDD. The second ends of the third transistor M3 and the fourth transistor M4 are respectively connected to the first ends of the fifth transistor M5 and the sixth transistor M6. The gates of the third transistor M3 and the fourth transistor M4 are interconnected and connected to the second end of the fifth transistor M5. The gates of the fifth transistor M5 and the sixth transistor M6 are interconnected. The second end of the fifth transistor M5 is connected to the output end of the blind element circuit 100. The second end of the sixth transistor M6 is connected to the output end of the sensitive element circuit 200. In one embodiment, the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are PMOS transistors. The transistor sizes of the third transistor M3 and the fourth transistor M4 are the same, but the number is not necessarily the same, that is, the third transistor M3 and the fourth transistor M4 may be multiple; the transistor sizes of the fifth transistor M5 and the sixth transistor M6 are the same, but the number is not necessarily the same, that is, the fifth transistor M5 and the sixth transistor M6 may also be multiple; wherein, the quantity ratio relationship between the fifth transistor M5 and the sixth transistor M6 is equal to the quantity ratio relationship between the third transistor M3 and the fourth transistor M4, and this quantity ratio relationship is equal to the number of the blind element resistors Rd0 to Rdn. In this embodiment, the number of the blind element resistors Rd0 to Rdn is 2. In other embodiments, the number of the blind element resistors Rd0 to Rdn may be multiple.

[0036] In one embodiment, the integrating circuit 400 has a capacitive feedback transimpedance amplifier (CTIA) structure, and includes a transimpedance amplifier A1, an integrating capacitor C1, and an integrating reset switch Mr1. The first terminal of the integrating capacitor C1 is connected to the negative input terminal of the transimpedance amplifier A1, and the second terminal of the integrating capacitor C1 is connected to the output terminal of the transimpedance amplifier A1. The positive input terminal of the transimpedance amplifier A1 receives a second reference voltage signal Vref2. The first terminal of the integrating reset switch Mr1 is connected to the negative input terminal of the transimpedance amplifier A1, and the second terminal of the integrating reset switch Mr1 is connected to the output terminal of the transimpedance amplifier A1. During auto-zeroing, an integrating reset signal az is received, and the integrating capacitor C1 is reset by controlling the integrating reset switch Mr1. In one embodiment, the capacitance value of the integrating capacitor C1 is adjustable, and the integrating gain can be adjusted by setting different capacitance values of the integrating capacitor C1. In one embodiment, the integrating circuit 400 further includes an integrating control switch S1 connected between the subtraction circuit 300 and the negative input terminal of the transimpedance amplifier A1 for controlling the stop of integration. The integrating control switch S1 can be a transistor switch, such as an NMOS transistor switch, a PMOS transistor switch, or a CMOS transistor switch. In one embodiment, the integrating circuit 400 further includes a sampling capacitor C2 connected between the negative input terminal of the transimpedance amplifier A1 and the ground.

[0037] This application Figure 2 The circuit structure of the focal plane infrared sensor provided in this application only shows the simplified circuit structure of one column of pixels. In an actual product, the readout circuits composed of the blind pixel circuit 100, the sensitive pixel circuit 200, the subtraction circuit 300, and the integrating circuit 400 all exist in an array form. The signals of each column of sensitive pixels are read out through a readout circuit to obtain a complete thermal imaging image.

[0038] Figure 3 and Figure 4 are the signal readout working timing diagrams of the focal plane infrared sensors in two embodiments provided in this application. The signal readout method of the focal plane infrared sensor provided in this application includes the following steps:

[0039] The blind pixel row selection signals rsd<0> to rsd of the blind pixel circuit 100 <n>When selected, the integration control switch S1 is turned on, and the first operational amplifier AMP10 biases the blind pixel circuit 100. The dark field current Id generated by the blind pixel circuit 100 (the current value of the dark field current Id is determined by dividing the first reference voltage signal Vref1 by the resistance values of the blind pixel resistors Rd0 to Rdn respectively) flows through the left half of the subtraction circuit 300, generates a bias and is mirrored to the right half of the subtraction circuit 300;

[0040] The sensitive element row select signals rsa<0> to rsa of the blind pixel circuit 100 <n>Selected sequentially, the sensitive element circuit 200 is biased by the second operational amplifier AMP20 to generate a thermal current Ia (the current value of the thermal current Ia is determined by dividing the first reference voltage signal Vref1 by the resistance values of the sensitive element resistors Ra0 to Ran respectively). When the sensitive element resistors Ra0 to Ran are irradiated by infrared rays, their temperatures rise, their resistances increase, and the thermal current Ia decreases. The thermal current Ia generated by the sensitive element resistors Ra0 to Ran flows through the right half of the subtraction circuit 300; and

[0041] The dark current Id and the thermal current Ia are subtracted in the subtraction circuit 300 to generate a current difference, which represents the current change generated by the infrared irradiation on the sensitive element resistor and is input to the negative input terminal of the transimpedance amplifier A1.

[0042] Specifically, during the automatic zeroing or reset signal quantization period (T1), the integration reset signal az is at a high level, the integration reset switch Mr1 is turned on, and the current difference directly flows into the output terminal of the transimpedance amplifier A1. The voltage output signal amp_out at the output terminal of the transimpedance amplifier A1 is equal to the second reference voltage signal Vref2 at the positive input terminal, and the second reference voltage signal Vref2 represents the reset signal. Among them, in the embodiment provided in the present application Figure 3 In the first automatic zeroing cycle, that is, at the same time, the reset signal is quantized (according to the timing of the reference signal ramp / count_en) to obtain a digital reset signal. In the embodiment provided in the present application Figure 4 In the second automatic zeroing cycle, the reset signal is quantized (according to the timing of the reference signal ramp / count_en) to obtain a digital reset signal.

[0043] After the automatic zeroing or reset signal quantization period (T1), the integration period (T2) is entered. The integration reset signal az goes low, the integration reset switch Mr1 is turned off, and the current difference flowing out of the subtraction circuit 300 is integrated on the integration capacitor C1, and the voltage output signal amp_out output at the output terminal of the transimpedance amplifier A1 gradually decreases. During the integration process, the relationship between the integration voltage, the integration current, the integration capacitor, and the integration time is the same as the existing technology calculation method, that is, the integration voltage is equal to the integration current multiplied by the integration time and then divided by the integration capacitor, which will not be elaborated here.

[0044] After the integration period (T2), the image signal quantization period (T3) is entered. The integration control switch S1 is turned off, and the integration of the integration circuit 400 stops. At this time, the voltage output signal amp_out at the output end of the transimpedance amplifier A1 is the image signal, and the image signal is quantized (refer to the timing of the reference signal ramp / count_en) to obtain a digital image signal. Then, the automatic zero-clearing / reset signal quantization period is entered again.

[0045] In the embodiments provided in the present application Figure 4 Since there is no long integration time interval between the quantization of the image signal and the reset signal, and the two sampling time intervals are short, low-frequency noise can be better suppressed. Further, the digital reset signal and the digital image signal are subtracted by a backend circuit (not shown in the figure) to obtain an effective output quantization digital signal, and the final effective output quantization digital signal is proportional to the temperature change sensed by the sensitive element circuit 200.

[0046] The blind pixel circuit and the sensitive element circuit of the focal plane infrared sensor and its signal reading method in the present application have the same structure, and voltage feedback is performed through an operational amplifier, so that the voltage for generating current on the sensitive element resistor can be kept stable, greatly suppressing the influence of CMOS process fluctuations and temperature changes on the bias voltage of the blind pixel / sensitive element resistor, improving the consistency of image signal output, reducing fixed pattern noise, thereby improving the thermal imaging quality. From the design principle, the bias calibration of each sensitive element resistor is avoided, greatly simplifying the system application. And since the blind pixel circuit and the sensitive element circuit are respectively connected to an operational amplifier, the dark field current and the thermal current can be obtained simultaneously, greatly increasing the dynamic range or measurement range during temperature measurement.

[0047] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0048] It should be noted that in this text, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, article or device including such element. In addition, components, features, elements with the same name in different embodiments of the present application may have the same meaning or may have different meanings, and their specific meanings need to be determined based on their explanations in the specific embodiments or further in combination with the context of the specific embodiments.

[0049] It should be understood that although the steps in the flowcharts in the embodiments of the present application are shown sequentially according to the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless there is a clear indication in this text, the execution of these steps has no strict order restriction and can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0050] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements or improvements made within the spirit and principle of the present application shall be included within the protection scope of the present application.< / n> < / n> < / n> < / n> < / n>

Claims

1. A focal plane infrared sensor, characterized in that, Comprising: An operational amplifier module, including a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the operational amplifier module receives a first reference voltage signal; A blind pixel circuit, including a plurality of blind pixel resistors, the blind pixel circuit is connected to the negative input terminal and the output terminal of the operational amplifier module, and the blind pixel circuit generates a dark field current according to the bias of the operational amplifier module; A sensitive pixel circuit, including a plurality of sensitive pixel resistors, the sensitive pixel circuit is connected to the negative input terminal and the output terminal of the operational amplifier module, and the sensitive pixel circuit generates a thermal current according to the bias of the operational amplifier module; wherein, the blind pixel resistors and the sensitive pixel resistors have the same circuit connection structure; A subtraction circuit, whose input terminal is connected to the output terminal of the blind pixel circuit, and whose output terminal is connected to the output terminal of the sensitive pixel circuit, for subtracting the dark field current from the thermal current to generate a current difference, and the current difference represents the current change generated by infrared irradiation on the sensitive pixel resistors; and An integration circuit, connected to the output terminal of the subtraction circuit, for integrating the current difference during an integration period.

2. The focal plane infrared sensor according to claim 1, wherein, The operational amplifier module includes: A first operational amplifier, including a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the first operational amplifier receives a first reference voltage signal; the blind pixel circuit is connected to the negative input terminal and the output terminal of the first operational amplifier, and the blind pixel circuit generates the dark field current according to the bias of the first operational amplifier; and A second operational amplifier, including a positive input terminal, a negative input terminal, and an output terminal, wherein the positive input terminal of the second operational amplifier receives the first reference voltage signal; the sensitive pixel circuit is connected to the negative input terminal and the output terminal of the second operational amplifier, and the sensitive pixel circuit generates the thermal current according to the bias of the second operational amplifier.

3. The focal plane infrared sensor according to claim 2, wherein The first end of the blind pixel resistor is grounded, its second end is connected to the negative input terminal of the first operational amplifier through a first switching transistor, and is also connected to the first end of a first transistor, the gate of the first transistor is connected to the output terminal of the first operational amplifier, the second end of the first transistor is connected to the subtraction circuit through a second switching transistor, and the gates of the first switching transistor and the second switching transistor receive a blind pixel row selection signal for control to enable the blind pixel resistor to work or not work.

4. The focal plane infrared sensor according to claim 2, wherein, The first end of the sensitive pixel resistor is grounded, its second end is connected to the negative input terminal of the second operational amplifier through a third switching transistor, and is also connected to the first end of a second transistor, the gate of the second transistor is connected to the output terminal of the second operational amplifier, the second end of the second transistor is connected to the subtraction circuit through a fourth switching transistor, and the gates of the third switching transistor and the fourth switching transistor are controlled by a sensitive pixel row selection signal to enable the sensitive pixel resistor to work or not work.

5. The focal plane infrared sensor according to claim 1, characterized in that, The subtraction circuit is a mirror bias circuit, including a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first ends of the third transistor and the fourth transistor are connected to a voltage source. The second ends of the third transistor and the fourth transistor are respectively connected to the first ends of the fifth transistor and the sixth transistor. The gates of the third transistor and the fourth transistor are interconnected and connected to the second end of the fifth transistor. The gates of the fifth transistor and the sixth transistor are interconnected. The second end of the fifth transistor is connected to the output end of the blind pixel circuit. The second end of the sixth transistor is connected to the output end of the sensitive pixel circuit.

6. The focal plane infrared sensor according to claim 5, characterized in that, The third transistor, the fourth transistor, the fifth transistor, and the sixth transistor respectively include a plurality of single transistors connected in parallel. The single transistors in the third transistor and the fourth transistor have the same size. The single transistors in the fifth transistor and the sixth transistor have the same size. And the quantity ratio relationship of the single transistors in the fifth transistor and the sixth transistor is equal to the quantity ratio relationship of the single transistors in the third transistor and the fourth transistor.

7. The focal plane infrared sensor according to claim 6, characterized in that, The quantity ratio relationship is equal to the number of the plurality of blind pixel resistors.

8. The focal plane infrared sensor according to claim 1, characterized in that, The integration circuit is a capacitive feedback transimpedance amplifier (CTIA) structure, including a transimpedance amplifier, an integration capacitor, and an integration reset switch. The first end of the integration capacitor is connected to the negative input end of the transimpedance amplifier. The second end of the integration capacitor is connected to the output end of the transimpedance amplifier. The positive input end of the transimpedance amplifier receives a second reference voltage signal. The first end of the integration reset switch is connected to the negative input end of the transimpedance amplifier. The second end of the integration reset switch is connected to the output end of the transimpedance amplifier. The integration reset switch is used to receive an integration reset signal during auto-zeroing to reset the integration capacitor.

9. The focal plane infrared sensor according to claim 8, wherein, The integration circuit further includes an integration control switch, connected between the subtraction circuit and the negative input end of the transimpedance amplifier, for controlling the stop of integration.

10. The focal plane infrared sensor according to claim 8, wherein, The integration circuit further includes a sampling capacitor, connected between the negative input end of the transimpedance amplifier and the ground.

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