Data reading and writing method and device, and soft error processing system

Abstract

A data reading method and device, a data writing method and device, and a soft error handling system. The data reading method includes: using an error checking method to perform a first check on m bits of data read from a target row in n rows of a storage array to obtain a first check result; in response to the first check result indicating that an error occurring in the target row cannot be fully corrected, using a parity check method to perform a second check on the data in each of the m columns read from the storage array to obtain a parity check result; combining the first check result and the parity check result to obtain a second check result corresponding to the target row; and using the second check result as the read result. The data reading method can promptly correct multi-bit soft errors occurring in a data storage device with minimal hardware overhead and latency overhead. The number of correction bits that can be corrected by the data reading method is greater than the maximum number of error correction bits that can be corrected by the error checking method.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a data reading method, a data writing method, a data reading device, a data writing device, and a soft error processing system. Background Art

[0002] Whether a chip can operate continuously and stably depends on the stability of each component in the chip system. Static Random Access Memory (SRAM) is a component used extensively in current chip designs. As long as the power is on, the data stored in this memory can be permanently retained. SRAM is typically used to store critical data, reduce latency, and improve chip performance. For example, SRAM can be used as a cache in a CPU (central processing unit) or GPU (graphics processing unit), a data buffer on the data path, and a first-in-first-out (FIFO) queue. Compared to dynamic random-access memory (DRAM), SRAM has the characteristics of low latency and high speed, and does not require refresh, which helps improve chip performance and reduce power consumption when accessing data. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a data reading method, which is applied to a data storage device, wherein the data storage device stores n data and each data has a data width of m bits, the n data are arranged in sequence to form an n*m-bit data array, and the data array is correspondingly stored as a storage array in the data storage device. The data reading method includes: using an error checking method, performing a first check on m bits of data read from a target row in n rows of the storage array to obtain a first check result; in response to the first check result indicating that an error occurring in the target row cannot be completely corrected, using a parity check method, performing a second check on data in each of m columns read from the storage array to obtain a parity check result; combining the first check result and the parity check result to obtain a second check result corresponding to the target row, wherein the number of correction bits in the second check result is greater than the maximum number of error correction bits that can be corrected by the error checking method; and using the second check result as a reading result, wherein m and n are both positive integers.

[0004] For example, in the data reading method provided in at least one embodiment of the present disclosure, the data storage device provides a first check array for the storage array, the first check array includes n error check storage rows corresponding one-to-one to the n data, each of the n error check storage rows includes p error check bits, and the p error check bits in the i-th row of the n error check storage rows are used to store error check data corresponding to the i-th row of the data array; the data storage device provides a parity check storage row for the storage array and the first check array, wherein the parity check storage row includes m bits corresponding one-to-one to m columns of the storage array and p bits corresponding one-to-one to p columns of the first check array, the m bits and the p bits are respectively used to store a reference parity check vector having m+p bits corresponding to the m columns of the data array and the p columns of the first check array, wherein p and i are both positive integers.

[0005] For example, in the data reading method provided in at least one embodiment of the present disclosure, an error checking method is used to perform a first check on m bits of data read from a target row in n rows of the storage array to obtain a first check result, including: reading m bits of data stored in the target row and p bits of error checking data corresponding to the target row to obtain a first data row; and performing the first check on the first data row using the error checking method to obtain the first check result.

[0006] For example, in the data reading method provided in at least one embodiment of the present disclosure, a parity check method is used to perform a second check on the data of each of the m columns read from the storage array to obtain a parity check result, including: using the parity check method, performing a parity check operation on the data bits of each of the m columns read from the storage array and the p columns read from the first check array to obtain a detection parity check vector having m+p bits; comparing the detection parity check vector with the reference parity check vector bit by bit to determine multiple difference bits between the detection parity check vector and the reference parity check vector; and obtaining the parity check result based on the multiple difference bits.

[0007] For example, in the data reading method provided in at least one embodiment of the present disclosure, comparing the detection parity check vector with the reference parity check vector bit by bit includes: performing a bitwise XOR calculation on the detection parity check vector and the reference parity check vector.

[0008] For example, in the data reading method provided by at least one embodiment of the present disclosure, in response to the first verification result indicating that the error occurring in the target row cannot be completely corrected, the first verification result includes the first data row, and the first verification result and the parity check result are combined to obtain a second verification result corresponding to the target row, including: determining, based on the parity check result, e potential error bits in the first data row where errors exist, wherein the positions of the e potential error bits are the positions of the multiple difference bits, and e is an integer; in response to e being greater than a-1 and less than or equal to a preset correction threshold, performing a trial and error combination test in combination with the e potential error bits, the error checking method and the first data row to obtain the second verification result, wherein a is the maximum number of error detection bits that the error checking method can detect.

[0009] For example, in the data reading method provided in at least one embodiment of the present disclosure, a trial-and-error combination test is performed in combination with the e potential error bits, the error checking method, and the first data row, including: determining at least one correction combination consisting of each a potential error bits among the e potential error bits, and performing the trial-and-error combination test on the at least one correction combination; wherein the trial-and-error combination test includes sequentially performing a trial-and-error test on each selected correction combination, the trial-and-error test including: flipping a data bits in the first data row corresponding to the a potential error bits included in the selected correction combination to obtain an intermediate test data row corresponding to the first data row; performing the first check on the intermediate test data row using the error checking method, and in response to at most a-1 bits in the intermediate test data row having errors, processing the intermediate test data row to obtain the second check result, and stopping the trial-and-error combination test; and in response to a bits still having errors in the intermediate test data row, performing the trial-and-error test on the next correction combination.

[0010] For example, in the data reading method provided in at least one embodiment of the present disclosure, the at least one correction combination performs the trial-and-error test in order from small to large data bit distance, and the data bit distance of each correction combination is determined according to the distance between a potential error bits included in each correction combination.

[0011] For example, in the data reading method provided in at least one embodiment of the present disclosure, in response to the presence of errors in at most a-1 bits of the intermediate test data row, the intermediate test data row is processed to obtain the second verification result, and the trial-and-error combination test is stopped, including: in response to the presence of no errors in the intermediate test data row, the intermediate test data row is used as the second verification result, and the trial-and-error combination test is stopped; in response to the presence of an error in bit b in the intermediate test data row, the b bit is corrected using the error correction method, the correction result is used as the second verification result, and the trial-and-error combination test is stopped, wherein b is a positive integer and is less than or equal to a-1.

[0012] For example, in the data reading method provided in at least one embodiment of the present disclosure, the first check result and the parity check result are combined to obtain a second check result corresponding to the target row, including: using the parity check result to determine multiple potential error bits in the m bits of data read from the target row; in response to the number of the multiple potential error bits being equal to the maximum number of error detection bits a that can be detected by the error checking method, processing the m bits of the data read from the target row according to the multiple potential error bits to obtain the second check result.

[0013] For example, the data reading method provided by at least one embodiment of the present disclosure also includes: in response to the number of the multiple potential error bits being within a preset correction range, constructing at least one correction combination based on the multiple potential error bits, wherein each correction combination consists of a selected a potential error bits; performing a trial and error combination test on the at least one correction combination; wherein the trial and error combination test includes performing a trial and error test on each selected correction combination in sequence, and the trial and error test includes: flipping a data bits corresponding to the a potential error bits included in the selected correction combination among the m bits of data read from the target row to obtain an intermediate test data row, using the error checking method, performing the first check on the intermediate test data row to obtain a first intermediate check result, in response to the first intermediate check result being a check pass, obtaining the second check result based on the first intermediate correction result, and stopping the trial and error combination test, and in response to the first intermediate check result being a check fail, performing the trial and error test on the next correction combination.

[0014] For example, in the data reading method provided in at least one embodiment of the present disclosure, the error checking method is a single error correction and double error detection method.

[0015] For example, the data reading method provided by at least one embodiment of the present disclosure further includes: in response to the first verification result indicating that the error occurring in the target row can be completely corrected, using the first verification result as the reading result.

[0016] At least one embodiment of the present disclosure provides a data writing method for writing data to a data memory, wherein the data memory is configured to store n data, and the data width of each of the n data is m bits, and the n data are arranged in sequence to form an n*m-bit data array, and the n*m-bit data array is correspondingly stored as an n*m-bit storage array in the data memory. The data writing method includes: generating first check data for target data of a target row in the n rows to be written to the storage array based on an error checking method, wherein the first check data is used to check the target row using the error checking method; and obtaining a reference parity check vector based on the target data using a parity check method, wherein the reference parity check vector is used to perform a parity check on each of the m columns.

[0017] For example, in the data writing method provided in at least one embodiment of the present disclosure, the data storage device provides a first check array for the storage array, the first check array includes n error check storage rows corresponding one-to-one to the n data, and the data storage device provides a parity storage row for the storage array and the first check array. The data writing method further includes: writing the target data into a target row in the storage array; writing the first check data into an error check storage row corresponding to the target row in the first check array; and writing the reference parity check vector into the parity storage row.

[0018] For example, in the data writing method provided in at least one embodiment of the present disclosure, a reference parity check vector is obtained based on the target data using a parity check method, including: reading a current reference check vector stored in the parity check storage row, and performing a bitwise XOR operation on the current reference check vector, the target data, and the first check data to obtain the reference parity check vector.

[0019] At least one embodiment of the present disclosure provides a soft error handling system, including a data memory and a control circuit, wherein the data memory stores n data, each data having a data width of m bits, the n data being arranged in sequence to form an n*m-bit data array, and the data array being correspondingly stored as a storage array in the data memory, the control circuit including a controller and an error checker, the error checker being configured to, using an error checking method, perform a first check on m bits of data read from a target row of n rows of the storage array to obtain a first check result; the controller being configured to: in response to the first check result indicating that an error occurring in the target row cannot be completely corrected, perform a second check on data in each of m columns read from the storage array using a parity check method to obtain a parity check result; combine the first check result and the parity check result to obtain a second check result corresponding to the target row, wherein the number of correction bits in the second check result is greater than the maximum number of error correction bits that can be corrected by the error checking method; and output the second check result as a read result, wherein m and n are both positive integers.

[0020] For example, in a soft error handling system provided in at least one embodiment of the present disclosure, the data memory provides a first check array for the storage array, the first check array includes n error check storage rows corresponding one-to-one to the n data, each of the n error check storage rows includes p error check bits, and the p error check bits in the i-th row of the n error check storage rows are used to store error check data corresponding to the i-th row of the data array. The data memory provides a parity check storage row for the storage array and the first check array, wherein the parity check storage row includes m bits corresponding one-to-one to m columns of the storage array and p bits corresponding one-to-one to p columns of the first check array, and the m bits and the p bits are used to store reference parity check vectors having m+p bits corresponding to the m columns of the data array and the p columns of the first check array, respectively, wherein p and i are both positive integers.

[0021] For example, in the soft error handling system provided by at least one embodiment of the present disclosure, the error checker performs a first check on m bits of data read from a target row in n rows of the storage array using an error checking method, and when obtaining a first check result, the system includes performing the following steps: receiving m bits of data stored in the target row read from the storage array and p bits of error check data corresponding to the target row to obtain a first data row; using the error checking method, determining whether there are errors in a bits among the m+p bits of the first data row, where a is the maximum number of error detection bits that can be detected by the error checking method; in response to an error in a bit in the first data row, outputting the first data row to the controller, wherein the first check result includes the first data row; in response to an error in at most a-1 bits in the first data row, performing correction processing on the first data row, and outputting the correction result to the controller, wherein the first check result includes the correction result.

[0022] For example, in the soft error handling system provided by at least one embodiment of the present disclosure, the controller performs a second check on the data of each of the m columns read from the storage array using a parity check method, and when obtaining a parity check result, the following operations are performed: using the parity check method, a parity check operation is performed on the data bits of each of the m columns read from the storage array and the p columns read from the first check array to obtain a detection parity check vector with m+p bits; reading the reference parity check vector from the parity check storage row; comparing the detection parity check vector with the reference parity check vector bit by bit to determine multiple difference bits between the detection parity check vector and the reference parity check vector; and obtaining the parity check result based on the multiple difference bits.

[0023] For example, in the soft error handling system provided by at least one embodiment of the present disclosure, when the controller executes the combination of the first check result and the parity check result to obtain the second check result corresponding to the target row, the following operations are performed: based on the parity check result, determining e potential error bits in the first data row, wherein the positions of the e potential error bits are the positions of the multiple difference bits, and e is an integer; in response to e being greater than a-1 and less than or equal to a preset correction threshold, performing a trial and error combination test in combination with the e potential error bits, the error checking method and the first data row to obtain the second check result.

[0024] For example, in the soft error handling system provided by at least one embodiment of the present disclosure, when the controller performs a trial-and-error combination test in combination with the e potential error bits, the error checking method, and the first data row to obtain the second check result, the controller includes performing the following steps: determining at least one correction combination consisting of each a potential error bits among the e potential error bits, and performing the trial-and-error combination test on the at least one correction combination; wherein the trial-and-error combination test includes sequentially performing a trial-and-error test on each selected correction combination, and the trial-and-error test includes: flipping a data bits in the first data row corresponding to the a potential error bits included in the selected correction combination to obtain an intermediate test data row corresponding to the first data row; sending the intermediate test data row to the error checker; in response to receiving a first flag signal sent by the error checker, stopping the trial-and-error combination test, outputting the second check result sent by the error checker, and in response to receiving a second flag signal sent by the error checker, performing the trial-and-error test on the next correction combination.

[0025] For example, in the soft error handling system provided by at least one embodiment of the present disclosure, the error checker is further configured to: perform the first check on the intermediate test data row received from the controller using the error checking method; in response to there being no error in the intermediate test data row, use the intermediate test data row as the second check result, and send the second check result and the first flag signal to the controller; in response to there being an error in bit b in the intermediate test data row, correct the bit b using the error checking method, use the correction result as the second check result, and send the second check result and the first flag signal to the controller, wherein b is a positive integer and is less than or equal to a-1; in response to there still being an error in bit a in the intermediate test data row, output the second flag signal to the controller.

[0026] For example, in the soft error handling system provided by at least one embodiment of the present disclosure, the control circuit further includes an error check code generator, which is configured to generate first check data for target data of a target row to be written into n rows of the storage array based on an error check method, wherein the first check data is used to check the target row using the error check method; the controller is further configured to obtain a reference parity check vector using a parity check method according to the target data, wherein the reference parity check vector is used to perform parity check on each of the m columns.

[0027] For example, in the soft error handling system provided in at least one embodiment of the present disclosure, the control circuit further includes an enable selector, an address selector, a read data selector, and a write data selector. The enable selector is configured to, under the control of the controller, input an enable signal determined based on a data write request or a read request, or an enable signal generated by the controller, to the enable port of the data storage; the address selector is configured to, under the control of the controller, input an address determined based on a data write request or a read request, or an address generated by the controller, to the address port of the data storage; the read data selector is configured to, under the control of the controller, input data received from the read data port of the data storage, or an intermediate test data row generated by the controller, to the error checker; the write data selector is configured to, under the control of the controller, input the target data and the first check data, or the reference parity check vector generated by the controller, to the write data port of the data storage.

[0028] At least one embodiment of the present disclosure provides a data reading device, applied to a data storage device, wherein the data storage device stores n data, each data having a data width of m bits, and the n data are sequentially arranged to form an n*m-bit data array, and the data array is correspondingly stored as a storage array in the data storage device. The data reading device includes: a first check unit configured to perform a first check on m bits of data read from a target row of n rows of the storage array using an error checking method to obtain a first check result; a second check unit configured to perform a second check on data in each of m columns read from the storage array using a parity check method in response to an indication that an error occurring in the target row cannot be completely corrected by the first check result to obtain a parity check result; a correction unit configured to combine the first check result and the parity check result to obtain a second check result corresponding to the target row, wherein the number of correction bits in the second check result is greater than the maximum number of error correction bits that can be corrected by the error checking method; and an output unit configured to output the second check result as a read result, wherein m and n are both positive integers.

[0029] At least one embodiment of the present disclosure provides a data writing device for writing data to a data memory, wherein the memory is configured to store n data, and the data width of each of the n data is m bits, the n data are arranged in sequence to form an n*m-bit data array, and the n*m-bit data array is correspondingly stored as an n*m-bit storage array in the data memory, the data writing device includes: a first check data generation unit, configured to generate first check data for data of a target row in the n rows to be written to the storage array based on an error checking method, wherein the first check data is used to check the target row using the error checking method; a second check data generation unit, configured to obtain a reference parity check vector using a parity check method based on the data to be written to the target row, wherein the reference parity check vector is used to perform a parity check on each of the m columns. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0031] Figure 1 It is a schematic structural diagram of a multi-core chip system;

[0032] Figure 2A This is a circuit logic diagram of a static random access memory;

[0033] Figure 2B Schematic diagram of an equivalent storage array of a static random access memory;

[0034] Figure 3 The process flow after a soft error is detected in a static random access memory is shown;

[0035] Figures 4A-4D Schematic diagram of the storage structure of static random access memory;

[0036] Figure 5 A schematic flow chart of a data reading method provided in at least one embodiment of the present disclosure;

[0037] Figure 6 A schematic structural diagram of a data storage device provided for at least one embodiment of the present disclosure;

[0038] Figure 7 A schematic diagram of potential misalignment provided for at least one embodiment of the present disclosure;

[0039] Figure 8 A flowchart of a data reading and writing method provided by at least one embodiment of the present disclosure;

[0040] Figure 9 A schematic flow chart of a data writing method provided in at least one embodiment of the present disclosure;

[0041] Figure 10 A flowchart of a data writing method provided by at least one embodiment of the present disclosure;

[0042] Figure 11 A schematic structural diagram of a soft error handling system provided in at least one embodiment of the present disclosure;

[0043] Figure 12 A structural diagram of a soft error system provided by at least one embodiment of the present disclosure;

[0044] Figures 13A-13E A schematic diagram of soft errors provided for at least one embodiment of the present disclosure;

[0045] Figure 14 A schematic block diagram of a data reading device provided in at least one embodiment of the present disclosure;

[0046] Figure 15 A schematic block diagram of a data writing device provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0048] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0049] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and components.

[0050] Figure 1 This is a schematic structural diagram of a multi-core chip system. Figure 1 As shown, the system is a typical 4-core system-on-chip, consisting of 4 cores, three-level caches (L1 cache, L2 cache, and L3 cache) corresponding to each core, an on-chip interconnect network, dynamic random access memory, and other intellectual property cores (Intellectual Property Core). I-L1$ is each core's private instruction L1 cache, D-L1$ is each core's private data L1 cache, every two cores share an L2 cache, and all four cores share an L3 cache. The L3 cache and other intellectual property cores (e.g., direct memory access / video / display, etc.) access the dynamic random access memory through the on-chip interconnect network.

[0051] In this typical multi-core system-on-chip, the L1 cache, L2 cache, and L3 cache contain a large amount of static random access memory. In addition, there are also a large number of data caches composed of static random access memory inside the core, other intellectual property cores, and the on-chip interconnect network.

[0052] Figure 2A This is the circuit logic diagram of static random access memory. Figure 2B For Figure 2A Schematic diagram of the storage array of an equivalent static random access memory.

[0053] like Figure 2A As shown in the figure, the static random access memory circuit mainly includes row address decoding, column address decoding, bit line selection, column multiplexer and storage array. The read and write data width of the static random access memory is m bits (bits), the read and write address width is N bits, where the column address width is k bits and the row address width is Nk bits. After decoding the row address, a row in the storage array is selected through the word line. A row in the storage array contains 2 k After decoding the column address, the column strobe address is obtained, and the row selected by the word line is selected by the column multiplexer. k A read or write operation is performed on a group of m-bit data in a group of m-bit data.

[0054] like Figure 2B As shown, the static random access memory can be equivalent to a two-dimensional array with n rows and m bits per row, for example, n=2 N . Figure 2B Each box in the figure is a storage unit in the static random access memory, that is, a bit.

[0055] Due to various reasons, static random access memory may have data errors, that is, the data read out of the same address is not equal to the data written previously. Static random access memory errors are mainly divided into two categories:

[0056] The first type is a hard error, where the circuitry of a portion of the SRAM's internal storage array is permanently damaged, resulting in irreversible errors in that portion of the data. These errors are primarily caused by defects in the chip manufacturing process and circuit aging. MBIST (Memory Build-In-Self Test) circuitry can be used to detect the memory areas with errors, and it is important to avoid using the chip in these areas during use.

[0057] The second type is soft errors. This type of error is not permanent and the original error will disappear after writing new data to the same address.

[0058] There are two main causes of soft errors: first, radioactive particle penetration causes SRAM memory cell inversion; second, dynamic voltage noise causes memory cell inversion during data reading and writing. As transistor size shrinks, the operating voltage of SRAM decreases, and the distance between adjacent memory cells in SRAM increases, resulting in increasingly common SRAM soft errors. Because soft errors are dynamic, meaning they can occur at any time and in any location during data reading and writing during normal chip operation, and cannot be detected and avoided in advance like hard errors, soft errors must be handled dynamically.

[0059] The two causes of soft errors in static random access memory are both localized, that is, the errors are usually concentrated in a local storage area for the following reasons:

[0060] (a) Soft errors caused by radioactive particle penetration primarily occur when radioactive particles penetrate semiconductor materials and disrupt the voltage of memory cell latches. Depending on the angle and intensity of the radioactive particle penetration, one or more memory cells can be flipped. Generally, this penetration is a straight line, and errors can occur in localized areas in three directions (horizontally, vertically, and diagonally). Radioactive events are relatively low in probability and typically only cause localized errors in one or two bits.

[0061] (b) Soft errors caused by dynamic voltage noise primarily arise from local memory cell flips caused by power supply noise when reading or writing static random access memory. For example, when the main clock within the chip switches from on (with a clock signal input) to off (without a clock signal input), many other transistors will transition, causing dynamic noise on the power supply line. If a memory cell is read or written at this time, some weaker memory cells may be disturbed. Furthermore, noise may also originate from external events on the chip, such as dynamic fluctuations and noise in board-level voltages. Dynamic power supply noise only affects weaker memory cells, which are caused by variations in the manufacturing process and are localized. Therefore, soft errors generally occur in one or two local bits. Similar to radioactive particle penetration, the impact of dynamic voltage noise will become increasingly significant as technology advances and chip operating voltages decrease.

[0062] In summary, soft errors in SRAM typically occur only in localized areas and have a low probability of occurring, typically only affecting one or two bits. However, because soft errors, if unrecoverable, can cause serious system problems, recovery from soft errors must be considered during chip design.

[0063] Soft error detection usually occurs when data is read. The current processing flow for handling soft errors in static random access memory can be as follows: Figure 3 shown.

[0064] Specifically, when a soft error is detected in the SRAM, it first determines whether the data can be directly corrected. If the error can be corrected, the corrected data is directly returned. For example, if a single-bit error occurs, a SECDED (single-error correction and double-error detection) circuit can be used for correction.

[0065] If the error cannot be corrected, for example, only the parity check circuit is used without the correction circuit, first determine whether there is backup data:

[0066] If there is backup data, read the backup data and return it. For example, if an error occurs in the L1 cache, the backup data in the L2 cache can be read. If an error occurs in the L2 cache, the backup data in the L3 cache can be read. If an error occurs in the L3 cache, the correct data can be obtained by reading the dynamic random access memory. If a soft error is also detected in the backup data, the above steps may be repeated, that is, the backup data of the next level is continuously read until the correct data is obtained or there is no backup data.

[0067] If the data is not backed up, an interrupt will be generated and reported to the CPU, allowing the software to perform data recovery at the application level. The software generally takes different actions based on the severity of the error. For example, for general data errors, only software-level retransmission is required. If a serious system error occurs, the entire chip system may need to be reset, or even cause the system to crash.

[0068] Currently, soft error handling for static random access memory in chip design is mainly divided into two categories. The first category is to only detect errors without correcting them, and the second category is to use the ECC algorithm for error detection and correction. The following details the implementation methods and existing problems of the two solutions.

[0069] For the first category, a typical application is to add parity bits to static random access memory. The schematic diagram of the static random access memory storage structure of this scheme is as follows: Figure 4A This solution has the advantage of minimal hardware overhead, but its disadvantage is that it only detects soft errors and cannot perform data correction. When a soft error is detected in the data read from the static random access memory, obtaining the correct data requires reading the next level of backup data or reporting an interrupt to the CPU for software recovery.

[0070] When reading the next level of backup data, this approach has a significant delay. For example, if an L1 cache error occurs, data from the L2 cache needs to be read, a process that takes about 10 cycles. If an L2 cache error occurs, data from the L3 cache needs to be read, a process that takes 30 to 50 cycles. And if an L3 cache error occurs, data from the dynamic random access memory needs to be read, a process that takes about 200 cycles. Therefore, this solution results in a significant data delay, which can affect chip performance. Additionally, accessing the next level of backup data generally involves additional data transfer. For example, accessing data from the L3 cache or dynamic random access memory requires initiating transmission on the on-chip interconnect, which significantly increases the chip's power consumption.

[0071] If there's no backup data, the only option is to generate an interrupt and report it to the CPU, allowing the software to perform application-level data recovery. In this scenario, the software typically takes different actions based on the severity of the error. For example, a minor data error only requires a software-level retransmission. However, a serious system error may require resetting the entire chip system, or even cause a system crash. This approach introduces greater latency than that associated with reading backup data (reaching milliseconds, or millions of cycles), severely impacting chip stability and usability.

[0072] For the second category, according to the aforementioned causes of soft errors, the probability of soft errors in static random access memory is relatively small, usually only 1 to 2 bits. Therefore, a typical solution is to add a SECDED check bit to the static random access memory, such as Figure 4B The advantage of this solution is that it can directly correct the error data after reading the data of the static random access memory, without the performance impact caused by the additional delay. However, the disadvantage of this solution is that it can only correct one error bit. Some chips also use the DECTED (double-error correction and triple-error-detection) method for soft error correction, such as Figure 4C Although this method can correct 2-bit soft errors, it requires more storage overhead, is more complex in hardware implementation, and introduces additional delay and power consumption.

[0073] Table 1 compares the additional hardware memory unit overhead incurred by using SECDED and DECTED circuits for correction. Data bits represent the total number of bits (m) of data to be detected, while check bits represent the total number of check bits used to detect the data. The total number of check bits is determined by the error detection algorithm. As can be seen from Table 1, the DECTED circuit's overhead is almost twice that of the SECDED circuit. When a soft error exceeds two bits, it is necessary to read the next-level backup data or report an interrupt to the CPU for software data recovery. While better algorithms can be used to correct more error bits, the additional hardware overhead increases as the number of correction bits increases, significantly increasing chip area and power consumption.

[0074] Table 1

[0075]

[0076] like Figure 4D As shown, in order to reduce the extra storage overhead of the static random access memory and save chip area, the error check bits (not limited to the error check bits in the SECDED or DECTED algorithm) can be stored in an area of ​​the dynamic random access memory, while the static random access memory still uses Figure 4A The solution shown here adds a parity bit. This solution utilizes the existing DRAM on the chip, eliminating the need for additional SRAM memory cells and thus eliminating any additional chip area. However, this solution requires the on-chip interconnect network to initiate data reads and writes to the DRAM, resulting in significant latency, typically around 200 clock cycles, significantly impacting chip performance. Furthermore, the high number of DRAM accesses significantly increases chip power consumption.

[0077] Some high-performance chips have high RAS (Reliability, Availability, and Serviceability) requirements and require timely correction of soft errors in static random access memory to ensure chip stability and performance. In the aforementioned solution, 1-bit soft errors are mainly detected and corrected. However, with the advancement of semiconductor technology, the reduction of transistor size and the reduction of voltage, 2-bit soft errors in static random access memory are becoming more and more common. Referring to the 2-bit soft error correction solution mentioned above, either a large delay or a large storage overhead will be introduced, neither of which can meet the usage requirements.

[0078] At least one embodiment of the present disclosure provides a data reading method, a data reading device, a data writing method, a data writing device, and a soft error handling system. The data reading method includes: using an error checking method to perform a first check on m bits of data read from a target row in n rows of a storage array to obtain a first check result; in response to the first check result indicating that an error occurring in the target row cannot be fully corrected, using a parity check method to perform a second check on data in each of the m columns read from the storage array to obtain a parity check result; combining the first check result and the parity check result to obtain a second check result corresponding to the target row, wherein the number of correction bits in the second check result is greater than the maximum number of error correction bits that can be corrected by the error checking method; and using the second check result as the read result.

[0079] This data reading method performs a second check on each column of data to obtain a parity check result. Based on the parity check result and the first check result, a comprehensive analysis is performed. This method can promptly correct multi-bit soft errors in the data memory with minimal hardware overhead and latency. The number of correction bits that this data reading method can correct exceeds the maximum number of error correction bits that can be corrected by the error checking method. For example, when the error checking method is the SECDED method, this data reading method can promptly correct a two-bit soft error in the data memory with minimal hardware overhead and latency, ensuring the stability and performance of the chip system.

[0080] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0081] Figure 5 A schematic flowchart of a data reading method provided in at least one embodiment of the present disclosure.

[0082] For example, the data reading method is applied to a data memory, for example, the data memory stores n data and the data width of each data is m bits, the n data are sequentially arranged to form an n*m bit data array, and the data array is correspondingly stored as a storage array in the data memory. For example, the data memory is a static random access memory, and the storage array in the data memory can refer to Figure 2B The equivalent schematic diagram of the storage array shown is shown, where m and n are both positive integers.

[0083] For example, Figure 5 As shown, the data reading method provided by the embodiment of the present disclosure includes steps S10 to S40.

[0084] First, in step S10 , a first check is performed on m bits of data read from a target row among n rows of a storage array using an error checking method to obtain a first check result.

[0085] In step S20 , in response to the first check result indicating that the error in the target row cannot be completely corrected, a second check is performed on the data of each of the m columns read from the storage array using a parity check method to obtain a parity check result.

[0086] In step S30, the first check result and the parity check result are combined to obtain a second check result corresponding to the target row.

[0087] For example, the number of correction bits of the second check result is greater than the maximum number of error correction bits that can be corrected by the error correction method.

[0088] In step S40, the second verification result is used as the reading result.

[0089] For example, the error checking method may include an error detection and correction (ECC) algorithm, and the ECC algorithm may include a single error correction and double error detection method (hereinafter referred to as the SECDED method), a double error correction and triple error detection method (hereinafter referred to as the DECTED method), etc. Of course, the error checking method may also adopt other feasible memory error correction and detection algorithms, and the present disclosure does not limit this.

[0090] Generally speaking, when the maximum number of error detection bits that an error checking method can detect is a bits, the maximum number of error correction bits that the error checking method can correct is a-1 bits. That is, the error checking method can detect a soft error in at most a bits in the target row, and can correct at most a-1 bits, but cannot correct all a soft errors. It should be noted that in this disclosure, a represents the maximum number of error detection bits that an error checking method can detect. For example, for the SECDED method, a=2, and for the DECTED method, a=3.

[0091] For example, in the data reading method provided in at least one embodiment of the present disclosure, after obtaining the first verification result in step S10, if the first verification result indicates that the error occurring in the target row cannot be completely corrected, that is, a soft error occurs in bit a in the target row, then a second verification result is obtained according to steps S20-S40, and the verification result has corrected the soft error in bit a, and the second verification result is used as the reading result; if the first verification result indicates that the error occurring in the target row can be completely corrected, that is, a soft error occurs in at most bit a-1 in the target row, then the error checking method can directly correct the bit a-1, and the first verification result can be used as the reading result.

[0092] For example, a data storage device provides a first check array for a storage array, the first check array includes n error check storage rows corresponding one-to-one to n data, each of the n error check storage rows includes p error check bits, and the p error check bits in the i-th row of the n error check storage rows are used to store error check data corresponding to the data in the i-th row of the data array, where p and i are both positive integers.

[0093] The data memory provides a parity storage row for the storage array and the first parity array. For example, the parity storage row includes m bits corresponding one-to-one to m columns of the storage array and p bits corresponding one-to-one to p columns of the first parity array. The m bits and p bits are used to store a reference parity vector having m+p bits corresponding to the m column of the data array and the p column of the first parity array, respectively.

[0094] Figure 6 This is a schematic structural diagram of a data storage device provided in at least one embodiment of the present disclosure. Figure 6 As shown, the data memory provides a storage array composed of n m-bit data arranged in sequence (such as Figure 6 For example, the storage array may be Figure 2B The equivalent memory array shown in the figure can be referenced for its actual circuit logic. Figure 2A The form is not described here.

[0095] For example, the data memory also provides a first check array (such as Figure 6 The first check array includes n error check storage rows, each error check storage row includes p error check bits, and the p error check bits are used to store error check data corresponding to m-bit data in the same row.

[0096] For example, the relationship between m and p satisfies the following formula:

[0097] p=q+1,m≤2 q -q-1(Formula 1)

[0098] Formula 1 is obtained by the standard SECDED method, for example, m=16, p=6, m=32, p=7, m=64, p=8, etc. Of course, when other error checking methods are used, the relationship between m and p can be adjusted accordingly, and this disclosure does not limit this.

[0099] For example, the data memory also provides parity storage rows (such as Figure 6 (shown in a dotted box), a parity storage row includes m+p column parity bits for storing a reference parity vector. For example, the i-th column parity bit in the parity storage row is used to store parity data corresponding to the corresponding i-th column n-bit data.

[0100] It should be noted that Figure 6 The parity storage row is shown as being located below the memory array, but the disclosed embodiments are not limited thereto. The parity storage row may also be located in the middle of the memory array or above the memory array. For example, if the address number corresponding to the first row of the memory array is 0 and the address number corresponding to the second row of the memory array is 1, then the address number corresponding to the parity storage row may be n. This configuration does not require modifying the address number arrangement order, nor does it require adjusting the peripheral read and write address logic of the data memory, resulting in greater compatibility.

[0101] For example, the storage space size of the first check array is n*p bits, the storage space size of the parity storage row is m+p bits, and the storage space size provided by the data memory is: (n+1)(m+p).

[0102] Therefore, the percentage calculation formula for the additional storage cells (first check array and parity storage rows) added to the data storage device in the data reading method provided by at least one embodiment of the present disclosure relative to the original data area (i.e., the storage array) is:

[0103]

[0104] For example, when the address width of the data memory is N=6, n=2 N =64, when the number of data bits m=32, p=7 is calculated according to Formula 1, the storage space size of the storage array is 64*32=2048 bits, the storage space size of the first check array is 64*7=448 bits, and the storage space size of the parity storage row is (32+7)=39 bits. In addition to the storage array, the total additional overhead of the data memory is (448+39) / 2048=23.78%.

[0105] For example, relative to Figure 4B In the scheme shown, the additional overhead of the data storage in the present disclosure is only the column parity storage row, so the increased overhead is 39 / (2048+448)=1.56%.

[0106] Table 2 below compares the additional storage unit overhead of the solution provided by the present disclosure with the SECDED method (SECDED in the table below) and the DECTED method (DECTED in the table below) under different storage array sizes (e.g., different n and m).

[0107] Table 2

[0108]

[0109]

[0110] It can be seen from Table 2 that the solution provided by the present disclosure is better than the SECDED method ( Figure 4B The number of additional storage units is not much, and compared with the DECTED method ( Figure 4C (as shown) has a great advantage in storage overhead, especially in the case of larger n and smaller m.

[0111] The following is a detailed description of the Figure 6 Under the data memory structure shown, the execution process of the data reading method provided by at least one embodiment of the present disclosure.

[0112] For example, step S10 may include: reading m bits of data stored in the target row and p bits of error check data corresponding to the target row to obtain a first data row; performing a first check on the first data row using an error check method to obtain a first check result.

[0113] For example, an N-bit input address can be determined according to a data read request, and a target row to be read is determined according to the N-bit input address. Then, m bits of data stored in the target row and p bits of error check data corresponding to the target row are read from the storage array and the first check array to obtain a first data row consisting of m bits of data and p bits of error check data.

[0114] Afterwards, a first check is performed on the first data row using an error checking method to obtain a first check result. For example, the first check can utilize the error checking method to determine whether a bits out of the m+p bits of the first data row contain errors, where a is the maximum number of error detection bits that the error checking method can detect. In response to an error in bit a of the first data row, the first data row is used as the first check result. Of course, the first check result may also include an error indication signal. In response to an error in at most a-1 bits of the first data row, the first data row is corrected, and the corrected result is used as the first check result. Of course, the first check result may also include a valid indication signal.

[0115] For example, in response to the first verification result indicating that the error in the target row cannot be completely corrected, for example, the first verification result indicates that there is an error in bit a in the first data row, steps S20 - S40 are continued.

[0116] For example, step S20 may include: using a parity check method, performing a parity check operation on the data bits of each of the m columns read from the storage array and the p columns read from the first check array to obtain a detection parity check vector having m+p bits; comparing the detection parity check vector with a reference parity check vector bit by bit to determine a plurality of difference bits between the detection parity check vector and the reference parity check vector; and obtaining a parity check result based on the plurality of difference bits.

[0117] For example, when calculating the detection parity check vector, the detection parity check vector P d The calculation formula is as follows:

[0118] P i =P i-1 ^R i , where P -1 =R RdAddr , i=0~n-1 and i!=RdAddr (Formula 3)

[0119] Among them, R RdAddr Indicates the first data row, RdAddr indicates the address number of the target row, i takes 0, 1, 2.., n-1 in sequence, but i skips the address number of the target row. When i=n-1, the obtained P i That is the detection parity check vector P d .For example, Figure 6 The m+p bits of data consisting of m bits of data and p error check bits located in the same row are called a data row. The n data rows in the data memory are accumulated and bit-wise XORed to obtain the detection parity check vector P d .

[0120] Afterwards, the currently stored reference parity vector P is read from the parity storage row a , the parity check vector P will be detected d With the reference parity check vector P a Comparing bit by bit. For example, comparing the detection parity check vector with the reference parity check vector bit by bit may include performing a bitwise exclusive-OR operation on the detection parity check vector and the reference parity check vector. For example, bits that are 1 in the exclusive-OR result indicate error locations in the detection parity check vector, i.e., multiple difference bits. These difference bits indicate that errors have occurred in some data bits or error check bits in the columns corresponding to the difference bits. For example, the parity check result includes the locations of the multiple difference bits, the number of the multiple difference bits, etc.

[0121] For example, step S30 may include: determining, based on the parity check result, e potential error bits in the first data row, where the positions of the e potential error bits are the positions of multiple difference bits, and e is an integer; in response to e being greater than a-1 and less than or equal to a preset correction threshold, performing a trial and error combination test in combination with the e potential error bits, the error checking method, and the first data row to obtain a second check result, where a is the maximum number of error detection bits that the error checking method can detect.

[0122] For example, the preset correction threshold E represents the maximum number of parity check bits that can be traversed. The preset correction threshold E can be set as needed. A larger preset correction threshold E may increase the time required for correction. Setting a maximum preset correction threshold E can control the correction time and prevent useless correction calculations due to errors caused by other reasons.

[0123] For example, performing a trial-and-error combination test in combination with e potentially erroneous bits, an error checking method, and a first data row may include determining at least one correction combination consisting of a potentially erroneous bits in the e potentially erroneous bits, and performing a trial-and-error combination test on the at least one correction combination. For example, the number X of correction combinations is obtained according to the following formula:

[0124]

[0125] Here, C represents a combined calculation formula, and “!” represents a factorial operation.

[0126] For example, the trial and error combination test includes performing trial and error testing on each selected correction combination in sequence, and the trial and error test includes: flipping a data bits in the first data row corresponding to a potential error bits included in the selected correction combination to obtain an intermediate test data row corresponding to the first data row; using an error checking method, performing a first check on the intermediate test data row, in response to the intermediate test data row having at most a-1 bits with errors, processing the intermediate test data row to obtain a second check result, and stopping the trial and error combination test, and in response to the intermediate test data row still having a bits with errors, performing trial and error testing on the next correction combination.

[0127] For example, in response to the presence of errors in at most a-1 bits of the intermediate test data row, processing the intermediate test data row to obtain a second verification result, and stopping the trial and error combination test may include: in response to the presence of no errors in the intermediate test data row, using the intermediate test data row as the second verification result, and stopping the trial and error combination test; in response to the presence of an error in bit b in the intermediate test data row, correcting bit b using an error correction method, using the correction result as the second verification result, and stopping the trial and error combination test, wherein b is a positive integer and is less than or equal to a-1.

[0128] For example, if e is greater than the preset correction threshold E, it indicates that the data cannot be corrected. At this time, the second verification result may include an error indication signal, and then the backup data of the next level is read or an interrupt is generated to report to the software for processing. The specific process can be referred to Figure 3 for relevant content.

[0129] If e < a, in this case, the a-bit error in the first data row cannot be located. At this time, the second verification result may include an error indication signal, and then the backup data of the next level is read or an interrupt is generated to report to the software for processing. The specific process can be referred to Figure 3 for relevant content.

[0130] If a - 1 < e ≤ E, then a trial-and-error combination test is performed. Specifically, a potential error bits are arbitrarily selected from e potential error bits for combination to obtain X correction combinations, and the trial-and-error test is sequentially performed for each selected correction combination.

[0131] Figure 7 is a schematic diagram of potential error bits provided by at least one embodiment of the present disclosure. As Figure 7 shown, there are two soft error bits in the first data row. After the detection parity check vector and the reference parity check vector are exclusive ORed bit by bit, 3 difference bits are obtained, and the positions of the difference bits are the Figure 7 positions of the 3 potential error bits in.

[0132] For example, for the correction combination composed of the potential error bit with bit index 5 and the potential error bit with bit index 6, the data bits with bit index 5 and bit index 6 in the first data row are flipped. For example, in the flipping process, if the value of the data bit is the first value (e.g., 0), the value of the data bit is flipped to the second value (1), and if the value of the data bit is the second value, the value of the data bit is flipped to the first value, so as to obtain an intermediate test data row; then, using an error verification method, such as the SECDED method, the intermediate test data row is first verified. Since the data bits with bit index 5 and bit index 6 in the original first data row have soft errors, the intermediate test data row after the flipping process is the correct result, and the intermediate test data row is used as the second verification result, and the trial-and-error combination test is stopped.

[0133] As mentioned above, the soft errors of the static random access memory have the characteristic of locality, and the probability of adjacent storage units having soft errors is greater. Therefore, a distance-first traversal method can be adopted to locate the real soft error bits from multiple correction combinations at the fastest speed. For example, the X correction combinations are sequentially subjected to the trial-and-error test in ascending order of the data bit distance. The data bit distance of each correction combination is determined according to the distance between the a potential error bits included in each correction combination. Take Figure 7For example, when the potential error bits are located in columns 5, 6, and 8, and the error checking method is the SECDED method, there are three correction combinations: correction combination 1 consisting of potential error bits with bit indices 5 and 6, correction combination 2 consisting of potential error bits with bit indices 6 and 8, and correction combination 3 consisting of potential error bits with bit indices 5 and 8. For example, the correction combination with the smallest data bit distance can be preferentially selected for trial-and-error testing. For example, the data of correction combination 1 has a distance of 1, the data of correction combination 2 has a distance of 2, and the data of correction combination 3 has a distance of 3. The trial-and-error test is first performed on correction combination 1. If the verification fails, the trial-and-error test is performed on correction combination 2. If the verification fails, the trial-and-error test is performed on correction combination 3. As mentioned above, due to the localized nature of soft errors in static random access memory, the correct correction result may have been obtained in correction combination 1. The correction process only requires one clock cycle at the shortest. Therefore, the distance-first traversal method can shorten the correction cycle and speed up the correction process.

[0134] For example, if all the calibration combinations fail to verify after the above trial and error test, the second verification result may include an error indication signal, and then the next level of backup data is read or an interrupt is generated to report the software for processing. The specific process can be referred to Figure 3 Related content.

[0135] Finally, in step S40, the second verification result is used as the read result. For example, if the verification of the intermediate test data row of any correction combination succeeds, the second verification result including the correction result or the intermediate test data row is used as the read result. In addition, the second verification result may also include a valid flag signal; if all correction combinations fail to verify, or the number of potential error bits e is greater than E or less than a, then the second verification result may include an error indication signal and the first data row. After that, the chip system reads the backup data of the next level or generates an interrupt to report the software for processing. The specific process can be referred to Figure 3 Related content.

[0136] The data reading method provided in at least one embodiment of the present disclosure can timely locate and correct a-bit soft errors occurring in static random access memory with relatively small hardware overhead and delay overhead by adding parity storage rows, and is compatible with existing system designs, thereby reducing the probability of chip system errors and ensuring the stability and performance of the chip system.

[0137] For example, in some other embodiments, p-bit error check data may be additionally stored, that is, the correction object is m-bit data.

[0138] For example, at this time, step S10 and step S20 are the same as the above process and are not repeated here.

[0139] For example, step S30 may include: using the parity check result to determine multiple potential error bits in the m bits of data read from the target row where errors exist; in response to the number of the multiple potential error bits being equal to the maximum number of error detection bits a that can be detected by the error checking method, processing the m bits of data read from the target row according to the multiple potential error bits to obtain a second check result.

[0140] For example, the data reading method also includes: in response to the number of multiple potential error bits being within a preset correction range, constructing at least one correction combination based on the multiple potential error bits, wherein each correction combination consists of a selected potential error bits; performing a trial and error combination test on at least one correction combination; wherein the trial and error combination test includes performing a trial and error test on each selected correction combination in sequence, and the trial and error test includes: flipping a data bits corresponding to the a potential error bits included in the selected correction combination among the m bits of data read from the target row to obtain an intermediate test data row, performing a first check on the intermediate test data row using an error checking method to obtain a first intermediate check result, in response to the first intermediate check result being a check pass, obtaining a second check result based on the first intermediate correction result, and stopping the trial and error combination test, and in response to the first intermediate check result being a check fail, performing a trial and error test on the next correction combination.

[0141] For example, if the first intermediate check result is "check passed", it means that there is no error in the intermediate test data row or there is at most a-1 bit error, which can be corrected by the error checking method.

[0142] The specific execution process of the above trial and error test can refer to the relevant introduction of step S30, which will not be repeated here.

[0143] The data reading method provided in the above embodiment can timely locate and correct a-bit soft errors occurring in m-bit data of static random access memory with relatively small hardware overhead and delay overhead by adding parity storage rows, and is compatible with existing system designs, reducing the probability of chip system errors and ensuring the stability and performance of the chip system.

[0144] Figure 8 This is a flow chart of a data reading and writing method provided by at least one embodiment of the present disclosure. For example, the error checking method is the SECDED method, that is, a=2.

[0145] First, if Figure 8 As shown, a read request is received, the address of the target row is determined, the data of the target row is read, and a first check is performed on m bits of the data read from the target row. For the specific process, reference may be made to the relevant content of step S10 and will not be repeated here.

[0146] Afterwards, if the first verification result indicates that the error in the target row can be completely corrected, for example, there is at most 1 bit error in the m-bit data of the target row (or the first data row), the target row data or the correction result is directly output as the first verification result, and the read data is returned, for example, the read data is the m-bit data or correction result in the target row, completing a reading process.

[0147] If the first check result indicates that the error in the target row cannot be completely corrected, for example, there are 2 errors in the first data row or the m-bit data, a second check is performed on the data in each of the m columns read from the storage array using a parity check method to obtain a parity check result. The specific process can be referred to the relevant content of step S20 and will not be repeated here.

[0148] Then, e potential error bits in the first data row are determined based on the parity check result. If e is greater than 1 and less than or equal to a preset correction threshold E, X correction combinations are determined, and trial and error tests are performed on each selected correction combination in sequence.

[0149] For example, for the i-th correction combination, if the trial and error test passes, that is, there is at most 1 error in the intermediate test data row corresponding to the i-th correction combination, the second verification result is output, and a reading process is completed; if the trial and error test fails, that is, there are still 2 errors in the intermediate test data row corresponding to the i-th correction combination, the trial and error test is performed on the i+1-th correction combination until all correction combinations have completed the trial and error test. If the correct data is still not obtained, the error data and error indication signal are returned, and then the next level backup data is read or an interrupt reporting software processing is generated to complete a reading process. Here, i is a positive integer and is less than or equal to the total number of correction combinations. For example, all correction combinations can be trial-and-error tested in sequence according to the distance priority principle. For the specific execution process of the trial and error test, please refer to the relevant content of step S30, which will not be repeated here.

[0150] If e is less than or equal to 1 or greater than the preset correction threshold E, the erroneous reading data and error indication signal are directly returned, and then the next level of backup data is read or an interrupt is generated to report software processing to complete a reading process.

[0151] With reference to the above-mentioned contents, the maximum delay RL consumed by the data reading method provided by at least one embodiment of the present disclosure is max As shown in the following formula:

[0152]

[0153] At this time, a soft error occurs in the first data row, and steps S20-S30 need to be executed, where reading n-1 data rows in step S20 consumes n-1 clock cycles, calculating the parity check result consumes 1 clock cycle, and the trial and error combination test consumes X clock cycles.

[0154] The minimum delay RL consumed by the data reading method provided by at least one embodiment of the present disclosure is min As shown in the following formula:

[0155]

[0156] Here, SE (Soft Error) represents the number of soft error bits in the first data row. When the number of soft error bits SE is less than or equal to a-1, the additional delay caused by the read operation is 0. When the number of data soft error bits SE is equal to a and the number of potential error bits e is greater than a-1 and less than or equal to the preset correction threshold E, and the a-bit error correction is completed in the first clock cycle, the additional delay caused by the read operation is n+1, wherein the process of calculating the detection parity vector requires n-1 clock cycles, comparing the detection parity vector with the reference parity vector bit by bit requires 1 clock cycle, and executing step S30 requires 1 clock cycle.

[0157] Table 3 lists the additional delays of read operations for several common address widths N and potential error bit numbers e. For example, in Table 3, the error checking method uses the SECDED method, which means that the maximum number of error detection bits a that can be detected is 2.

[0158] As can be seen from Table 3, the read operation delay mainly depends on the address width N of the static random access memory. The smaller N is, the smaller the delay overhead is. When the depth of the static random access memory is less than or equal to 128 (N=7), the read operation delay is less than the delay overhead of reading dynamic random access memory data (200 cycles). Therefore, the solution provided by the present disclosure is more suitable for static random access memories with a relatively small depth, that is, static random access memories with a relatively small N.

[0159] Table 3

[0160]

[0161] Therefore, the data reading method that at least one embodiment of the present disclosure provides can be applicable to the size of any static random access memory, and when the depth of the static random access memory is smaller, the additional delay required for correcting a bit error is smaller, but the area cost ratio is relatively high; The larger the depth of the static random access memory, the smaller the area cost ratio, but the delay for correcting a bit error is also larger. In chip design, usually many static random access memories with larger storage spaces are divided into multiple small static random access memories, to meet convenient layout and routing and timing closure, such as a 1024x256 static random access memory is divided into four 128x256 blocks (bank), the area of ​​each block is smaller, performance is higher, and it is more friendly for layout and routing. Therefore, in chip design, large block static random access memories can be divided into small static random access memories, to balance area and delay cost.

[0162] In summary, the data reading method provided by at least one embodiment of the present disclosure has advantages in area overhead, performance, and power consumption. It can correct the increasingly common 2-bit soft errors in real time and is compatible with the correction of 1-bit soft errors. 2-bit soft error correction is implemented when reading data from a static random access memory (SRAM), reducing the delay and power consumption of data recovery caused by SRAM errors that cannot be corrected, thereby improving system performance. Furthermore, the storage overhead of a SRAM that corrects 2-bit soft errors is less than that of all other current solutions, saving chip area and cost.

[0163] Specifically, in terms of area overhead, the data reading method provided by at least one embodiment of the present disclosure is superior to Figures 4A-4D The soft error correction solution provided, and the larger the static random access memory, the lower the proportion of area overhead. In terms of performance, the data reading method provided by at least one embodiment of the present disclosure is better. For example, when there is at most a-1 bit error, no additional read delay is generated. When an a-bit error occurs, for a static random access memory with a small depth (such as N<=7), the read operation delay can be controlled within 150 cycles, and the smaller the depth of the static random access memory, the smaller the delay. Compared with reading the next level backup data (10 to 200 cycles) or reporting interrupt software processing (millions of cycles), it has obvious advantages in performance; for a static random access memory with a larger depth, although the read delay is relatively large, it still has obvious advantages compared to reporting interrupt software processing (millions of cycles). In terms of power consumption, because a-bit error correction occurs when reading data, there is no need to initiate other system transmissions, so power consumption also has certain advantages.

[0164] At least one embodiment of the present disclosure further provides a data writing method. Figure 9 This is a schematic flow chart of a data writing method provided by at least one embodiment of the present disclosure. Figure 9As shown, the data writing method provided by the embodiment of the present disclosure includes steps S50 to S60.

[0165] For example, the data writing method is used to write data to a data storage device. For example, the data storage device is configured to be able to store n data, and the data width of each of the n data is m bits, and the n data are arranged in sequence to form an n*m-bit data array, and the n*m-bit data array is correspondingly stored as an n*m-bit storage array in the data storage device. For example, the data storage device provides a first check array for the storage array, and the first check array includes n error check storage rows corresponding to the n data one by one. For example, the data storage device provides a parity check storage row for the storage array and the first check array. For more information about the storage array, the first check array, and the parity check storage row in the data storage device, please refer to Figure 6 The relevant content will not be repeated here.

[0166] In step S50 , first verification data is generated for target data of a target row among n rows to be written into a storage array based on an error checking method.

[0167] For example, the first verification data is used to verify the target row using an error checking method.

[0168] In step S60, a reference parity check vector is obtained based on the target data using a parity check method.

[0169] For example, a reference parity check vector is used to perform parity check on each of the m columns.

[0170] For example, in step S50, when a data write request is received, the data write request is parsed to determine the target data included in the data write request and the address of the target row to be written, for example, the data width of the target data is m bits; an error checking method, such as the SECDED method, the DECTED method, etc., is used to generate the first check data of the target data, for example, the first check data includes p error check bits, and the relationship between m and p is shown in Formula 1, which will not be repeated here.

[0171] For example, step S60 may include: reading a current reference check vector stored in the parity storage row, and performing a bitwise exclusive OR operation on the current reference check vector, the target data, and the first check data to obtain a reference parity check vector.

[0172] For example, Figure 6 As shown, the address of the parity storage row is n, and the m-bit target data and the p-bit first check data are stored in Figure 6 The positional relationship shown is spliced ​​into a data row, and a bitwise XOR operation is performed with the current reference check vector read from the parity storage row to calculate the updated value of the reference parity check vector.

[0173] For example, the data writing method may further include: writing target data into a target row in a storage array; writing first check data into an error check storage row corresponding to the target row in a first check array; and writing an updated value of a reference parity check vector into a parity check storage row.

[0174] Figure 10 This is a flowchart of a data writing method provided by at least one embodiment of the present disclosure.

[0175] like Figure 10 As shown, first, when receiving a data write request, first verification data is generated. The specific process is as described in step S50 and will not be repeated here.

[0176] Afterwards, the operations of reading the parity check storage row, writing the target data into the target row in the storage array, and writing the first check data generated in step S50 into the error check storage row corresponding to the target row in the first check array are completed in parallel.

[0177] Afterwards, a reference parity check vector is calculated and written into the parity check storage row. The specific process of calculating the reference parity check vector is as described in step S60 and will not be repeated here. This process requires an additional clock cycle.

[0178] Therefore, in the data writing method provided in at least one embodiment of the present disclosure, the additional delay caused by the write operation is 1 clock cycle, that is, the time taken to calculate the reference parity vector and write it into the parity storage row.

[0179] Table 4 shows the technical solutions of the present disclosure and Figures 4A-4D The technical solutions in

[15] were compared in terms of storage overhead, access latency, and power consumption. For example, the solution adopted by this disclosure uses an address width of N = 6, a data bit number m = 64, and a SECDED error correction method, i.e., a = 2. As can be seen in Table 4, the solution disclosed in this disclosure can achieve timely correction of 2-bit soft errors in static random access memory with minimal storage overhead and power consumption, and moderate latency.

[0180] Table 4

[0181]

[0182] Here is an explanation of the parameters in Table 4: Figure 4A For example, when a 1-bit error occurs, if there is data backup (such as backup data in the next-level cache or DRAM), the access delay is 10 to 200 clock cycles. If there is no data backup, an interrupt needs to be reported and processed by software, which takes more than milliseconds (millions of clock cycles). Since a system bus transmission needs to be initiated to read or restore data, it will cause greater power consumption. Figure 4D The solution shown in the figure needs to initiate a system bus transmission to read the data in the dynamic random access memory, which will result in a large power consumption.

[0183] Corresponding to the data reading method and the data writing method described above, at least one embodiment of the present disclosure further provides a soft error handling system.

[0184] Figure 11 A schematic structural diagram of a soft error handling system provided in at least one embodiment of the present disclosure.

[0185] like Figure 11 As shown, the soft error reading system 100 includes a data memory 101 and a control circuit 102 .

[0186] For example, the data memory 101 may be a static random access memory.

[0187] For example, the data memory 101 stores n data and the data width of each data is m bits. The n data are arranged in sequence to form an n*m-bit data array, and the data array is correspondingly stored as a storage array in the data memory. For example, the data memory 101 provides a first check array for the storage array, and the first check array includes n error check storage rows corresponding to the n data one-to-one. Each of the n error check storage rows includes p error check bits, and the p error check bits in the i-th row of the n error check storage rows are used to store the error check data corresponding to the data in the i-th row of the data array. For example, the data memory 101 provides a parity check storage row for the storage array and the first check array, wherein the parity check storage row includes m bits corresponding to the m columns of the storage array and p bits corresponding to the p columns of the first check array, and the m bits and p bits are used to store the reference parity check vectors with m+p bits corresponding to the m columns of the data array and the p columns of the first check array, respectively. For the specific structure of the data memory, please refer to Figure 6 The relevant content will not be repeated here.

[0188] For example, Figure 11 As shown, the control circuit 102 includes a controller 103 and an error checker 104 .

[0189] For example, the error checker 104 is configured to perform a first check on m bits of data read from a target row in n rows of the memory array using an error checking method to obtain a first check result.

[0190] For example, the error checker 104 performs a first check on m bits of data read from a target row in n rows of a storage array using an error checking method, and when obtaining a first check result, includes performing the following steps: receiving m bits of data stored in the target row read from the storage array and p bits of error checking data corresponding to the target row to obtain a first data row; using the error checking method, determining whether there are errors in a bits among the m+p bits of the first data row, where a is the maximum number of error detection bits that the error checking method can detect; in response to an error in a bit in the first data row, outputting the first data row to the controller 103, wherein the first check result includes the first data row; in response to an error in at most a-1 bits in the first data row, performing correction processing on the first data row, and outputting the correction result to the controller 103, wherein the first check result includes the correction result.

[0191] For example, the controller 103 is configured to: in response to a first check result indicating that an error occurring in a target row cannot be completely corrected, perform a second check on the data of each of the m columns read from the storage array using a parity check method to obtain a parity check result; combine the first check result and the parity check result to obtain a second check result corresponding to the target row, wherein the number of correction bits in the second check result is greater than the maximum number of error correction bits that can be corrected by the error checking method; and output the second check result as a read result.

[0192] For example, when the controller 103 executes a second check using a parity check method on the data of each column of the m columns read from the storage array and obtains a parity check result, the following operations are performed: using the parity check method, a parity check operation is performed on the data bits of each column of the m columns read from the storage array and the p columns read from the first check array to obtain a detection parity check vector with m+p bits; reading a reference parity check vector from the parity check storage row; comparing the detection parity check vector with the reference parity check vector bit by bit to determine multiple difference bits between the detection parity check vector and the reference parity check vector; and obtaining a parity check result based on the multiple difference bits.

[0193] For example, when the controller 103 executes the combination of the first check result and the parity check result to obtain the second check result corresponding to the target row, it includes the following operations: according to the parity check result, determining e potential error bits in the first data row, wherein the positions of the e potential error bits are the positions of multiple difference bits, and e is an integer; in response to e being greater than a-1 and less than or equal to a preset correction threshold, performing a trial and error combination test in combination with the e potential error bits, the error checking method and the first data row to obtain the second check result.

[0194] For example, when the controller 103 executes a trial-and-error combination test in combination with e potential error bits, an error checking method, and a first data row to obtain a second check result, the following steps are included: determining at least one correction combination consisting of a potential error bits in each of the e potential error bits, and performing a trial-and-error combination test on at least one correction combination; wherein the trial-and-error combination test includes performing a trial-and-error test on each selected correction combination in sequence, and the trial-and-error test includes: flipping a data bits in the first data row corresponding to the a potential error bits included in the selected correction combination to obtain an intermediate test data row corresponding to the first data row; sending the intermediate test data row to the error checker 104; in response to receiving a first flag signal sent by the error checker 104, stopping the trial-and-error combination test, outputting a second check result sent by the error checker 104, and in response to receiving a second flag signal sent by the error checker 104, performing a trial-and-error test on the next correction combination.

[0195] For example, the error checker 104 is further configured to: perform a first check on the intermediate test data row received from the controller using an error checking method; in response to there being no error in the intermediate test data row, use the intermediate test data row as a second check result, and send the second check result and the first flag signal to the controller 103, for example, the first flag signal may be a valid indication signal indicating that the check is successful; in response to there being an error in bit b in the intermediate test data row, correct bit b using an error checking method, use the correction result as a second check result, and send the second check result and the first flag signal to the controller, where b is a positive integer and is less than or equal to a-1; in response to there still being an error in bit a in the intermediate test data row, output a second flag signal to the controller, for example, the second flag signal may be an error indication signal indicating that the check failed.

[0196] For example, Figure 11 As shown, the control circuit 102 further includes an error check code generator 105, which is configured to generate first check data for target data of a target row in n rows to be written to the storage array based on an error check method, wherein the first check data is used to check the target row using the error check method; the controller 103 is further configured to obtain a reference parity check vector using a parity check method based on the target data, wherein the reference parity check vector is used to perform a parity check on each column in the m columns.

[0197] For example, the control circuit 103 further includes an enable selector MUX1, an address selector MUX2, a read data selector MUX3, and a write data selector MUX4.

[0198] The enable selector MUX1 is configured to input an enable signal determined based on a data write request or a read request, or an enable signal generated by the controller 103 , to an enable port of the data memory 101 under the control of the controller 103 .

[0199] The address selector MUX2 is configured to input an address determined based on a data write request or a data read request, or an address generated by the controller 103 , to an address port of the data memory 101 under the control of the controller 103 .

[0200] The read data selector MUX3 is configured to input data received from the read data port of the data memory 101 or an intermediate test data row generated by the controller 103 to the error checker 104 under the control of the controller 103 .

[0201] The write data selector MUX4 is configured to input the target data and the first check data, or the reference parity check vector generated by the controller 103 , to the write data port of the data memory 101 under the control of the controller 103 .

[0202] At least one embodiment of the present disclosure provides a soft error handling system, which provides a parity storage row in a data memory to locate the position of an a-bit soft error with a relatively small storage overhead. By designing the peripheral hardware circuit of the data memory, that is, the control circuit, possible potential error bits are processed in a traversal manner to ensure that the a-bit soft error is corrected in a timely manner, thereby reducing the probability of system errors and improving system stability. In addition, the soft error handling system is fully compatible with existing solutions, such as the interface of static random access memory, error reporting mechanisms, etc., and the interface definition of the soft error handling system does not need to be changed. The hardware and software modifications are small, and the soft error system is modular and reconfigurable.

[0203] Figure 12 A structural diagram of a soft error system provided by at least one embodiment of the present disclosure.

[0204] like Figure 12 As shown, the soft error system includes a data memory 101 and a peripheral hardware circuit, namely a control circuit 102. The control circuit 102 controls the soft error correction process, and cooperates with the improved data memory 101 to correct a bit soft error with less hardware overhead and delay overhead.

[0205] The interface of the control circuit 102 is identical to the read and write control circuit of a standard static random access memory, and can replace the static random access memory in an existing device in situ without modifying other circuit logics.

[0206] The control circuit 102 includes a controller 103, which is the core of the soft error handling system. It is responsible for generating a first read address, a first write address, a first read enable signal, a first write enable signal, etc., controlling the selection of the enable selector MUX1, the address selector MUX2, the read data selector MUX3 and the write data selector MUX4, and controlling the data correction processing flow.

[0207] The control circuit 102 also includes an error checker 104, for example, the error checker 104 is a SECDED checker, which is used to perform single error correction and double error detection on the read data row or the intermediate test data row, and output the check result and an indication signal, for example, the indication signal includes a first flag signal and a second flag signal.

[0208] For example, the control circuit 102 further includes an error check code generator 105 for generating first check data for the target data to be written. This process is the same as the conventional check code generation process of the adopted error check method.

[0209] For example, the first read address, the first write address, the first read enable signal, and the first write enable signal are generated by the controller 103 , and the second read address, the second write address, the second read enable signal, and the second write enable signal are determined by an external read request or write request.

[0210] For example, when reading a parity storage row, the controller 103 generates a first read address (eg, a data storage structure such as Figure 6 As shown, the first read address is n) and the first read enable signal are used to read the reference parity vector from the data memory; for example, when calculating the detection parity vector, the controller 103 generates the first read address and the first read enable signal, and sequentially reads n-1 data rows other than the target row and the corresponding error check data in the data memory; for example, when updating the parity storage row, the controller 103 generates the first write address (for example, n) and the first write enable signal, and writes the reference parity vector to the data memory; for example, when writing the target data, the controller 103 generates the second write address (for example, the address of the target row) and the second write enable signal, and writes the second data row to the data memory, for example, the second data row includes the target data and the first check data corresponding to the target data.

[0211] For example, when receiving a data read request, the controller 103 controls the address selector MUX2 and the enable selector MUX1 to select the second read address and the second read enable, respectively, where the second read address and the second read enable are determined based on the data read request. For example, when receiving a data write request, the controller 103 controls the address selector MUX2 and the enable selector MUX1 to select the second write address and the second write enable, respectively, where the second write address and the second write enable are determined based on the data write request. For example, when executing a data correction-related process, the controller 103 controls the address selector MUX2 and the enable selector MUX1 to select the first read address and the first read enable, respectively.

[0212] For example, when a data read request is received, the read data selector MUX3 selects the read data row and sends it to the error checker 104 for error checking. When a trial-and-error combination test is performed, the read data selector MUX3 selects the intermediate test data row and sends it to the error checker 104 for error checking.

[0213] For example, when receiving a data write request, the write data selector MUX4 selects the second data row to be written into the data memory, and when updating the parity storage row, the write data selector MUX4 selects the reference parity vector row to be written into the data memory.

[0214] The following combination Figure 12 , specifically describing the processing process of the soft error system provided by at least one embodiment of the present disclosure.

[0215] For example, when receiving a data read request, the controller 103 controls the address selector MUX2 and the enable selector MUX1 to select the second read address (for example, the address of the target row) and the second read enable respectively, and reads the m-bit data and the p-bit error check data in the target row in the data memory. The m-bit data and the p-bit error check data are sequentially shifted. Figure 6 The storage structure shown forms a first data row. The controller 103 controls the read data selector MUX3 to send the first data row output from the read data port to the error checker 104 for error checking.

[0216] If the error checker 104 determines during the error checking process that there are errors in at most a-1 bits in the first data row, for example, there are no errors in the first data row, the first flag signal (for example, 0) is output to the controller 103, indicating that there are no data bit errors. The error checker 104 sends the first data row as the check result to the controller 103, and the controller 103 immediately forwards and outputs the first data row as read data, and sets the error indication signal to 0 and the valid flag signal to 1, thereby ending this round of read operation; for example, if there are 1 to a-1 bit errors in the first data row, the first flag signal (for example, 1) is output to the controller 103, indicating that there are errors but they have been corrected. The error checker 104 performs correction processing on the first data row, and outputs the correction result as the check result to the controller 103, and the controller 103 immediately forwards and outputs the correction result as read data, and sets the error indication signal to 0 and the valid flag signal to 1, thereby ending this round of read operation.

[0217] If the error checker 104 determines during the error checking process that there is an error in a bit in the first data row, and the error checking method cannot correct the error to obtain the correct data, the first data row is sent to the controller 103 as the check result, and a second flag signal (for example, 2) is output to the controller 103, indicating that there is an a-bit data error and it cannot be corrected, and the a-bit error correction process needs to be started. The specific process is as follows.

[0218] First, the controller 103 sequentially reads n-1 data rows other than the target row in the data memory (at this time, the first data row in the target row has been input through the branch of the read data port and stored in the controller 103, so it no longer needs to be read). Each data row includes m bits of data and p bits of error check data corresponding to the m bits of data. The controller 103 calculates the detection parity check vector according to Formula 3, which is not repeated here.

[0219] Afterwards, the controller 103 reads the reference parity check vector stored in the parity check storage row. For example, the first read address is n at this time, and compares the detection parity check vector with the reference parity check vector bit by bit to obtain a parity check result. The specific process is as described above and will not be repeated here.

[0220] Controller 103 then determines, based on the parity check result, the number of potentially erroneous bits in the first data row, e. If e is less than or equal to a-1 or greater than a preset correction threshold, indicating that the data cannot be corrected, controller 103 returns the erroneous data and sets the error indication signal to 1 and the valid indication signal to 0. In this case, it is necessary to read the backup data at the next level or generate an interrupt to report to the software for processing, which will not be detailed here.

[0221] If e is greater than a-1 and less than or equal to the preset correction threshold, a trial and error combination test is performed. For example, during the trial and error combination test, a distance-priority traversal method can be adopted, and correction combinations with smaller data bit distances are preferentially selected for traversal. The specific process of the trial and error test is referred to the content described above and will not be repeated here.

[0222] If the intermediate test data row corresponding to any correction combination is input into the error checker 104 for verification, the indication signal output by the error checker 104 is a first flag signal (for example, 0 or 1), indicating that the correct data is obtained, the controller 103 forwards the verification result output from the error checker 104 and outputs it as read data, sets the error indication signal to 0, and sets the valid flag signal to 1, thereby ending this round of reading operation.

[0223] If the intermediate test data row corresponding to any correction combination is input to the error checker 104 for verification, and the indication signal output by the error checker 104 is the second flag signal (for example, 2), indicating that correct data is not obtained, the controller 103 continues to perform trial and error testing on the next correction combination.

[0224] If correct data is still not obtained after X correction combinations are traversed, it means that the verification has failed, and the controller 103 returns error data and sets the error indication signal to 1 and the valid indication signal to 0. In this case, it is necessary to read the backup data of the next level or generate an interrupt to report the software processing, which will not be repeated here.

[0225] For example, when a data write request is received, first, the data write request is parsed to obtain target data and target row, the target data is input into the error check code generator 105 to generate first check data, and the error check code generator 105 combines the first check data and the target data into a first check data. Figure 6 The storage structures shown are spliced ​​together to form a second data row.

[0226] Afterwards, the controller 103 controls the write data selector MUX4 to write the second data row into the target row in the data memory, and the error check code generator also sends the second data row to the controller 103; the controller 103 reads the current parity vector stored in the parity storage row, and the first read address is n at this time.

[0227] Afterwards, the controller 103 performs an XOR operation on the second data row and the current parity vector to obtain a reference parity vector, and controls the write data selector MUX4 to write the reference parity vector into the parity storage row in the data memory. At this time, the first write address is n.

[0228] Figures 13A-13EA diagram illustrating soft errors in at least one embodiment of the present disclosure is provided. In these embodiments, a storage array in a data memory includes 64 64-bit data rows, each 64-bit data row corresponds to 8 bits of error checking data, and each data row includes 72 bits. For example, in this embodiment, the error checking method uses the SECDED method, i.e., a = 2. However, the present disclosure is not limited to this method.

[0229] Below Figures 13A-13E The soft error shown is taken as an example, combined with Figure 12 The soft error processing system shown in the figure specifically illustrates the processing process under various soft error conditions.

[0230] For example, Figure 13A It is a soft error caused by vertical radioactive particles. Figure 13A As shown, it is assumed that a 3-bit soft error occurs in a local vertical direction, and the 3 bits are distributed on the same column (column number is 5) in rows 2 to 4 of the storage array.

[0231] like Figure 13A As shown, the target row has an address of 3. First, the 64-bit data and 8-bit error check data at address 3 are read from data memory 101. A first check is performed on the first data row consisting of the 64-bit data and the 8-bit error check data. Since only one bit in the first data row has an error, a correction can be performed directly. The correction result is sent to controller 103 as the check result. An indication signal of 1 indicates that correct data has been obtained. When controller 103 detects that the indication signal is 1, it immediately outputs the check result from error checker 104 as the read data, sets the error indication signal to 0, and sets the valid flag signal to 1, thus ending this round of read operations.

[0232] This reading process does not cause any additional delay and has no additional impact on the performance and power consumption of the chip system.

[0233] It should be noted that this embodiment is described by taking the occurrence of soft errors in three consecutive storage units in the vertical direction as an example. Of course, it can also be extended to soft errors in storage units at any position in the vertical direction. The processing method is exactly the same and will not be repeated here.

[0234] For example, Figure 13B is the soft error caused by diagonal radioactive particles. Figure 13B As shown, it is assumed that a 3-bit soft error occurs in the local diagonal direction, and the 3 bits are distributed in different columns (4, 5, 6) of the 2nd to 4th rows of the storage array.

[0235] like Figure 13BAs shown, the target row has an address of 3. First, the 64-bit data and 8-bit error check data at address 3 are read from data memory 101. A first check is performed on the first data row consisting of the 64-bit data and the 8-bit error check data. Since only one bit in the first data row has an error, a correction can be performed directly. The correction result is sent to controller 103 as the check result. An indication signal of 1 indicates that correct data has been obtained. When controller 103 detects that the indication signal is 1, it immediately outputs the check result from error checker 104 as the read data, sets the error indication signal to 0, and sets the valid flag signal to 1, thus ending this round of read operations.

[0236] Although there are three potential error bits in this embodiment (columns 4, 5, and 6), because there is only one soft error bit in the read data row, the two-bit error correction process is not initiated. This read process does not consume additional delay and has no additional impact on the performance and power consumption of the chip system.

[0237] It should be noted that in this embodiment, the description is made by taking the occurrence of soft errors in three consecutive storage units in the diagonal direction as an example. Of course, it can also be extended to soft errors in storage units at any position in the diagonal direction. The processing method is exactly the same and will not be repeated here.

[0238] For example, Figure 13C It is a soft error caused by radioactive particles in the horizontal direction. Figure 13C As shown, it is assumed that two bits of soft error occur in the local horizontal direction, and the two bits are distributed in different columns (4, 5) of the same row.

[0239] like Figure 13C As shown, the address of the target row is 3. First, the 64-bit data and 8-bit error check data at address 3 are read from the data memory 101, and the first check is performed on the first data row consisting of the 64-bit data and the 8-bit error check data. Since there are 2 bits of errors in the first data row, the error checker 104 cannot directly perform correction at this time. The error checker 104 sends the first data row as the check result to the controller 103, and outputs an indication signal with a value of 2 to the controller 103.

[0240] The controller 103 detects that the indication signal is 2, indicating that a 2-bit soft error occurs in the first data row being read. At this time, the controller 103 controls and starts a 2-bit error correction process.

[0241] First, the controller 103 sequentially reads rows 0, 1, 2, 4 to 63 except address 3 in the data memory 101, and performs a cumulative XOR operation on the read data rows to obtain a detection parity check vector.

[0242] Afterwards, the controller 103 reads the reference parity vector stored in the parity storage row, and performs an XOR operation on the reference parity vector and the detection parity vector to obtain a parity result of 72'b00001100...00.

[0243] Afterwards, the controller 103 finds that two bits in the parity check result are 1, that is, there are two potential error bits in the first data row, namely bits 4 and 5, indicating that errors have occurred in these two columns, so bits 4 and 5 in the first data row are flipped. For example, bits 4 and 5 in the first data row are 1 and 0 respectively. After flipping, bits 4 and 5 become 0 and 1 respectively, thereby obtaining the middle test data row.

[0244] Afterwards, the controller 103 sends the flipped intermediate test data row to the error checker 104 for verification. If the verification passes, the error checker 104 outputs an indication signal of 0.

[0245] Afterwards, the controller 103 detects that the indication signal is 0, indicating that the correct data has been obtained, and immediately outputs the verification result from the error checker 104 as the read data, sets the error indication signal to 0, and the valid flag signal to 1, ending this round of reading operation.

[0246] This reading process introduces a delay consumption of 63+1+1=65 clock cycles.

[0247] It should be noted that in this embodiment, the soft errors of two consecutive bits in the horizontal direction are described as an example. Of course, it can also be extended to soft errors of two bits at any position in the horizontal direction. The processing method is exactly the same and will not be repeated here.

[0248] For example, Figure 13D It is a soft error caused by radioactive particles in the horizontal direction. Figure 13D As shown, it is assumed that a 4-bit soft error occurs in a local area. Although this situation is rare, this embodiment shows that the soft error handling system provided by the present disclosure can handle similar problems.

[0249] like Figure 13D As shown, the address of the target row is 3. First, the 64-bit data and 8-bit error check data at address 3 are read from the data memory 101, and the first check is performed on the first data row consisting of the 64-bit data and the 8-bit error check data. Since there are 2 bits of errors in the first data row, the error checker 104 cannot directly perform correction at this time. The error checker 104 sends the first data row as the check result to the controller 103, and outputs an indication signal with a value of 2 to the controller 103.

[0250] The controller 103 detects that the indication signal is 2, indicating that a 2-bit soft error occurs in the first data row being read. At this time, the controller 103 controls and starts a 2-bit error correction process.

[0251] First, the controller 103 sequentially reads rows 0, 1, 2, 4 to 63 except address 3 in the data memory 101, and performs a cumulative XOR operation on the read data rows to obtain a detection parity check vector.

[0252] Afterwards, the controller 103 reads the reference parity check vector stored in the parity check storage row, and performs an XOR operation on the reference parity check vector and the detection parity check vector to obtain a parity check result of 72'b00111100...00.

[0253] Afterwards, the controller 103 finds that four bits in the parity check result are 1, which means that there are four potential error bits in the first data row, namely bits 2, 3, 4 and 5, indicating that errors have occurred in these columns. However, according to the first check result, only two bits in the first data row are erroneous, so it is necessary to traverse six correction combinations consisting of any two bits of bits 2, 3, 4 and 5 and perform trial and error combination testing. According to the distance-first traversal principle, the traversal order of the six correction combinations is: (2, 3), (3, 4), (4, 5), (2, 4), (3, 5) and (2, 5), which requires a maximum of 6 clock cycles. The trial and error combination test is described in detail below:

[0254] For the correction combination consisting of bits 2 and 3: Flip bits 2 and 3 in the first data row. For example, if bits 2 and 3 in the first data row are 1 and 0, respectively, after flipping, bits 2 and 3 become 0 and 1, respectively, thereby obtaining an intermediate test data row. Because the actual erroneous bits are 2 and 4, after flipping bits 2 and 3, bit 2 becomes correct data, but bit 3 now becomes erroneous data. Combined with the originally erroneous bit 4, there are still two erroneous bits in the intermediate test data row. Therefore, controller 103 sends the intermediate test data row to error checker 104 for verification. At this time, the output verification result signal is still 2 (indicating that two bit errors are uncorrectable). Controller 103 detects that the indication signal from error checker 104 is 2, indicating that the verification result is not correct data, and then continues to try the next correction combination.

[0255] For the correction combination consisting of bits 3 and 4: Similar to the above process, the intermediate test data row now contains two bit errors (bits 2 and 3), and the indication signal from error checker 104 is still 2. Controller 103 detects that the indication signal from error checker 104 is 2, indicating that the verification result is not correct data, and thus proceeds to try the next correction combination.

[0256] For the correction combination consisting of bits 4 and 5: Similar to the above process, the intermediate test data row now contains two bit errors (bits 2 and 5), and the indication signal from error checker 104 is still 2. Controller 103 detects that the indication signal from error checker 104 is 2, indicating that the verification result is not correct data, and then proceeds to try the next correction combination.

[0257] The correction combination for bits 2 and 4 is similar to the above process. Because the bits with soft errors in the first data row are bits 2 and 4, the intermediate test data row obtained in this case is correct data, and the indication signal from error checker 104 is 0. Controller 103 detects that the indication signal from error checker 104 is 0, indicating that the verification result output by error checker 104 is correct data. Therefore, the correction process is stopped and no further combinations that have not been traversed are tried.

[0258] Afterwards, the controller 103 outputs the check result output from the error checker 104 as the read data, sets the error indication signal to 0, sets the valid flag signal to 1, and ends this round of reading operation.

[0259] This reading process introduces a delay consumption of 63+1+4=68 clock cycles, and due to the use of the distance-first traversal method, the delay is reduced by 2 clock cycles.

[0260] It should be noted that in this embodiment, multiple potential error bits occur due to soft errors in non-target rows. Of course, there may be more soft errors in non-target rows as long as they are not greater than the preset correction threshold E.

[0261] For example, Figure 13E This is an example of a soft error handling system correction provided by an embodiment of the present disclosure.

[0262] like Figure 13E As shown, the address of the target row is 3. First, the first data row is read from the data memory 101 and a first check is performed. Since there are 2 bits of error in the first data row, the error checker 104 cannot directly perform correction at this time. The error checker 104 sends the first data row as the check result to the controller 103 and outputs an indication signal with a value of 2 to the controller 103.

[0263] The controller 103 detects that the indication signal is 2, indicating that a 2-bit soft error occurs in the first data row being read. At this time, the controller 103 controls and starts a 2-bit error correction process.

[0264] First, the controller 103 sequentially reads rows 0, 1, 2, 4 to 63 except address 3 in the data memory 101, and performs a cumulative XOR operation on the read data rows to obtain a detection parity check vector.

[0265] Afterwards, the controller 103 reads the reference parity vector stored in the parity storage row, and performs an XOR operation on the reference parity vector and the detection parity vector to obtain a parity result of 72'b001110111100...00.

[0266] Afterwards, the controller 103 detects that 7 bits in the parity check result are 1, that is, there are 7 potential error bits in the first data row. Assuming that the preset correction threshold is 6, the controller 103 cannot process it at this time, returns the error data, sets the error indication signal to 1, sets the valid flag signal to 0, and ends this round of reading operation. Of course, if the preset correction threshold is set to 7, soft error correction can still be performed with reference to the process described above, and the specific process will not be repeated. In other words, the preset correction threshold can be adjusted according to performance requirements. The larger the preset correction threshold, the longer the delay spent on traversing the correction combination. In practice, an appropriate preset correction threshold can be selected according to specific application requirements to balance the stability and delay performance of the data storage.

[0267] Corresponding to the above-mentioned data reading method, at least one embodiment of the present disclosure further provides a data reading device. Figure 14 A schematic block diagram of a data reading device provided in at least one embodiment of the present disclosure.

[0268] For example, the data reading device is applied to a data storage device. For relevant contents of the data storage device, reference may be made to the relevant introduction of the data storage device in the aforementioned data reading method, and repeated details will be omitted.

[0269] like Figure 14 As shown, the data reading device 200 includes: a first verification unit 201 , a second verification unit 202 , a correction unit 203 and an output unit 204 .

[0270] The first check unit 201 is configured to perform a first check on m bits of data read from a target row in n rows of the storage array using an error checking method to obtain a first check result;

[0271] The second check unit 202 is configured to, in response to the first check result indicating that the error occurring in the target row cannot be completely corrected, perform a second check on the data of each of the m columns read from the storage array using a parity check method to obtain a parity check result;

[0272] a correction unit 203 configured to combine the first check result and the parity check result to obtain a second check result corresponding to the target row, wherein the number of correction bits in the second check result is greater than the maximum number of error correction bits that can be corrected by the error correction method;

[0273] The output unit 204 is configured to output the second verification result as a reading result.

[0274] For example, the first verification unit 201, the second verification unit 202, the correction unit 203, and the output unit 204 can be dedicated hardware devices for implementing some or all of the functions of the first verification unit 201, the second verification unit 202, the correction unit 203, and the output unit 204 described above. For example, the first verification unit 201, the second verification unit 202, the correction unit 203, and the output unit 204 can be a circuit board or a combination of multiple circuit boards for implementing the functions described above. In an embodiment of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processors; and (3) firmware stored in the memories that is executable by the processors.

[0275] It should be noted that the first verification unit 201 is used to implement Figure 5 In step S10 shown, the second verification unit 202 is used to implement Figure 5 In step S20 shown, the correction unit 203 is used to implement Figure 5 In step S30 shown, the output unit 204 is used to implement Figure 5 Therefore, the detailed description of the first verification unit 201 can refer to the embodiment of the above data reading method. Figure 5 For the description of step S10 shown in FIG. 1 , the specific description of the correction unit 203 can be referred to in the embodiment of the above data reading method. Figure 5 For the description of step S30 shown in FIG. 1 , the specific description of the output unit 204 can refer to the embodiment of the data reading method described above. Figure 5 In addition, the data reading device can achieve similar technical effects as the aforementioned data reading method, which will not be described in detail here.

[0276] Corresponding to the above-mentioned data writing method, at least one embodiment of the present disclosure further provides a data writing device, Figure 15 A schematic block diagram of a data writing device provided in at least one embodiment of the present disclosure.

[0277] For example, the data writing device is used to write data into the data storage device. For relevant contents of the data storage device, reference can be made to the relevant introduction of the data storage device in the aforementioned data reading method, and the repeated parts will not be repeated.

[0278] For example, Figure 15 As shown, the data writing device 300 includes: a first verification data generating unit 301 and a second verification data generating unit 302.

[0279] A first check data generating unit 301 is configured to generate first check data for data of a target row among the n rows to be written into the storage array based on an error checking method, wherein the first check data is used to check the target row using the error checking method;

[0280] The second check data generating unit 302 is configured to obtain a reference parity check vector using a parity check method according to the data to be written into the target row, wherein the reference parity check vector is used to perform parity check on each of the m columns.

[0281] For example, the first verification data generation unit 301 and the second verification data generation unit 302 may be dedicated hardware devices for implementing some or all of the functions of the first verification data generation unit 301 and the second verification data generation unit 302 described above. For example, the first verification data generation unit 301 and the second verification data generation unit 302 may be a circuit board or a combination of multiple circuit boards for implementing the functions described above. In an embodiment of the present application, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processors; and (3) firmware stored in the memories that is executable by the processors.

[0282] It should be noted that the first verification data generating unit 301 is used to implement Figure 9 In step S50 shown, the second verification data generating unit 302 is used to implement Figure 9 Therefore, the detailed description of the first verification data generating unit 301 can refer to the embodiment of the above data writing method. Figure 9 For the description of step S50 shown in FIG. 1 , and for the specific description of the second verification data generating unit 302 , reference can be made to the embodiment of the data writing method described above. Figure 9 In addition, the data writing device can achieve similar technical effects as the aforementioned data writing method, which will not be described in detail here.

[0283] Regarding this disclosure, the following points need to be explained:

[0284] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0285] (2) For the sake of clarity, the thickness and size of layers or structures in the drawings used to describe the embodiments of the present invention are exaggerated. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0286] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0287] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A data reading method, applied to a data storage device, wherein: The data memory stores n data and each data has a data width of m bits. The n data are sequentially arranged to form an n*m-bit data array, and the data array is correspondingly stored as a storage array in the data memory. The data reading method comprises: Performing a first check on m bits of data read from a target row in n rows of the storage array using an error checking method to obtain a first check result; In response to the first verification result indicating that the error occurring in the target row cannot be completely corrected, Using a parity check method, performing a second check on the data of each of the m columns read from the storage array to obtain a parity check result; Combining the first check result and the parity check result to obtain a second check result corresponding to the target row, wherein the number of correction bits in the second check result is greater than the maximum number of error correction bits that can be corrected by the error checking method; Taking the second verification result as the reading result, Wherein, m and n are both positive integers.

2. The data reading method according to claim 1, wherein: The data memory is provided with a first check array for the storage array, the first check array including n error check storage rows corresponding one-to-one to the n data, each of the n error check storage rows including p error check bits, and the p error check bits in the i-th row of the n error check storage rows are used to store error check data corresponding to the data in the i-th row of the data array; The data memory provides a parity storage row for the storage array and the first parity array, wherein the parity storage row includes m bits corresponding one-to-one to m columns of the storage array and p bits corresponding one-to-one to p columns of the first parity array, and the m bits and the p bits are used to store a reference parity vector having m+p bits corresponding to the m column of the data array and the p column of the first parity array, respectively. Wherein, p and i are both positive integers.

3. The data reading method according to claim 2, wherein: Performing a first check on m bits of data read from a target row in n rows of the storage array using an error checking method to obtain a first check result, comprising: Reading m bits of data stored in the target row and p bits of error check data corresponding to the target row to obtain a first data row; The first error checking method is used to perform the first check on the first data row to obtain the first check result.

4. The data reading method according to claim 3, wherein: Performing a second check on the data of each of the m columns read from the storage array using a parity check method to obtain a parity check result, including: Using a parity check method, a parity check operation is performed on the data bits of each of the m columns read from the storage array and the p columns read from the first check array to obtain a detection parity check vector having m+p bits; comparing the detection parity check vector with the reference parity check vector bit by bit to determine a plurality of difference bits between the detection parity check vector and the reference parity check vector; The parity check result is obtained according to the multiple difference bits.

5. The data reading method according to claim 4, wherein: Comparing the detected parity check vector with the reference parity check vector bit by bit, comprising: Perform a bitwise exclusive OR calculation on the detection parity check vector and the reference parity check vector.

6. The data reading method according to claim 4, wherein: In response to the first verification result indicating that an error occurring in the target row cannot be completely corrected, the first verification result includes the first data row, Combining the first check result and the parity check result to obtain a second check result corresponding to the target row includes: Determine, based on the parity check result, e potential error bits in the first data row, where positions of the e potential error bits are positions of the multiple difference bits, and e is an integer; In response to e being greater than a-1 and less than or equal to a preset correction threshold, a trial-and-error combination test is performed in combination with the e potential error bits, the error checking method and the first data row to obtain the second check result, wherein a is the maximum number of error detection bits that can be detected by the error checking method.

7. The data reading method according to claim 6, wherein: Performing a trial-and-error combination test in combination with the e potential error bits, the error checking method, and the first data row, including: determining at least one correction combination consisting of each a potential error bit among the e potential error bits, and performing the trial-and-error combination test on the at least one correction combination; The trial and error combination test includes sequentially performing a trial and error test on each selected correction combination, and the trial and error test includes: Flipping a data bits in the first data row corresponding to a potential error bits included in the selected correction combination to obtain an intermediate test data row corresponding to the first data row; Using the error checking method, the first check is performed on the intermediate test data row. In response to the intermediate test data row having at most a-1 bits with errors, the intermediate test data row is processed to obtain the second check result, and the trial-and-error combination test is stopped. In response to the intermediate test data row still having a bits with errors, the trial-and-error test is performed on the next correction combination.

8. The data reading method according to claim 7, wherein: The at least one correction combination performs the trial and error test in order from small to large data bit distances, The data bit distance of each correction combination is determined according to the distances between a potential erroneous bits included in each correction combination.

9. The data reading method according to claim 7, wherein: In response to at most a-1 bits of the intermediate test data row having errors, processing the intermediate test data row to obtain the second verification result, and stopping the trial-and-error combination test, comprising: In response to the intermediate test data row not having errors, taking the intermediate test data row as the second verification result and stopping the trial and error combination test; In response to an error in bit b in the intermediate test data row, the bit b is corrected using the error checking method, the correction result is used as the second check result, and the trial-and-error combination test is stopped, where b is a positive integer and is less than or equal to a-1.

10. The data reading method according to claim 1, wherein: Combining the first check result and the parity check result to obtain a second check result corresponding to the target row includes: Using the parity check result, determining a plurality of potential error bits having errors among the m bits of data read from the target row; In response to the number of the multiple potential error bits being equal to the maximum error detection bit number a detectable by the error checking method, m bits of data read from the target row are processed according to the multiple potential error bits to obtain the second checking result.

11. The data reading method according to claim 10, further comprising: In response to the number of the plurality of potential error bits being within a preset correction range, constructing at least one correction combination based on the plurality of potential error bits, wherein each correction combination consists of a selected number of potential error bits; performing trial and error combination testing on the at least one correction combination; The trial and error combination test includes sequentially performing a trial and error test on each selected correction combination, and the trial and error test includes: Performing flip processing on a data bits corresponding to a potential error bits included in the selected correction combination among the m bits of data read from the target row to obtain an intermediate test data row, Using the error checking method, performing the first check on the intermediate test data row to obtain a first intermediate check result, In response to the first intermediate verification result being a verification pass, obtaining the second verification result based on the first intermediate verification result, and stopping the trial and error combination test, In response to the first intermediate verification result being a verification failure, performing the trial and error test on a next correction combination.

12. The data reading method according to any one of claims 1 to 11, wherein: The error checking method is a single error correction and double error detection method.

13. The data reading method according to any one of claims 1 to 11, further comprising: In response to the first verification result indicating that the error occurring in the target row can be completely corrected, the first verification result is used as the read result.

14. A data writing method for writing data into a data storage device. The data memory is configured to store n data, and each of the n data has a data width of m bits. The n data are sequentially arranged to form an n*m-bit data array, and the n*m-bit data array is correspondingly stored as an n*m-bit storage array in the data memory. The data writing method comprises: generating first verification data for target data to be written into a target row of n rows of the storage array based on an error checking method, wherein the first verification data is used to verify the target row using the error checking method; A reference parity check vector is obtained based on the target data using a parity check method, wherein the reference parity check vector is used to perform a parity check on each of the m columns of the memory array.

15. The data writing method according to claim 14, wherein: The data memory is provided with a first check array for the storage array, wherein the first check array includes n error check storage rows corresponding to the n data one by one. The data memory provides a parity storage row for the storage array and the first check array, The data writing method further includes: Writing the target data into a target row in the storage array; Writing the first verification data into an error-checking storage row corresponding to the target row in the first verification array; The reference parity vector is written into the parity storage row.

16. The data writing method according to claim 15, wherein: Based on the target data, obtaining a reference parity check vector using a parity check method, comprising: Reading the current reference check vector stored in the parity check storage row, A bitwise exclusive OR operation is performed on the current reference parity check vector, the target data, and the first parity check data to obtain the reference parity check vector.

17. A soft error handling system comprising a data memory and a control circuit, wherein: The data memory stores n data and each data has a data width of m bits. The n data are sequentially arranged to form an n*m-bit data array, and the data array is correspondingly stored as a storage array in the data memory. The control circuit includes a controller and an error checker, The error checker is configured to perform a first check on m bits of data read from a target row in n rows of the storage array using an error checking method to obtain a first check result; The controller is configured to: In response to the first verification result indicating that the error occurring in the target row cannot be completely corrected, Using a parity check method, performing a second check on the data of each of the m columns read from the storage array to obtain a parity check result; Combining the first check result and the parity check result to obtain a second check result corresponding to the target row, wherein the number of correction bits in the second check result is greater than the maximum number of error correction bits that can be corrected by the error checking method; The second verification result is output as a reading result, Wherein, m and n are both positive integers.

18. The soft error handling system according to claim 17, wherein: The data memory is provided with a first check array for the storage array, the first check array including n error check storage rows corresponding one-to-one to the n data, each of the n error check storage rows including p error check bits, and the p error check bits in the i-th row of the n error check storage rows are used to store error check data corresponding to the data in the i-th row of the data array, The data memory provides a parity storage row for the storage array and the first parity array, wherein the parity storage row includes m bits corresponding one-to-one to m columns of the storage array and p bits corresponding one-to-one to p columns of the first parity array, and the m bits and the p bits are used to store reference parity vectors having m+p bits corresponding to the m columns of the data array and the p columns of the first parity array, respectively, where p and i are both positive integers.

19. The soft error handling system according to claim 18, wherein: The error checker performs a first check on m bits of data read from a target row in n rows of the storage array using an error check method, and when a first check result is obtained, the error checker includes the following steps: receiving m bits of data stored in the target row and p bits of error check data corresponding to the target row read from the storage array to obtain a first data row; Using the error checking method, determining whether there are errors in a bits among the m+p bits of the first data row, where a is the maximum number of error detection bits that can be detected by the error checking method; In response to an error in bit a of the first data row, outputting the first data row to the controller, wherein the first verification result includes the first data row, In response to errors in at most a-1 bits in the first data row, correction processing is performed on the first data row, and a correction result is output to the controller, wherein the first check result includes the correction result.

20. The soft error handling system according to claim 19, wherein: The controller performs a second check on the data of each of the m columns read from the storage array using a parity check method, and when a parity check result is obtained, the controller performs the following operations: Using a parity check method, a parity check operation is performed on the data bits of each of the m columns read from the storage array and the p columns read from the first check array to obtain a detection parity check vector having m+p bits; reading the reference parity vector from the parity storage row; comparing the detection parity check vector with the reference parity check vector bit by bit to determine a plurality of difference bits between the detection parity check vector and the reference parity check vector; The parity check result is obtained according to the multiple difference bits.

21. The soft error handling system according to claim 20, wherein: When the controller combines the first check result and the parity check result to obtain a second check result corresponding to the target row, the controller may perform the following operations: Determine, based on the parity check result, e potential error bits in the first data row, where positions of the e potential error bits are positions of the multiple difference bits, and e is an integer; In response to e being greater than a-1 and less than or equal to a preset correction threshold, a trial-and-error combination test is performed in combination with the e potential error bits, the error checking method, and the first data row to obtain the second check result.

22. The soft error handling system according to claim 21, wherein: When the controller performs a trial-and-error combination test combining the e potential error bits, the error checking method, and the first data row to obtain the second check result, the controller includes performing the following steps: determining at least one correction combination consisting of each a potential error bit among the e potential error bits, and performing the trial-and-error combination test on the at least one correction combination; The trial and error combination test includes sequentially performing a trial and error test on each selected correction combination, and the trial and error test includes: Flipping a data bits in the first data row corresponding to a potential error bits included in the selected correction combination to obtain an intermediate test data row corresponding to the first data row; sending the intermediate test data row to the error checker; In response to receiving the first flag signal sent by the error checker, stopping the trial and error combination test, and outputting the second verification result sent by the error checker, In response to receiving the second flag signal sent by the error checker, the trial and error test is performed on the next correction combination.

23. The soft error handling system according to claim 22, wherein: The error checker is further configured to: performing the first check on the intermediate test data row received from the controller using the error checking method, In response to the intermediate test data row not having errors, taking the intermediate test data row as the second verification result, and sending the second verification result and the first flag signal to the controller, In response to an error in bit b in the intermediate test data row, the bit b is corrected using the error checking method, a correction result is used as the second check result, and the second check result and the first flag signal are sent to the controller, wherein b is a positive integer and is less than or equal to a-1. In response to a bit still having an error in the intermediate test data row, the second flag signal is output to the controller.

24. The soft error handling system according to any one of claims 17 to 23, wherein: The control circuit further includes an error checking code generator, The error checking code generator is configured to generate first check data for target data of a target row among the n rows of the storage array to be written based on an error checking method, wherein the first check data is used to check the target row using the error checking method; The controller is further configured to obtain a reference parity check vector using a parity check method according to the target data, wherein the reference parity check vector is used to perform a parity check on each of the m columns.

25. The soft error handling system according to claim 24, wherein: The control circuit further includes an enable selector, an address selector, a read data selector and a write data selector, The enable selector is configured to, under the control of the controller, input an enable signal determined based on a data write request or a data read request, or an enable signal generated by the controller, to an enable port of the data memory; The address selector is configured to, under the control of the controller, input an address determined based on a data write request or a data read request, or an address generated by the controller, to an address port of the data storage; The read data selector is configured to, under the control of the controller, input data received from a read data port of the data memory or an intermediate test data row generated by the controller to the error checker; The write data selector is configured to, under the control of the controller, input the target data and the first check data, or the reference parity vector generated by the controller, to a write data port of the data memory.

26. A data reading device, used in a data storage device, wherein: The data memory stores n data and each data has a data width of m bits. The n data are sequentially arranged to form an n*m-bit data array, and the data array is correspondingly stored as a storage array in the data memory. The data reading device comprises: a first check unit configured to perform a first check on m bits of data read from a target row in n rows of the storage array using an error checking method to obtain a first check result; a second check unit configured to, in response to the first check result indicating that the error occurring in the target row cannot be completely corrected, perform a second check on the data of each of the m columns read from the storage array using a parity check method to obtain a parity check result; a correction unit configured to combine the first check result and the parity check result to obtain a second check result corresponding to the target row, wherein the number of correction bits in the second check result is greater than a maximum number of error correction bits that can be corrected by the error correction method; an output unit configured to output the second verification result as a reading result, Wherein, m and n are both positive integers.

27. A data writing device for writing data into a data storage device, The memory is configured to store n data, and the data width of each of the n data is m bits. The n data are sequentially arranged to form an n*m bit data array, and the n*m ​​bit data array is correspondingly stored as an n*m bit storage array in the data memory. The data writing device includes: a first check data generating unit configured to generate first check data for data of a target row among the n rows to be written into the storage array based on an error checking method, wherein the first check data is used to check the target row using the error checking method; The second check data generating unit is configured to obtain a reference parity check vector using a parity check method according to the data to be written to the target row, wherein the reference parity check vector is used to perform parity check on each of the m columns of the memory array.

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