Precharge circuit for sense amplifier circuit

Abstract

The present invention discloses a pre-charging circuit of a sensitive amplifier circuit, wherein the second end of a first MOS tube is connected to a power supply voltage, the first end of the first MOS tube is connected to a second end of a second MOS tube, and the first end of the second MOS tube is connected to a storage unit; the first end of the second MOS tube also feeds back the potential of the first end of the second MOS tube to the third end of the second MOS tube through a feedback circuit; the second end of an eighth MOS tube is connected to the first end of the second MOS tube, the first end of the eighth MOS tube is grounded, and the third end of the eighth MOS tube is connected to a second pre-charging signal; the first end of a seventh MOS tube is connected to a power supply voltage, the third end of the seventh MOS tube is connected to a second pre-charging signal, and the second end of the seventh MOS tube is connected to the third end of the second MOS tube; the third end of the first MOS tube is connected to a first pre-charging signal. The pre-charging circuit of the present invention adopts dual-phase charging, so that the feedback node can also be pre-charged at the same time in the pre-charging stage, thereby improving the charging speed, that is, improving the zero sensing speed.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuit design and manufacturing, in particular to a pre-charging circuit of a sensitive amplifier circuit. Background Art

[0002] Flash memory stores data information by storing charge on the floating gate. SA reads out the memory cell information by sensing the current of the memory cell under well-defined conditions. Under the read reference condition, a programmed memory cell draws a smaller current because of its high threshold voltage, while an erased memory cell draws a larger current because of its low threshold voltage. SA usually detects the memory cell information by comparing the memory cell current with the reference current. The reference current can be obtained by mirroring the reference cell current through a current mirror, or it can be generated by other reference current source circuits. Depending on whether the reference cell is used for comparison in the read circuit, SA can be divided into single-ended structure and differential structure. The sense amplifier is an important component of the memory. The sense amplifier senses the small signal on the bit line (BL) and reads the data stored in the memory cell by amplifying the small signal. In order to read the data stored in the memory cell, the bit line of the memory cell needs to be precharged.

[0003] The existing sense amplifier includes a pre-charging circuit, in which a MOS tube is used as a switch tube, such as Figure 1 As shown, the MOS M1 tube is connected to the power supply, the gate is connected to the precharge control signal pre, and the other end is connected to the bit line of the storage unit. When the precharge control signal controls the MOS tube to be turned on, the MOS tube outputs the current to the bit line through the M2 tube, so that the voltage of the bit line BL of the storage unit increases. Among them, the potential of point C is the feedback node potential, and the D node potential is fed back to point C through the inverter formed by M3 and M4. From the structure of the circuit, it can be seen that the potential of the feedback node C limits the precharge speed, making the rising rate of the bit line BL too slow, which will affect the 0 sensing speed. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a sensitive amplifier circuit which adopts two-phase charging and has a fast charging speed.

[0005] In order to solve the above problems, a pre-charging circuit of a sense amplifier circuit according to the present invention comprises:

[0006] The second end of the first MOS tube is connected to the power supply voltage, the first end of the first MOS tube is connected to the second end of the second MOS tube, and the first end of the second MOS tube is connected to the storage unit.

[0007] The first end of the second MOS tube also feeds back the potential of the first end of the second MOS tube to the third end of the second MOS tube through a feedback circuit.

[0008] The second end of the eighth MOS tube is connected to the first end of the second MOS tube, the first end of the eighth MOS tube is grounded, and the third end of the eighth MOS tube is connected to the second pre-charging signal.

[0009] A first terminal of the seventh MOS tube is connected to a power supply voltage, a third terminal of the seventh MOS tube is connected to a second pre-charge signal, and a second terminal of the seventh MOS tube is connected to a third terminal of the second MOS tube.

[0010] The third end of the first MOS tube is connected to a first pre-charge signal.

[0011] A further improvement is that the feedback circuit is an inverter, the input end of the inverter is connected to the first end of the second MOS tube, and the output tube of the CMOS inverter is connected to the third end of the second MOS tube.

[0012] A further improvement is that the inverter is a CMOS inverter, and the inverter and the second MOS tube form a clamping circuit.

[0013] A further improvement is that the storage unit includes a fifth MOS tube, a sixth MOS tube and a storage tube, and the third ends of the fifth MOS tube and the sixth MOS tube are connected to an external control signal to perform data reading and writing operations.

[0014] A further improvement is that it also includes an output circuit, wherein the first input end of the output circuit is connected to the first end of the first MOS tube and the second end of the second MOS tube, the second input end of the output circuit is connected to the reference voltage, and the output end outputs the storage signal of the storage unit.

[0015] A further improvement is that the output circuit is a comparator.

[0016] A further improvement is that the first pre-charge signal and the second pre-charge signal are valid at high level, and the second pre-charge signal is converted to high level before the first pre-charge signal is converted to high level. When the second pre-charge signal returns to low level, the first pre-charge signal is converted to high level, and the period of the first pre-charge signal being high level is greater than the period of the second pre-charge signal being high level.

[0017] The pre-charging circuit of the sense amplifier circuit of the present invention adopts dual-phase charging, so that the feedback node can also be pre-charged simultaneously in the pre-charging stage, thereby improving the charging speed, that is, improving the zero sensing speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The invention is a schematic diagram of the structure of a pre-charging circuit of an existing sensitive amplifier circuit.

[0019] Figure 2 The present invention provides a schematic diagram of the pre-charging circuit structure of a sensitive amplifier circuit.

[0020] Figure 3 3 is a waveform diagram of the first pre-charge signal Pre and the second pre-charge signal Pre2 of the present invention. DETAILED DESCRIPTION

[0021] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0022] It should be understood that the present invention can be implemented in different forms, and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layer and the zone may be exaggerated, and the same reference numerals represent the same elements from beginning to end. It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to " or "coupled to " other elements or layers, it can be directly on other elements or layers, adjacent to it, connected or coupled to other elements or layers, or there can be an intervening element or layer. On the contrary, when an element is referred to as "directly on ... ", "directly adjacent to ... ", "directly connected to " or "directly coupled to " other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, zones, layers and / or parts, these elements, components, zones, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0023] In order to make the technical means, creative features, objectives and effects achieved by the present invention easy to understand, the present invention is further described below with reference to specific diagrams.

[0024] A pre-charging circuit of a sensitive amplifier according to the present invention is as follows: Figure 2 As shown in the figure, M1 to M8 correspond to the first to eighth MOS tubes respectively. In this embodiment, the third MOS tube and the seventh MOS tube are PMOS, and the other MOS tubes are NMOS tubes. The connection relationship is that the drain end of the first MOS tube is connected to the power supply voltage VDD, the source end of the first MOS tube is connected to the drain end of the second MOS tube, and the source end of the second MOS tube is connected to the storage unit; the storage unit includes the fifth MOS tube, the sixth MOS tube and the bottom storage tube, and the gate ends of the fifth MOS tube and the sixth MOS tube are connected to the external control signal to perform data reading and writing operations. The gate end of the storage tube is connected to the word line signal VWL, and CBL is the bit line equivalent capacitance.

[0025] The source end of the second MOS tube also feeds back the potential of the source end of the second MOS tube to the gate end of the second MOS tube through a feedback circuit. The feedback circuit is a CMOS inverter composed of a third MOS tube and a fourth MOS tube, the input end of the inverter is connected to the source of the second MOS tube, and the source potential D of the second MOS tube is fed back to point C to form a clamping circuit.

[0026] The drain end of the eighth MOS tube is connected to the source end of the second MOS tube, the source end of the eighth MOS tube is grounded, and the gate end of the eighth MOS tube is connected to the second pre-charge signal Pre2.

[0027] The source terminal of the seventh MOS tube is connected to the power supply voltage VDD, the gate terminal of the seventh MOS tube is connected to the second precharge signal, the drain terminal of the seventh MOS tube is connected to the gate terminal of the second MOS tube, and the drain terminal of the second MOS tube is also connected to the power supply VDD to provide current for the storage unit.

[0028] The gate terminal of the first MOS tube is connected to a first pre-charge signal Pre.

[0029] In the figure, an output circuit is connected to the first MOS tube and the second MOS tube, and the output circuit is a comparator. The first input terminal + is connected to the source terminal of the first MOS tube and the drain terminal of the second MOS tube, the second input terminal - of the output circuit is connected to the reference voltage Vref, and the output terminal outputs the storage signal DOUT of the storage unit.

[0030] The first pre-charge signal Pre and the second pre-charge signal Pre2 are mutually inverted signals. That is, when the first pre-charge signal Pre is at a low level, the second pre-charge signal Pre2 is at a high level. Its waveform is as follows Figure 3 shown.

[0031] The above circuit adopts a dual-phase pre-charging. When the first MOS tube of the pre-charging tube charges the bit line through M2, the second pre-charging signal Pre2 first provides a high level. At this time, the eighth MOS tube is turned on, and the potential of point D is pulled to a low level, and the potential of point C is a high level at this time. The second MOS tube is turned on in advance. When the second pre-charging signal Pre2 returns to a low level, the first pre-charging signal Pre switches to a high level, the first MOS tube is turned on, and the seventh MOS tube is in a conducting state. The potential of point C is still a high level, and the second MOS tube remains in a conducting state. At this time, the first MOS tube charges the bit line through the second MOS tube. Because the feedback node C is also pre-charged in the pre-charging stage before the first pre-charging signal Pre arrives, the second MOS tube is turned on in advance, which will increase the 0 sensing speed. Therefore, the present invention improves the corresponding speed through two-phase pre-charging.

[0032] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A pre-charging circuit for a sense amplifier circuit, Features: The pre-charging circuit comprises: The second end of the first MOS tube is connected to the power supply voltage, the first end of the first MOS tube is connected to the second end of the second MOS tube, and the first end of the second MOS tube is connected to the storage unit; The first end of the second MOS tube also feeds back the potential of the first end of the second MOS tube to the third end of the second MOS tube through a feedback circuit; The second end of the eighth MOS tube is connected to the first end of the second MOS tube, the first end of the eighth MOS tube is grounded, and the third end of the eighth MOS tube is connected to the second pre-charging signal; A first terminal of the seventh MOS tube is connected to a power supply voltage, a third terminal of the seventh MOS tube is connected to a second pre-charging signal, and a second terminal of the seventh MOS tube is connected to a third terminal of the second MOS tube; The third end of the first MOS tube is connected to the first pre-charge signal; the feedback circuit is an inverter, the input end of the inverter is connected to the first end of the second MOS tube, and the output tube of the inverter is connected to the third end of the second MOS tube; The inverter is a CMOS inverter, and the inverter and the second MOS tube form a clamping circuit; the first pre-charge signal and the second pre-charge signal are valid at high level, and the second pre-charge signal is converted to high level before the first pre-charge signal is converted to high level. When the second pre-charge signal returns to low level, the first pre-charge signal is converted to high level, and the period of the first pre-charge signal being high level is greater than the period of the second pre-charge signal being high level.

2. The precharge circuit of the sense amplifier circuit according to claim 1, Features: The storage unit comprises a fifth MOS tube, a sixth MOS tube and a storage tube. The third ends of the fifth MOS tube and the sixth MOS tube are connected to an external control signal to perform data reading and writing operations.

3. The precharge circuit of the sense amplifier circuit according to claim 1, Features: It also includes an output circuit, wherein a first input end of the output circuit is connected to a first end of the first MOS tube and a second end of the second MOS tube, a second input end of the output circuit is connected to a reference voltage, and an output end outputs a storage signal of the storage unit.

4. The precharge circuit of the sense amplifier circuit according to claim 3, Features: The output circuit is a comparator.

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