Selective inhibition of memory

Abstract

The present application relates to selective inhibition of memory. An example device may include a memory array and control circuitry. The memory array may include a first portion including a first plurality of memory cells. The memory array may further include a second portion including a second plurality of memory cells. The control circuitry may be configured to designate the first portion as active in response to determining that the first portion passes a performance test. The control circuitry may be configured to designate the second portion as inactive in response to determining that the second portion fails the performance test.

Description

Technical Field

[0001] The present disclosure generally relates to apparatus and methods related to selective inhibition of memory. Background Art

[0002] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states in the memory device. For example, a binary device has two states, typically represented by a logical "1" or a logical "0." In other systems, more than two states can be stored. To access stored information, components of the electronic device can read or sense the states stored in the memory device. To store information, components of the electronic device can write or program states in the memory device.

[0003] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can maintain its stored logic state for a long period of time even in the absence of an external power source. Volatile memory cells may lose their stored state over time unless periodically refreshed by an external power source.

[0004] Generally speaking, improving memory devices may include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Summary of the Invention

[0005] An embodiment of the present disclosure provides a device for selective inhibition of a memory, comprising: a memory array comprising: a first portion comprising a first plurality of memory cells; and a second portion comprising a second plurality of memory cells; and a control circuit system configured to: designate the first portion as active in response to determining that the first portion passes a performance test; and designate the second portion as inactive in response to determining that the second portion fails the performance test.

[0006] Another embodiment of the present disclosure provides a device for selective inhibition of a memory, comprising: a memory array comprising: a plurality of portions, each comprising a plurality of memory cells; and a control circuit system of a system controller coupled to the first portion and the second portion, wherein the control circuit system is configured to: receive results of a performance test performed on each of the plurality of portions; designate any portion of the plurality of portions that fails the performance test as inactive using a first fuse setting; and designate any portion of the plurality of portions that passes the performance test as active using a second fuse setting.

[0007] Yet another embodiment of the present disclosure provides a method for selective inhibition of a memory, comprising: performing a performance test on a memory array indicated as having a first capacity and a first density, the memory array comprising a plurality of portions, the plurality of portions comprising: a first portion comprising a first plurality of memory cells; and a second portion comprising a second plurality of memory cells; designating each of the plurality of portions as active or inactive in response to the performance test, wherein designating the plurality of portions comprises: designating the first portion as active in response to determining that the first portion exceeds a performance test threshold; and designating the second portion as inactive in response to determining that the second portion does not exceed the performance test threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of an apparatus in the form of a computing system including a memory device according to several embodiments of the present disclosure.

[0009] Figure 2 Methods for selective inhibition of memory according to several embodiments of the present disclosure are described.

[0010] Figure 3A A memory array having multiple levels and corresponding lookup tables is described according to several embodiments of the present disclosure.

[0011] Figure 3B A memory array and corresponding lookup table after remapping according to several embodiments of the present disclosure are illustrated. DETAILED DESCRIPTION

[0012] An example device may include a memory array and control circuitry. The memory array may include a first portion including a first plurality of memory cells. The memory array may further include a second portion including a second plurality of memory cells. The control circuitry may be configured to designate the first portion as active in response to determining that the first portion passes a performance test. The control circuitry may be further configured to designate the second portion as inactive in response to determining that the second portion fails the performance test.

[0013] The manufacturing trend of memory arrays is to increase density and reduce costs. Various 3-dimensional (3-D) memory devices (e.g., 3D NAND and / or 3D DRAM) include stacked configurations. 3D cross-point memory devices (e.g., bare chips) include, for example, multiple levels (e.g., layers) in a stacked configuration, which can increase density and reduce costs. An example 3D cross-point memory device (such as a 3D XPoint device) may include an array of memory cells, each memory cell including a selection device and a storage material connected in series between a bit line and a corresponding word line. Some 3D cross-point memory devices may include an array of memory cells, each memory cell including a single material (e.g., a chalcogenide) that can act as both a selection device and a storage device. Such a cell may be referred to as a self-selected memory (SSM) cell. When such a 3D cross-point memory device is manufactured, it is typically tested to determine whether the device and / or internal memory array meets thresholds in various performance criteria. Such testing is referred to herein as "performance testing" or simply "testing." Performance testing can be used to determine the grade and / or price of a memory device before it is sold.

[0014] In various examples, each layer of the array is tested (e.g., sequentially). Performance testing of the array layers may include testing structural aspects of the layers and / or electrical aspects of the layers. Testing may include performing a plurality of different subtests on each layer, or performing a plurality of different subtests using each layer. Some of these subtests may allow for determining whether a given layer is functional. Some of these subtests may allow for determining the speed of a given layer. Some of these subtests may allow for determining the grade (e.g., quality and / or efficiency) of a given layer of the memory device.

[0015] For example, testing may include performing a bit error rate (BER) subtest on a layer to determine the BER associated with the layer, among other procedures. The determined BER associated with the layer may be compared to a threshold (e.g., desired) BER. In some cases, if the determined BER is above the threshold BER, the layer may be referred to as failing the BER subtest of the performance test. In other words, the layer did not exceed the BER subtest threshold. Alternatively, if the determined BER is below the threshold BER, the layer may be referred to as passing the BER subtest of the performance test (e.g., the layer exceeded the BER subtest threshold). As previously discussed, testing may include performing multiple different subtests on each layer, or performing multiple different subtests using each layer. Whether a particular layer passes or fails the performance test depends on the results of the individual subtests and may be manufacturer-specific and / or customer-specific.

[0016] Typically, if only a single array level of an entire memory device (e.g., a die) fails a performance test and all other array levels pass the performance test, the memory device is designated as having failed a performance test. In this case, the failed die may be discarded. Consequently, the already time-consuming and expensive nature of memory device manufacturing becomes even more costly.

[0017] Performance testing can go beyond simply determining whether a particular layer passes or fails (or whether a memory device should be sold or discarded). For example, memory devices can be graded based on their quality and priced accordingly for sale. Typically, the grade given to a memory device is determined by the lowest performing layer within it. For example, if an array contains one layer graded as "Tier 2" and all other layers graded as "Tier 1" (a higher grade than Tier 2), the array as a whole may be graded as "Tier 2." This grading practice can inhibit manufacturer yields for highly graded arrays, particularly as the number of layers per array increases.

[0018] Embodiments of the present disclosure address these issues by selectively inhibiting the rescue of a memory array. Thus, embodiments herein are able to "re-claim" layers that might otherwise have been discarded. In some embodiments, for example, layers that pass a performance test are designated as "active," and layers that fail a performance test are designated as "inactive." By doing so, embodiments of the present disclosure can avoid discarding an array when less than all of the entire array is not performing or performing poorly. Additionally, embodiments of the present disclosure can rank a memory array based on less than all of the layers in the memory array (e.g., the active layers), thereby allowing for higher rankings than previous approaches.

[0019] In some embodiments, for example, the density of the array can be updated (e.g., downgraded) based on the active or inactive designation of a layer. The addresses of the inactive layer can be re-scrambled so that the logical addresses only point to the physical addresses of the active layer. It should be noted that while specific examples of layers and 3D cross-point arrays are discussed herein, embodiments of the present disclosure are not limited thereto. Rather, the present disclosure relates to other memory arrays, and ranges of physical addresses that do not correspond to specific instances of layers can be designated as "active" or "inactive."

[0020] Figure 1 is a block diagram of an apparatus in the form of a computing system 100 including a memory device 128, according to several embodiments of the present disclosure. As used herein, memory device 128, controller 140, and memory array 130 may also be individually considered "apparatus."

[0021] In this example, system 100 includes an external processing resource 126 coupled (eg, connected) to a memory device 128, which includes a memory array 130. Note that Figure 1 While the example illustrated in includes a single memory device 128, a system according to the present disclosure may include multiple memory devices coupled to an external processing resource 126. The external processing resource 126 may be a host system such as a personal laptop computer, desktop computer, digital camera, smartphone, or memory card reader, as well as various other types of hosts. The external processing resource 126 may include a system motherboard and / or baseboard, and may include several processing resources (e.g., one or more processors, microprocessors, or some other type of control circuitry). The system 100 may include a separate integrated circuit, or both the external processing resource 126 and the memory device 128 may be on the same integrated circuit. The system 100 may be, for example, a server system and / or a high performance computing (HPC) system and / or a portion thereof. In some embodiments, the system 100 may be a solid state drive (SSD) in which the external processing resource 126 is a system controller coupled to multiple memory devices 128. The external processing resource 126 may communicate with the host. In some embodiments, the external processing resource 126 may be, for example, a host processor in which the controller 140 is an on-die controller. Although Figure 1 The examples shown in the drawings illustrate a system having a von Neumann architecture, but embodiments of the present disclosure may be implemented in non-von Neumann architectures, which may not include one or more components typically associated with a von Neumann architecture (e.g., a CPU, an ALU, etc.).

[0022] For clarity, system 100 has been simplified to focus on features that are particularly relevant to the present disclosure. For example, memory array 130 may be a self-select memory (SSM) array, a 3-dimensional (3-D) X-point memory array, an STT RAM array, a PCRAM array, an RRAM array, a NAND flash array, and / or a NOR flash array. Array 130 may include memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as data lines or digit lines). Although in Figure 1 A single array 130 is shown in FIG, but embodiments are not limited thereto. For example, memory device 128 may include several arrays 130 (eg, several groups of NAND flash cells, etc.).

[0023] Memory device 128 includes address circuitry 142 to latch address signals provided by I / O circuitry 144 via bus 135 (e.g., an I / O bus). Address signals are received by address circuitry 142 and decoded by row decoder 146 and column decoder 137 to access memory array 130. Address signals may also be provided to controller 140 (e.g., via address circuitry 142 and / or via control bus 131). Data may be read from memory array 130 by sensing voltage and / or current changes on data lines using sensing circuitry (not illustrated). The sensing circuitry may read and latch a page (e.g., a row) of data from memory array 130. I / O circuitry 144 may be used for bidirectional data communication with external processing resources 126 via I / O bus 135. Write circuitry 148 is used to write data to memory array 130.

[0024] Memory controller 140 (which may be referred to as group control logic and / or a sequencer) decodes signals provided by control bus 131 from external processing resources 126. These signals may include chip enable signals, write enable signals, and address latch signals used to control operations performed on memory array 130, including data read, data write, and data erase operations. In various embodiments, controller 140 is responsible for executing instructions from external processing resources 126 and sequencing accesses to array 130. Memory controller 140 may be a state machine, a sequencer, or some other type of controller.

[0025] The memory controller 140 may control the operation (e.g., reading, writing, rewriting, refreshing, discharging) of the memory cells through various components (e.g., row decoder 146, column decoder 137, etc.). In some cases, one or more of the row decoder 146 and the column decoder 137 may be co-located with the controller (e.g., memory controller) 140. The memory controller 140 may generate row and column address signals in order to activate the desired access lines and sense lines. The memory controller 140 may also generate and control various voltages or currents used during operation of the memory array. In general, the magnitude, shape, polarity, and / or duration of the applied voltages or currents discussed herein may be adjusted or varied and may be different for the various operations discussed when operating the memory array. In addition, one, multiple, or all memory cells within the memory array 130 may be accessed simultaneously; for example, multiple or all cells of the memory array 130 may be accessed simultaneously during a reset operation in which all memory cells or groups of memory cells are set to a single logical state. The memory controller 140 may include circuitry (e.g., control circuitry) that, when Figure 1 141. The designator / remapper 141 may perform various processes as described herein. It should be noted that although Figure 1 , the designator / remapper 141 is shown as being included in the memory controller 140 , but embodiments of the present disclosure are not limited thereto.

[0026] The memory array 130 may include a first portion 122-1 of a plurality of memory cells and a second portion 122-2 of a plurality of memory cells. The first portion 122-1 and the second portion 122-2 are sometimes referred to herein as "first level 122-1" and "second level 122-2," respectively. Although Figure 1 The example shows two memory levels, but other configurations may include any number of levels. In some embodiments, one or more of the memory levels may include optional memory cells including variable resistance (e.g., chalcogenide) materials. In other embodiments, one or more of the memory levels 122-2 and 122-1 may include FeRAM cells including ferroelectric materials. In still other embodiments, one or more of the memory levels 122-2 and 122-1 may include CBRAM cells including metal oxide or chalcogenide materials. Chalcogenide materials may, for example, include chalcogenide glass, such as an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some embodiments, chalcogenide materials primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as SAG alloys. As will be appreciated by those skilled in the art, the first level 122-1 may be positioned above the substrate, and the second level 122-2 may be positioned on top of the first level 122-2, but the embodiments of the present disclosure are not limited in this regard.

[0027] Cross-point architectures can provide relatively high-density data storage at a lower production cost than some other memory architectures. For example, a memory array having a cross-point architecture can have memory cells with reduced area and, therefore, can support increased memory cell density compared to some other architectures.

[0028] Figure 2 Method 250 for selective inhibition of memory according to several embodiments of the present disclosure is described. Method 250 may be implemented by, for example, a control circuit system (e.g., as previously described in conjunction with Figure 1 In some embodiments, the control circuitry is located on the die of the memory array. In some embodiments, the control circuitry is included in a controller, such as a system controller or a memory controller (e.g., similar to the controller described previously in conjunction with Figure 1 The memory controller 140 described herein may be a memory controller 140. For example, the controller may execute a set of codes to control the functional elements of the device to perform the functions described below. The controller may use hardware and / or firmware to perform aspects of the functions described below.

[0029] At 252, method 250 may include performing a performance test on a memory array indicated as having a first (e.g., expected) capacity and a first (e.g., expected) density, the memory array comprising a plurality of portions, including a first portion comprising a first plurality of memory cells and a second portion comprising a second plurality of memory cells. As previously discussed, the first portion may refer to a first level of the memory array, and the second portion may refer to a second level of the memory array, though it should be noted that embodiments herein are not limited in this regard. In some embodiments, for example, a portion may refer to a region of the memory array. For example, some embodiments may include selectively inhibiting a portion of less than one level of the memory array.

[0030] A memory array may be expected to have a specific capacity. Capacity refers to storage space that can be measured in bytes. For example, an array may be manufactured such that, if manufactured as intended, it would have a capacity of 256 gigabytes (Gb) (e.g., a first capacity). A memory array may be expected to have a specific density. Density refers to the amount of capacity in a given area or space. For example, an array may be manufactured such that, if manufactured as intended, it would have a density of 0.62 Gb per square millimeter.

[0031] As previously discussed, the array may be subjected to performance testing. Performance testing may be performed in conjunction with the manufacture of the array (e.g., after manufacture is complete). Performance testing may include performing a plurality of subtests on or using the array. The subtests may include, for example, high temperature testing, low temperature testing, temperature cycling testing, power cycling testing, shock testing, vibration testing, BER testing, and / or ongoing reliability testing, among others. The results of the performance testing may be communicated to and received by the control circuitry described herein.

[0032] At 254, method 250 may include designating each of the plurality of sections as active or inactive in response to the performance test. If a level exceeds a performance test threshold, the control circuitry may designate it as active. If a level does not exceed the performance test threshold, the control circuitry may designate it as inactive. Designating a level as inactive may include placing the level in a suppressed state. Placing a level in a suppressed state may include modifying (or maintaining) a fuse setting for a level designated as inactive. Designating a level as active may include modifying (or maintaining) a fuse setting for a level indicated as active such that the fuse setting for the active level is different from the fuse setting for the inactive level. Thus, designation may include designating a first section as active at 256 in response to determining that the first section exceeds a performance test threshold, and designating a second section as inactive at 258 in response to determining that the second section does not exceed the performance test threshold.

[0033] Whether a layer exceeds or does not exceed a performance test threshold may depend on the number and / or type of performance subtests that the layer passes or fails. In some embodiments, not exceeding a performance test threshold may depend on the extent to which the layer fails one or more of the performance subtests. When indicating a layer as inactive, the control circuitry may remap an address (e.g., a portion of a physical address) corresponding to the second portion (e.g., a layer address corresponding to the second layer) so that the address is mapped to the first portion. Remapping is further described below in conjunction with FIG3 .

[0034] Once the control circuitry designates a layer as active or inactive, method 250 may include modifying information describing the array. For example, in some embodiments, a memory array may be indicated as having a reduced (e.g., second) capacity. The reduced capacity refers to the capacity of the layer designated as active. If a layer of the array is designated as inactive, the array may no longer be indicated as having the first capacity discussed above. For example, an array may be manufactured such that, if manufactured as intended, it has a capacity of 256Gb (e.g., the first capacity). However, if a 64Gb layer of the array is designated as inactive, the reduced (e.g., second) capacity may be indicated as 192Gb.

[0035] Method 250 may include indicating the memory array as having a reduced (e.g., second) density in response to designating the plurality of portions. Reduced density refers to the amount of capacity of the layers designated as active in a given area or space. If a layer of the array is designated as inactive, the array may no longer be indicated as having the intended (e.g., first) density discussed above. For example, an array may be manufactured such that, if manufactured as intended, it would have a density of 0.62 Gb / mm². However, if half of the layers of the array are designated as inactive, the reduced (e.g., second) density may be indicated as 0.31 Gb / mm².

[0036] Method 250 may include ranking a memory array based on a subset of portions of the memory array designated as active. In contrast to previous methods in which ranking may be based on all layers of the array, embodiments herein may rank an array based on less than all layers of the array (e.g., only active layers). Typically, in previous methods, the rank assigned to a memory array is determined by the lowest performing layer therein. For example, if an array includes one layer rated "Tier 2" and all other layers rated "Tier 1" (a higher level than Tier 2), the array as a whole may be ranked "Tier 2." According to embodiments herein, the lowest performing layer (or layers) may be designated as inactive and ranking may not take into account the lowest performing layer (or layers). Thus, in the above example, the "Tier 2" layer may be designated as inactive, thereby causing the remainder of the layers (and therefore the array) to be designated "Tier 1."

[0037] For example, the capacity, density, and / or tier of a memory array may be designated based on various external factors, such as sales, revenue, customer needs, and / or customer preferences. In some embodiments, if a higher-tier array is preferred for increased capacity and / or density, then the performance test threshold for designating a tier as inactive is decreased. In some embodiments, if an array with increased capacity and / or density is preferred for a higher tier, then the performance test threshold for designating a tier as inactive is increased. Thus, method 250 may include assigning a reduced (e.g., second) density and a higher (e.g., first) tier or a higher (e.g., expected) density and a lower (e.g., second) tier based on a subset of the plurality of portions of the memory array designated as active.

[0038] Figure 3A A memory array 330 having multiple levels and corresponding lookup tables 360 is illustrated according to several embodiments of the present disclosure. Figure 3B A memory array and corresponding lookup table after remapping according to several embodiments of the present disclosure are illustrated. Figure 3A and 3B May be cumulatively referred to herein as "Figure 3."

[0039] The memory array 330 may be part of a 3D architecture in which several layers are stacked vertically on top of each other. The example array 330 shown in FIG3 includes four layers: layer 0 322-0, layer 1 322-1, layer 2 322-2, and layer 322-3 (referred to herein as layer 0, layer 1, layer 2, and layer 3, respectively). It should be noted that embodiments of the present disclosure do not limit the memory array to a particular type, let alone a particular number of layers.

[0040] Figure 3AThe memory array 330 and its corresponding table 360 are illustrated before any of levels 0, 1, 2, and 3 are designated as active or inactive. As shown in table 360, each level 0, 1, 2, and 3 corresponds to a respective level address. Level address 00 corresponds to level 0, level address 01 corresponds to level 1, level address 10 corresponds to level 2, and level address 11 corresponds to level 3. The logical address received in association with a command from the controller may include a level address that may be associated with a physical address range (e.g., one of levels 0, 1, 2, and 3).

[0041] In an example, array 330 is subjected to a performance test, the results of which cause the control circuitry to indicate level 1 and level 2 as inactive, and the control circuitry to indicate level 0 and level 3 as active. Figure 3B Table 362 shown in includes the remapped addresses after designating level 1 and level 2 as inactive.

[0042] like Figure 3B As shown in , layer address 00 still corresponds to layer 0, and layer address 11 still corresponds to layer 3. However, layers 1 and 2 have been remapped. Figure 3B As shown in FIG, level address 11 now corresponds to level 1 in addition to level 3, and level address 00 now corresponds to level 2 in addition to level 0. In some embodiments, the remapping is stored in non-volatile memory. In some embodiments, the remapping is stored in a controller (e.g., previously associated with Figure 1 The controller 140 may be configured to store the remapped data in a dedicated fuse register within the controller 140 as described above. For example, the remapped data may be written to a fuse table. In some embodiments, the fuses may be set (e.g., loaded) after power-up. In some embodiments, the controller may read the remap data from the array at power-up to determine the remapped data for the array.

[0043] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, embodiments from two or more of the methods described may be combined.

[0044] The devices discussed herein, including memory devices, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, and the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a subregion of the substrate can be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0045] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred" or "advantageous" over other examples. For the purpose of providing an understanding of the described techniques, the detailed description includes specific details. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0046] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0047] The various illustrative blocks and modules described in connection with the present disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or another programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a digital signal processor (DSP) and a microprocessor, a combination of multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0048] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0049] In the preceding detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustration specific examples. In the drawings, like numerals describe substantially similar components throughout the several views. Other examples may be utilized, and structural, logical, and / or electrical changes may be made, without departing from the scope of this disclosure.

[0050] The figures herein follow a numbering convention in which the first one or more digits correspond to the figure number, and the remaining digits identify the elements or components in the figure. Similar elements or components between different figures can be identified by using similar numerals. As will be appreciated, the elements shown in the various embodiments herein can be added, exchanged, and / or removed to provide several additional embodiments of the present disclosure. In addition, as will be appreciated, the proportions and relative scales of the elements provided in the figures are intended to illustrate embodiments of the present disclosure and should not be understood in a limiting sense.

[0051] As used herein, "a" or "an" or "several" things may refer to one or more of such things. "Multiple" things mean two or more. As used herein, the term "coupled" may include electrically coupled, directly coupled, and / or directly connected without intervening elements (e.g., by direct physical contact), or indirectly coupled and / or connected with intervening elements. The term coupled may further include two or more elements that cooperate or interact with each other (e.g., as in a cause-and-effect relationship).

[0052] Although specific examples have been illustrated and described herein, it will be appreciated by those skilled in the art that arrangements calculated to achieve the same results may be substituted for the specific embodiments shown. This disclosure is intended to cover modifications or variations of one or more embodiments of the present disclosure. It should be understood that the above description has been presented by way of illustration and not limitation. The scope of one or more embodiments of the present disclosure should be determined with reference to the appended claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A device for selective inhibition of a memory, comprising: A memory array (130, 330) comprising: a first portion (122-1) comprising a first plurality of memory cells; and a second portion (122-2) comprising a second plurality of memory cells; and A control circuit system (141) configured to: designating the first portion (122-1) as active in response to determining that the first portion (122-1) passes the performance test; and The second portion (122-2) is designated as inactive in response to determining that the second portion (122-2) fails the performance test.

2. The apparatus of claim 1, wherein the control circuitry (141) is configured to remap addresses corresponding to the second portion (122-2) such that the addresses map to the first portion (122-1).

3. The apparatus of claim 1 , wherein the first portion ( 122 - 1 ) is a first level ( 122 - 1 ) of the memory array ( 130 , 330 ) and wherein the second portion ( 122 - 2 ) is a second level ( 122 - 2 ) of the memory array ( 130 , 330 ) .

4. The apparatus of claim 1, wherein the control circuitry (141) is configured to place the second portion (122-2) in an inhibited state in response to the determination that the second portion (122-2) fails the performance test.

5. The apparatus of claim 1, wherein the control circuitry (141) is included in a system controller coupled to the first portion (122-1) and the second portion (122-2).

6. The apparatus of claim 1, wherein the control circuitry (141) is on-die of the memory array (130, 330).

7. The apparatus of any one of claims 1 to 6, wherein the control circuitry (141) is configured to set a circuit fuse to a first setting to designate the second portion (122-2) as inactive.

8. The apparatus of claim 7, wherein the control circuitry (141) is configured to set a circuit fuse to a second setting to designate the first portion (122-1) as active.

9. An apparatus for selective inhibition of a memory, comprising: A memory array (130, 330) comprising: a plurality of sections (122-1, 122-2), each comprising a plurality of memory cells; and Control circuitry (141) of a system (100) controller (140) coupled to the first portion (122-1) and the second portion (122-2), wherein the control circuitry (141) is configured to: receiving results of a performance test performed on each of the plurality of portions (122-1, 122-2); designating any of the plurality of sections (122-1, 122-2) that fail the performance test as inactive using a first fuse setting; and Any portion of the plurality of portions (122-1, 122-2) that passes the performance test is designated as active using a second fuse setting.

10. The apparatus of claim 9, wherein the control circuitry (141) is configured to designate any of the plurality of portions (122-1, 122-2) as inactive without designating the memory array (130, 330) as inactive.

11. The apparatus of claim 9 , wherein the control circuitry ( 141 ) is configured to remap any address corresponding to any portion of the plurality of portions ( 122 - 1 , 122 - 2 ) designated as inactive so that the address maps to a portion of the plurality of portions ( 122 - 1 , 122 - 2 ) designated as active.

12. The apparatus of claim 11, wherein the control circuitry (141) is configured to write the remapping to a fuse table.

13. A method (250) for selective inhibition of a memory, comprising: A performance test is performed on a memory array (130, 330) indicated as having a first capacity and a first density, the memory array (130, 330) including a plurality of portions (122-1, 122-2), the plurality of portions (122-1, 122-2) including: a first portion (122-1) comprising a first plurality of memory cells; and a second portion (122-2) comprising a second plurality of memory cells; designating each of the plurality of sections (122-1, 122-2) as active or inactive in response to the performance test, wherein designating the plurality of sections (122-1, 122-2) comprises: designating the first portion (122-1) as active in response to determining that the first portion (122-1) exceeds a performance test threshold; and The second portion (122-2) is designated as inactive in response to determining that the second portion (122-2) does not exceed the performance test threshold.

14. The method (250) of claim 13, wherein performing the performance test comprises determining a bit error rate associated with each of the plurality of portions (122-1, 122-2).

15. The method (250) of claim 14, wherein the method (250) includes determining that the second portion (122-2) does not exceed the performance test threshold in response to determining that the determined bit error rate associated with the second portion (122-2) exceeds a bit error rate threshold.

16. The method (250) of any one of claims 13 to 15, wherein the method (250) includes indicating the memory array (130, 330) as having a second capacity in response to specifying the plurality of portions (122-1, 122-2).

17. The method (250) of any one of claims 13 to 15, wherein the method (250) includes indicating the memory array (130, 330) as having a second density in response to specifying the plurality of portions (122-1, 122-2).

18. The method (250) of any one of claims 13 to 15, wherein the method (250) includes rating the memory array (130, 330) based on a subset of the plurality of portions (122-1, 122-2) of the memory array (130, 330) that is designated as active.

19. The method (250) of claim 18, wherein the method (250) includes assigning a ranking of one of the following based on the subset of the plurality of portions (122-1, 122-2) of the memory array (130, 330) designated as active: the first density and second level; and Second density and first level.

20. The method (250) of any one of claims 13 to 15, wherein the method (250) comprises setting the performance test threshold based on customer preferences.

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