Heat dissipation structure and method for chip stacked airtight ceramic package

Abstract

A heat dissipation structure for a chip stacked airtight ceramic package comprises an overall package structure, a T-shaped cover plate, and a thermally conductive adhesive layer. The T-shaped cover plate comprises a boss area and a welding area, wherein the T-shaped cover plate is connected to the overall package structure via the welding area, the boss area being positioned corresponding to the chip within the overall package structure, and a thermally conductive adhesive layer being applied between the boss area and the chip. The thermally conductive adhesive layer is a resin adhesive having a thermal conductivity better than 2W / mK. The boss area is slightly smaller than the chip, and the gap between the boss area and the chip is 20μm to 100μm. The surface roughness of the boss area is less than 20μm. The boss thickness is not less than 0.5mm, and the chamfer radius of the boss area is not less than 0.2mm. The heat dissipation method of the present invention can provide an additional heat dissipation channel for the chip stack structure, and the heat dissipation channel is a metal cover plate, with the outer side of the cover plate being exposed to the external environment. Compared with a heat dissipation structure that relies solely on the bottom chip to the ceramic housing, the heat dissipation method has a stronger heat dissipation capability.

Description

Technical Field

[0001] The invention relates to a heat dissipation structure and method for chip stacking airtight ceramic packaging, belonging to the field of chip stacking packaging. Background Art

[0002] With the rapid development of information technology, data volumes are exploding, driving ever-increasing demands on memory capacity and integration. However, single-chip memory integrated circuits are constrained by Moore's Law, preventing further capacity increases while maintaining the same footprint and volume. Therefore, the chips within memory integrated circuits must be stacked in the Z direction, preventing horizontal expansion of the memory integrated circuit and minimizing the overall footprint of the device.

[0003] There are two packaging methods for bare chip stacking, one is chip stacking plastic packaging, and the other is chip stacking ceramic airtight packaging. After the chip stacking is bonded and the chip leads are bonded, the chip stacking plastic packaging will use plastic filler to fill the gaps between the chip, bonding wire and structure. After the plastic encapsulation material is cured, it plays the role of support, isolation and insulation. The plastic encapsulation material is generally a resin, which can play the role of fixing, supporting, protecting and dissipating heat for the chips and bonding wires inside the integrated circuit in a conventional environment. Therefore, the chip stacking plastic packaging can be suitable for stacking more layers of chips. However, due to the problems of moisture absorption and thermal adaptation of resin-based plastic encapsulation materials, it is easy to absorb moisture and crack in a humid environment or a thermal alternation environment, or the stress matching between the chip and the bonding wire is poor, resulting in cracking of the chip or bonding wire. Therefore, plastic packaging is not suitable for more harsh environments for the time being, and its reliability is slightly lower.

[0004] Chip stacked ceramic packaging requires stacking the chips in a hollow ceramic housing. After chip bonding and wire bonding, a metal cover is needed to seal the ceramic cavity, so its reliability is relatively high. The interior of the ceramic package is a nitrogen environment. Except for the bottom chip, other chips and bonding wires do not require other materials for contact support. However, since the upper chip in the chip stacked ceramic package is only bonded to the top of the bottom chip and does not contact other structures, heat can only be dissipated in the direction of the bottom chip-ceramic housing. Chip stacked ceramic airtight packaging can achieve high reliability, but due to the structural characteristics of ceramic airtight packaging, a solution needs to be proposed for chip heat dissipation. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: to overcome the shortcomings of the existing technology and provide a heat dissipation structure of a chip stacked airtight ceramic package, including an overall package structure, a T-shaped cover plate, and a thermally conductive adhesive layer; the T-shaped cover plate includes a boss area and a welding area, wherein the T-shaped cover plate is connected to the overall package structure through the welding area, the position of the boss area corresponds to the chip in the overall package structure, and a thermally conductive adhesive layer is applied between the boss area and the chip; wherein the thermally conductive adhesive layer is a resin adhesive with a thermal conductivity better than 2W / mK; the size of the boss area is slightly smaller than the size of the chip, and the gap between the boss area and the chip is 20μm to 100μm; the surface roughness of the boss area is less than 20μm; the boss thickness is not less than 0.5mm, and the chamfer radius of the boss area is not less than 0.2mm.

[0006] The purpose of the present invention is achieved through the following technical solutions:

[0007] (1) Based on the ceramic shell structure and the chip stacking structure, a "T"-shaped airtight packaging metal cover is designed. The metal cover is made of Kovar alloy and its surface is nickel-plated. A boss slightly smaller than the chip size is designed in the center of the cover. The boss size is required to be 2mm to 3mm smaller than the chip on each side. The purpose is to leave enough space for the thermal conductive glue to overflow between the boss and the chip surface when they are in contact, so as to prevent the thermal conductive glue from overflowing onto the pads or bonding wires on the chip surface. In addition, the boss height, the inner / outer chamfers of the boss structure, the thickness of other parts of the cover, the roughness of the lower surface of the boss, and the coating structure of the cover surface are required;

[0008] (2) According to the ceramic shell structure and the overall thickness of the chip stack, the cover plate is designed to match. The height of the boss in the center of the cover plate is required to just meet the gap between the lower surface of the boss and the upper surface of the top chip after the cap is sealed, which is 20μm to 100μm. Therefore, in order to achieve the best match, boss cover plates with various height specifications should be designed. According to the actual process control capabilities and requirements, the boss heights are h (theoretical calculation height, h ≥ 500μm), h + 10μm, h + 20μm, h + 30μm, h - 10μm, h - 20μm, etc.

[0009] (3) The edge thickness of the metal cover is 0.1 mm, so that it can be welded to the ceramic shell sealing ring through a parallel seam welding process;

[0010] (4) The roughness of the metal cover plate boss surface should be ≤20μm to avoid the boss surface damaging the active area of ​​the top chip;

[0011] (5) The cover plate boss is provided with inner / outer chamfers, with a chamfer radius of ≥0.2mm, to ensure the realization of the cover plate manufacturing process. At the same time, the inner chamfer can ensure the structural reliability of the cover plate, and the outer chamfer can ensure that the thermal conductive glue can overflow well and prevent the boss from damaging the chip;

[0012] (6) During the capping operation, the height difference between the upper surface of the chip stack structure and the ceramic shell sealing ring must be measured first, with a measurement accuracy of 1 μm;

[0013] (7) Calculate the height difference between the upper surface of the chip stack structure and the sealing ring of the ceramic housing, and the difference between the height difference between the upper surface of the chip stack structure and the upper surface of the ceramic housing, and the height difference between the upper surface of the chip stack structure and the upper surface of the ceramic housing;

[0014] (8) After the difference calculation is completed, the cover plate with the corresponding boss height is selected according to the magnitude of the difference;

[0015] (9) Apply a certain amount of thermal conductive glue on the surface of the chip active area. The glue application range should be 0.5mm to 2mm smaller than the size of the cover plate boss on each side. The glue application amount should be controlled. When the cover plate is bonded to the chip, the glue layer thickness should be slightly thicker by 5μm to 10μm than the distance between the cover plate boss and the upper surface of the chip calculated above. The glue layer thickness should be greater than the boss roughness by more than 10μm, but the glue layer thickness should be less than 50μm to avoid the glue layer being too thick and affecting the bonding performance and thermal conductivity.

[0016] (10) Place the cover accurately in the capping position. At this time, the lower surface of the cover boss and the upper surface of the chip can be connected to each other through the thermal conductive adhesive. At this time, apply a force of 10N to 20N to the cover in the vertical direction for 10s to 30s to ensure that the thermal conductive adhesive between the cover boss and the chip surface can be evenly spread;

[0017] (11) The circuit is placed in a parallel seam welding device and capped by parallel seam welding;

[0018] (12) Place the circuit in an oven to cure the thermal adhesive;

[0019] (13) The cured thermal conductive adhesive provides a new heat dissipation channel for the chip stacking structure, that is, heat dissipation is achieved through the contact between the upper chip and the cover plate.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] (1) The cover plate of the present invention has strong versatility and can be applied to a variety of chip stacked airtight ceramic packaged integrated circuits.

[0022] (2) The heat dissipation method of the present invention can provide an additional heat dissipation channel for the chip stacking structure, and the heat dissipation channel is a metal cover plate, and the outside of the cover plate is the external environment. Compared with the heat dissipation structure that only relies on the bottom chip to the ceramic shell, it has a stronger heat dissipation capacity.

[0023] (3) The cover plate boss of the present invention is designed with consideration given to the overall height of the chip stack structure and the height difference between the shell sealing ring and the upper surface of the chip stack structure, so that the structure can be well adapted.

[0024] (4) The lower surface of the cover plate boss and the upper surface of the chip stacking structure are connected by thermally conductive adhesive, which can ensure heat dissipation from the chip to the cover plate.

[0025] (5) The size of the cover plate boss of the present invention is 2mm to 3mm smaller on each side than the chip, which can leave enough space for the thermal conductive glue to overflow to the chip surface. At the same time, the boss size is smaller than the chip, which can maintain a safe distance between the boss and the upper chip bonding wire after installation.

[0026] (6) The inner and outer chamfers of the cover boss of the present invention are processed, which can not only ensure the structural strength of the cover, but also avoid damage to the internal structure of the shell, the chip, etc. during the installation of the cover. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 Schematic diagram of the overall structure of the chip stacked airtight ceramic package;

[0028] Figure 2 Schematic diagram of the ceramic shell chip stacking structure;

[0029] Figure 3 This is a schematic diagram of the "T"-shaped cover structure. DETAILED DESCRIPTION

[0030] To make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0031] In order to further increase memory capacity while controlling the size of integrated circuits, it is necessary to adopt the Z-direction chip integration method, that is, stacking multiple layers of memory chips in the height direction to avoid the horizontal expansion of memory integrated circuits, so as to control the overall expansion area as much as possible.

[0032] Chip stacked ceramic packaging requires stacking the chips in a hollow ceramic housing. After chip bonding and wire bonding, a metal cover is used to seal the ceramic cavity, so its reliability is relatively high. The interior of the ceramic package is a nitrogen environment. The bottom chip is bonded to the ceramic housing substrate, and the upper chip is stacked in the height direction on the basis of the bottom chip. Since the upper chip in the chip stacked ceramic package is only bonded to the surface of the lower chip, the upper chip can only dissipate heat toward the ceramic housing through the bottom chip. The heat dissipation channel is single and the heat dissipation efficiency is low. Therefore, it is necessary to propose a heat dissipation structure and method for chip stacked airtight ceramic packaging. Based on the analysis of the characteristics of the chip stacking structure, the top of the stacked chip can be used for heat dissipation to quickly improve the heat dissipation capacity. Therefore, a heat dissipation structure and method for chip stacked airtight ceramic packaging are proposed.

[0033] like Figure 1As shown, a heat dissipation structure of a chip stacked airtight ceramic package is characterized by comprising a package overall structure 1 (i.e., a ceramic shell chip stacked structure), a "T"-shaped cover plate 2, and a thermal conductive adhesive layer 3.

[0034] The overall package structure includes a chip 4, bonding wires 5, a ceramic housing sealing ring 6, a silicon wafer 7, and a ceramic housing 8. The "T"-shaped airtight package metal cover is made of Kovar alloy and its surface is nickel-plated. A boss slightly smaller than the chip size is designed in the center of the cover. The boss size is required to be 2mm to 3mm smaller than the chip on each side. The purpose is to leave enough room for the thermal conductive adhesive to overflow between the boss and the chip surface when they come into contact, so as to prevent the thermal conductive adhesive from overflowing onto the pads or bonding wires on the chip surface. Specifically, the "T"-shaped cover includes structures such as the boss area 9, the inner chamfer of the boss 10, the outer chamfer of the boss 11, and the welding area 12; the thermal conductive adhesive layer 3 is a resin adhesive with a high thermal conductivity coefficient of ≥2W / mK. During the packaging process, after completing the bonding and wire bonding of the chip stacking structure, it is necessary to apply thermal conductive adhesive on the surface of the top chip of the chip stacking structure, and then place the "T"-shaped cover in the welding position so that the lower surface of the cover boss contacts the thermal conductive adhesive on the upper surface of the chip. Then, parallel seam welding is used to form a welding connection between the cover welding area and the ceramic shell sealing ring.

[0035] like Figure 2 、 Figure 3 As shown, the specific contents of the package heat dissipation structure design are as follows:

[0036] (1) The chip stacking structure consists of 4 layers of chips, which are connected by single-crystal silicon wafers. The chips are bonded to each other with epoxy insulating adhesive. After each layer of chip is bonded, wire bonding is required before bonding the upper layer of chip.

[0037] (2) After all chips are stacked and wire bonded, the height difference between the upper chip surface and the ceramic shell sealing ring needs to be measured, and the measurement accuracy is required to be better than 1μm.

[0038] (3) The size of the "T"-shaped cover plate boss area requires that the length of each side be 2mm to 3mm less than the corresponding chip side length. The purpose is to leave enough space for the thermal conductive adhesive to overflow between the boss and the chip surface when the boss contacts the chip surface, so as to prevent the thermal conductive adhesive from overflowing onto the pads or bonding wires on the chip surface.

[0039] (4) "T"-shaped cover plate, with a boss thickness of ≥0.5mm, is designed to ensure good heat dissipation and avoid contact between the boss of the cover plate and the bonding wire after parallel seam welding. The cover plate is designed to match the ceramic shell structure and the overall design thickness of the chip stack. The height of the boss in the center of the cover plate is required to just meet the gap between the lower surface of the boss and the upper surface of the top chip after capping, which is 20μm to 100μm. Therefore, in order to achieve the best match, boss cover plates with various specifications and heights should be designed. According to the actual process control capabilities and requirements, the boss heights are h (theoretical calculation height, h≥500μm), h+10μm, h+20μm, h+30μm, h-10μm, h-20μm, etc.

[0040] (5) The thickness of the welding area of ​​the “T”-shaped cover is 0.1mm to 0.3mm, and airtight welding can be achieved through parallel seam welding process.

[0041] (6) The “T”-shaped cover plate boss is provided with inner / outer chamfers, with a chamfer radius of ≥0.2mm, to ensure the realization of the cover plate manufacturing process. At the same time, the inner chamfer can reduce stress concentration and improve the structural reliability of the cover plate. The outer chamfer can ensure that the thermal conductive glue can overflow well and prevent the boss from damaging the chip.

[0042] (7) The surface roughness of the “T”-shaped cover plate boss is ≤20μm to prevent the boss surface from damaging the active area of ​​the top chip.

[0043] (8) The thermal conductive adhesive between the top chip and the cover is the only channel for the chip to dissipate heat to the cover, so the thermal conductivity of the thermal conductive adhesive should be ≥2W / mK.

[0044] A heat dissipation method for a chip stacked airtight ceramic package includes a package heat dissipation structure design and a package process method, wherein the specific contents of the package process method are as follows:

[0045] (1) After completing the ceramic shell chip stacking structure and before parallel seam welding, it is necessary to measure the height difference between the upper surface of the chip stacking structure and the ceramic shell sealing ring, and the measurement accuracy is required to be better than 1μm;

[0046] (2) After completing the height difference measurement, calculate the height difference between the upper surface of the chip stack structure and the ceramic housing sealing ring, and the difference between the cover plate boss and the upper surface of the chip; the difference is the distance between the cover plate boss and the upper surface of the chip;

[0047] (3) After the difference calculation is completed, a certain amount of thermal conductive glue is applied on the chip surface according to the magnitude of the difference. The amount of glue applied should be such that after uniform spreading, the thickness of the glue layer should be 5μm to 10μm thicker than the distance between the cover plate boss and the chip surface calculated above. At the same time, the glue application range should be 0.5mm to 2mm smaller than the size of the cover plate boss on each side.

[0048] (4) Place the cover accurately in the capping position. At this time, the lower surface of the cover boss and the upper surface of the chip can be connected to each other through the thermal conductive adhesive. At this time, apply a force of 10N to 20N in the vertical direction to the cover for 10s to 30s to ensure that the thermal conductive adhesive between the cover boss and the chip surface can be evenly spread;

[0049] (5) Place the circuit in a parallel seam welding device and perform parallel seam welding to seal the cap;

[0050] (6) After the parallel seam welding cap is completed, the circuit is airtightly packaged. At this time, the thermal conductive adhesive is still in a sticky state, so it needs to be placed in an oven to cure the thermal conductive adhesive. The curing temperature should be set according to the thermal conductive adhesive instructions.

[0051] (7) Complete airtight packaging.

[0052] Example:

[0053] The heat dissipation structure and method of the chip stack airtight ceramic package proposed in the present invention were used to package a four-layer chip stack circuit, achieving the following results:

[0054] For a 4-layer chip stacking product, the chip size is 10mm×10mm, the chip thickness is 200μm, and the silicon wafer size between the chips is 8mm×8mm and the thickness is 250μm. According to the chip size, the boss size is designed to be 8mm×8mm. After the chip stacking, the height difference between the top chip surface and the shell sealing ring is designed to be 650μm. Based on the height difference of 650μm, considering that the general adhesive layer thickness is 20μm to 40μm, various specifications of "T"-shaped cover plates are designed, with boss thicknesses of 610μm, 620μm, 630μm, 640μm, and 650μm respectively. The cover plate is selected according to the actual measured height difference.

[0055] After all chips were stacked and wire-bonded, the height difference between the upper chip surface and the ceramic housing sealing ring was measured and found to be 630μm. Based on a 20μm adhesive layer thickness, a T-shaped cover with a 610μm boss thickness was selected.

[0056] Before capping, apply thermal adhesive to the active area of ​​the top chip surface, ensuring a thickness of approximately 25μm and a coating area of ​​approximately 9mm x 9mm. After application, place the cover downward and apply a force of 15N for 20 seconds to ensure even spread of the thermal adhesive between the cover bosses and the chip surface. After the cover is placed, perform parallel seam welding to cap the chip. After capping, place the cover in an oven at 150°C for 1 hour to cure the thermal adhesive and complete the package.

[0057] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0058] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

Claims

1. A heat dissipation structure of a chip stacked airtight ceramic package, characterized in that: Including the overall packaging structure, T-shaped cover, and thermal conductive adhesive layer; The T-shaped cover includes a boss area and a welding area, wherein the T-shaped cover is connected to the overall package structure through the welding area, the boss area is located corresponding to the chip in the overall package structure, and a thermal conductive adhesive layer is applied between the boss area and the chip; The thermal conductive adhesive layer is a resin adhesive with a thermal conductivity better than 2W / mK; the size of the boss area is smaller than that of the chip, and the gap between the boss area and the chip is 20μm to 100μm; the surface roughness of the boss area is less than 20μm; the boss thickness is not less than 0.5mm, and the chamfer radius of the boss area is not less than 0.2mm; The chamfers of the platform area include inner chamfers and outer chamfers. The root edge of the platform area away from the chip is the inner chamfer, and the end edge of the platform area is the outer chamfer.

2. The heat dissipation structure according to claim 1, characterized in that: The thickness of the welding zone is 0.1mm to 0.3mm.

3. The heat dissipation structure according to claim 1, characterized in that: The T-shaped cover and the overall package structure are welded using parallel seam welding.

4. The heat dissipation structure according to claim 1, characterized in that: The multi-layer chips within the overall package structure are connected by single-crystal silicon wafers, and the chips are bonded to the single-crystal silicon wafers using epoxy insulating adhesive. Wire bonding is performed after each layer of chips is bonded.

5. The heat dissipation structure according to claim 1, characterized in that: After the boss area is projected onto the nearest chip, the distance between each edge of the boss area and the corresponding edge of the chip is 2 mm to 3 mm.

6. A heat dissipation method for a chip stacked airtight ceramic package, characterized in that: The heat dissipation structure according to any one of claims 1 to 5 comprises the following steps: (1) Measure the height difference between the chip top surface and the ceramic housing sealing ring with an accuracy of 1 μm; (2) determining the distance between the boss area and the top surface of the chip based on the height difference measurement value and the height of the boss area; (3) Apply thermal conductive glue on the chip surface. The thickness of the glue layer after the glue is evenly spread is slightly thicker than the distance between the boss area and the chip surface by 5μm to 10μm. At the same time, the glue application range is 0.5mm to 2mm smaller than the size of the cover boss on each side. (4) Place the cover plate on the overall package structure. At this time, the lower surface of the boss area and the upper surface of the chip can be connected to each other through the thermal conductive adhesive. Then, apply a force of 10N to 20N in the vertical direction to the cover plate for 10s to 30s to ensure that the thermal conductive adhesive between the boss area and the upper surface of the chip is evenly spread. (5) Place the package structure and T-shaped cover in a parallel seam welding device and perform parallel seam welding to seal the cap; (6) After completing the parallel seam welding capping, the circuit is airtightly packaged, and then placed in an oven to cure the thermal conductive adhesive, finally completing the airtight packaging.

7. The heat dissipation method of the chip stacked airtight ceramic package according to claim 6, characterized in that: After the cover is placed and the overall structure is packaged, the interior is a nitrogen environment.

8. The heat dissipation method of the chip stacked airtight ceramic package according to claim 6, characterized in that: After the circuit is airtightly packaged, it is placed in an oven and cured at 150°C for 1 hour to complete the packaging.

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