MOSFET and Method for Manufacturing the Same

Abstract

The present invention provides a MOSFET, comprising: a substrate, a first shielding gate, a first gate oxide layer, a control gate, a second shielding gate, a second gate oxide layer, a base region and a source region, wherein an epitaxial layer with a U-shaped trench is formed on the substrate, the first shielding gate is located at the bottom of the U-shaped trench, the control gate is located on the first shielding gate and covers the upper half sidewall of the U-shaped trench; the second shielding gate fills the remaining U-shaped trench, wherein the source region is electrically interconnected with the first shielding gate. The present invention also provides a manufacturing method of the MOSFET. By electrically interconnecting the first shielding gate and the source region, the displacement current is dispersed, the contact resistance between the first shielding gate and the source region is reduced, the contact resistance uniformity is improved, and the uniformity of the induced potential distributed along the first shielding gate is improved, thereby avoiding the current concentration caused by the fixed avalanche point due to the non-uniform potential distribution.

Description

Technical Field

[0001] This application relates to the technical field of MOSFET devices, and particularly to a MOSFET and a manufacturing method thereof. Background Art

[0002] MOSFETs can be roughly classified into the following categories: planar MOSFETs; Trench MOSFETs, mainly used in low-voltage fields; SGT (Shielded Gate Transistor) MOSFETs, mainly used in medium- and low-voltage fields; SJ- (Super Junction) MOSFETs, mainly applied in high-voltage fields. With the rise of mobile phone fast charging, electric vehicles, brushless motors, and lithium batteries, SGT MOSFETs, as representatives of medium-voltage MOSFETs, are widely used as switching devices in motor drive systems, inverter systems, and power management systems, and are core power control components.

[0003] Currently, the common SGT MOSFETs on the market mainly include left-right structure SGT MOSFETs (LRSGT MOSFETs) and up-down structure SGT MOSFETs (UDSGT MOSFETs). Among them, LRSGT MOSFETs are suitable for medium-voltage to high-voltage fields, and UDSGT MOSFETs are suitable for low-voltage fields. However, both of the existing two types of SGT MOSFETs have the problem of current concentration caused by fixed avalanche points due to non-uniform potential distribution. Therefore, it is necessary to invent a new MOSFET to solve this problem. Summary of the Invention

[0004] This application provides a MOSFET and a manufacturing method thereof, which can solve the problem of current concentration caused by fixed avalanche points due to non-uniform potential distribution of SGT MOSFETs.

[0005] On the one hand, an embodiment of this application provides a MOSFET, including:

[0006] A substrate, on which an epitaxial layer is formed, and a U-shaped trench is formed in the epitaxial layer;

[0007] A first shielding gate, which covers the bottom wall and the lower half of the side wall of the U-shaped trench;

[0008] A first gate oxide layer, which is located in the U-shaped trench and covers the first shielding gate;

[0009] A control gate, which covers the upper half of the side wall of the U-shaped trench;

[0010] A second shielding gate, which is located in the U-shaped trench and covers the first gate oxide layer;

[0011] A second gate oxide layer, which is located between the control gate and the second shielding gate in the U-shaped trench;

[0012] A base region, which is located in the epitaxial layer and on both sides of the U-shaped trench; and,

[0013] Two source regions, which are respectively located in the base regions on each side.

[0014] Optionally, in the MOSFET, the MOSFET further includes: a field oxide layer, which covers the bottom wall and all side walls of the U-shaped trench and the surface of the epitaxial layer to isolate the first shielding gate and the control gate in the U-shaped trench from the external epitaxial layer.

[0015] Optionally, in the MOSFET, the thickness of the field oxide layer is 200 nm to 300 nm.

[0016] Optionally, in the MOSFET, the MOSFET further includes: an interlayer insulating layer, which covers the field oxide layer, the control gate and the second shielding gate, wherein a plurality of first contact holes are formed in the interlayer insulating layer.

[0017] Optionally, in the MOSFET, by filling metal in the first contact holes, the control gate and the source regions are respectively electrically led out to the interlayer insulating layer, and the control gate and the source regions are insulated from each other.

[0018] Optionally, in the MOSFET, a second contact hole is formed in the first gate oxide layer, and by filling metal in the first contact hole and the second contact hole, the first shielding gate is electrically led out to the interlayer insulating layer and is electrically interconnected with the source region.

[0019] Optionally, in the MOSFET, the thickness of the first gate oxide layer is 300 nm to 330 nm.

[0020] Optionally, in the MOSFET, the thickness of the second gate oxide layer is

[0021] Optionally, in the MOSFET, the materials of the first shielding gate, the control gate and the second shielding gate are all polysilicon.

[0022] On the other hand, an embodiment of the present application further provides a manufacturing method of a MOSFET, including:

[0023] Provide a substrate, on which an epitaxial layer is formed, and a U-shaped groove is formed in the epitaxial layer;

[0024] Form a first shielding gate, which covers the bottom wall and the lower half of the side wall of the U-shaped groove;

[0025] Form a first gate oxide layer, which is located in the U-shaped groove and covers the first shielding gate;

[0026] Form a control gate, which covers the upper half of the side wall of the U-shaped groove;

[0027] Form a second gate oxide layer, which is located in the U-shaped groove and covers the side surface of the control gate;

[0028] Form a second shielding gate, which is located in the U-shaped groove and covers the first gate oxide layer;

[0029] Form a base region, which is located in the epitaxial layer and on the side of the U-shaped groove; and,

[0030] Form two source regions, which are respectively located in the base regions on each side.

[0031] The technical solution of this application has at least the following advantages:

[0032] In this application, by electrically interconnecting the first shielding gate and the source region, when avalanche occurs, the displacement current can directly flow from the first shielding gate to the source region. In this extreme case, the contact resistance between the first shielding gate and the source region is uniform and much smaller than that of the traditional SGT MOSFET. The induced potential distribution of the MOSFET provided in this application along the first shielding gate is uniform and much lower than that of the traditional SGT MOSFET. Therefore, the MOSFET provided in this application avoids the situation of current concentration caused by the fixed avalanche point due to non-uniform potential distribution.

[0033] Furthermore, the design of the control gate covering the upper half of the side wall of the U-shaped groove can improve the ability of unclamped inductive switching (UIS).

[0034] In addition, the first shielding gate at the bottom of the U-shaped groove electrically interconnected with the source region has a large volume, which can eliminate the facing area between the gate and the drain, greatly reduce the gate-drain charge and capacitance, and improve the switching characteristics of the device. Description of the Drawings

[0035] To more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0036] Figures 1 - 10 It is a schematic diagram of a semiconductor structure in each process step of manufacturing a MOSFET according to an embodiment of the present invention;

[0037] Among them, the description of the reference numerals is as follows:

[0038] 100 - Substrate, 110 - Epitaxial layer, 120 - Field oxide layer, 130 - First shielding gate, 140 - First gate oxide layer, 150 - Control gate, 160 - Second gate oxide layer, 170 - Second shielding gate, 180 - Base region, 181 - Source region, 190 - Interlayer insulating layer, 191 - First via hole, 200 - Trench, 210 - Metal. Specific Embodiments

[0039] The following will clearly and completely describe the technical solutions in the present application in conjunction with the drawings. Obviously, the described embodiments are some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0040] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0041] In the description of the present application, it should be noted that unless otherwise clearly specified and limited, the terms "mounted", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific circumstances.

[0042] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0043] On the one hand, an embodiment of the present application provides a method for manufacturing a MOSFET. Specifically, please refer to Figures 1 - 10 , Figures 1 - 10 which is a schematic diagram of a semiconductor structure in each process step of manufacturing a MOSFET according to an embodiment of the present invention.

[0044] First, as Figure 1 shown, a substrate 100 is provided, an epitaxial layer 110 is formed on the substrate 100, and a U-shaped trench 200 is formed in the epitaxial layer. Specifically, the substrate 100 can be a substrate doped with arsenic with a low resistivity, and the epitaxial layer 110 is a silicon epitaxy doped with phosphorus. In this embodiment, an inclined angle etching can be used to form an arc shape at the bottom of the trench to obtain the U-shaped trench 200. The U-shaped trench 200 has a large aspect ratio. The U-shaped trench 200 with a high aspect ratio can use more silicon volume to absorb EAS energy. Further, the U-shaped trench 200 with a high aspect ratio serves as a "body field plate" to balance the charge in the drift region under reverse voltage, which can reduce the resistivity of the drift region, thereby reducing the specific on-resistance (RSP) and gate charge (Qg) of the device. The MOSFET provided by the present application can laterally use more silicon epitaxial volume to block voltage, making the internal resistance of the device at least 2 times lower than that of a traditional MOSFET.

[0045] Then, as Figure 2 shown, a field oxide layer 120 is formed. The field oxide layer 120 covers the bottom wall and side walls of the U-shaped trench 200, as well as the surface of the epitaxial layer 110. The thickness of the field oxide layer 120 is 200 nm to 300 nm, mainly for insulating the first shielding gate 130 inside the trench from the external epitaxial layer 110. In this embodiment, the field oxide layer 120 is formed by a thermal growth process, and the process temperature is greater than 1000 °C.

[0046] Further, as Figure 3As shown, a first shielding gate 130 is formed, and the first shielding gate 130 covers the bottom wall and the lower half of the side wall of the U-shaped trench 200, that is, covers the field oxide layer 120 on the bottom wall and the lower half of the side wall of the U-shaped trench 200. Specifically, the material of the first shielding gate 130 is polysilicon. The steps of forming the first shielding gate 130 may specifically include: first depositing polysilicon material, and the polysilicon material can fill the entire U-shaped trench 200 and cover the surface of the field oxide layer 120, then using a CMP process to grind and remove the polysilicon material on the surface of the field oxide layer 120, and finally using an etch-back process to remove a part of the thickness of the polysilicon material in the U-shaped trench 200, and retaining the polysilicon material covering the bottom wall and the lower half of the side wall of the U-shaped trench 200 to obtain the first shielding gate 130. In this embodiment, the thickness of the polysilicon material etched back in the U-shaped trench 200 is at least 1 / 2 of the height of the trench. The first shielding gate 130 functions to generate a lateral electric field, generate lateral depletion, and increase the breakdown voltage.

[0047] Next, as Figure 4 shown, a first gate oxide layer 140 is formed, and the first gate oxide layer 140 is located in the U-shaped trench 200 and covers the first shielding gate 130. Specifically, the material of the first gate oxide layer 140 may be silicon dioxide, and the first gate oxide layer 140 is formed on the first shielding gate 130 by a thermal oxidation process, and the thickness of the first gate oxide layer 140 may be 300 nm to 330 nm.

[0048] Further, as Figure 5 shown, a control gate 150 is formed, and the control gate 150 covers the upper half of the side wall of the U-shaped trench 200. Specifically, the material of the control gate 150 is polysilicon. The specific steps of forming the control gate 150 may include: first filling the remaining space in the U-shaped trench 200 with polysilicon material, and then removing the polysilicon material at the central position of the U-shaped trench 200 by an etch-back process, and retaining the polysilicon material on the upper half of the side wall of the U-shaped trench 200 to obtain the control gate 150. The design of the control gate 150 covering the upper half of the side wall of the U-shaped trench 200 in this application can improve the ability of unclamped inductive switching (UIS).

[0049] Next, as Figure 6 shown, a second gate oxide layer 160 is formed, and the second gate oxide layer 160 is located in the U-shaped trench 200 and covers the side of the control gate 150. Specifically, the material of the second gate oxide layer 160 may be silicon dioxide, and the thickness of the second gate oxide layer 160 is In this embodiment, the second gate oxide layer 160 is formed by a thermal oxidation process with a process temperature higher than 1000°C. The second gate oxide layer 160 isolates the control gate 150 from the subsequently formed second shielding gate 170. The thermally grown second gate oxide layer 160 should be relatively thin to facilitate the subsequent filling of the second shielding gate 170 in the U-shaped trench 200.

[0050] Further, as Figure 7 shown, a second shielding gate 170 is formed. The second shielding gate 170 is located in the U-shaped trench 200 and covers the first gate oxide layer 140. Specifically, the material of the second shielding gate 170 is polysilicon. The specific steps for forming the second shielding gate 170 may include: filling polysilicon material in the remaining space at the center position of the U-shaped trench 200 and depositing a layer on the surface of the field oxide layer 120 and the surface of the control gate 150 as well. Then, the polysilicon material on the surface of the field oxide layer 120 and the surface of the control gate 150 is removed by CMP process, and only the polysilicon material in the remaining space at the center position of the U-shaped trench 200 is retained to obtain the second shielding gate 170.

[0051] Next, as Figure 8 shown, a base region 180 is formed. The base region 180 is located in the epitaxial layer 110 and on both sides of the U-shaped trench 200. Specifically, boron ions are implanted in the epitaxial layer 110 on both sides of the U-shaped trench 200 and subjected to high-temperature thermal annealing to form a P-type base region 180.

[0052] Further, as Figure 8 shown, two source regions 181 are formed. The source regions 181 are respectively located in the base regions 180 on each side. Specifically, arsenic ions are implanted at the top of the base region 180, and after activation, N+ source regions 181 are formed in the base region 180.

[0053] Preferably, as Figure 9 shown, after forming the source regions 181, the manufacturing method of the MOSFET may further include: forming an interlayer insulating layer 190. The interlayer insulating layer 190 covers the field oxide layer 120, the control gate 150, the second gate oxide layer 160, and the second shielding gate 170. Among them, a plurality of first contact holes 191 are formed in the interlayer insulating layer 190. The first contact holes 191 located on the source regions 181 also penetrate the field oxide layer 120.

[0054] Finally, as Figure 10As shown, after forming the interlayer insulating layer 190, the manufacturing method of the MOSFET may further include: filling the first contact hole 191 with metal 210. In this embodiment, by filling the first contact hole 191 with metal 210, the control gate 150 and the source region 181 are electrically led out to the interlayer insulating layer 190 respectively, and are insulated from each other between the control gate 150 and the source region 181.

[0055] Furthermore, in this embodiment, a second contact hole (not shown) may be formed in the first gate oxide layer 140 and at a position that does not affect the second shielding gate 170. By filling the first contact hole 191 and the second contact hole with metal 210, the first shielding gate 130 is electrically led out to the interlayer insulating layer 190 and is electrically interconnected with the source region 181. In this application, by electrically interconnecting the first shielding gate 130 and the source region 181, when avalanche occurs, the displacement current can directly flow from the first shielding gate 130 to the source region 181. In this extreme case, the contact resistance between the first shielding gate 130 and the source region 181 is uniform and much smaller than that of the traditional SGT MOSFET. The induced potential distribution of the MOSFET provided in this application along the first shielding gate 130 is uniform and much lower than that of the traditional SGT MOSFET. Therefore, the MOSFET provided in this application avoids the situation of current concentration caused by the fixed avalanche point due to non-uniform potential distribution, ensures the reliability of the device, and improves the device yield. In addition, the first shielding gate 130 at the bottom of the U-shaped trench 200 electrically interconnected with the source region 181 has a larger volume, which can eliminate the facing area between the gate and the drain, greatly reduce the gate-drain charge and capacitance, and improve the switching characteristics of the device. In addition, under the same specifications, the area of the MOSFET device chip provided in this application is smaller and the cost performance is higher.

[0056] On the other hand, the embodiment of this application also provides a MOSFET, referring to Figure 10 , Figure 10It is a schematic structural diagram of the MOSFET according to an embodiment of the present invention. The MOSFET includes: a substrate 100, a first shielding gate 130, a first gate oxide layer 140, a control gate 150, a second shielding gate 170, a second gate oxide layer 160, a base region 180, and two source regions 181. Among them, an epitaxial layer 110 is formed on the substrate 100, and a U-shaped trench 200 is formed in the epitaxial layer 110; the first shielding gate 130 covers the bottom wall and the lower half of the side wall of the U-shaped trench 200; the first gate oxide layer 140 is located in the U-shaped trench 200 and covers the first shielding gate 130; the control gate 150 covers the upper half of the side wall of the U-shaped trench 200; the second shielding gate 170 is located in the U-shaped trench 200 and covers the first gate oxide layer 140; the second gate oxide layer 160 is located between the control gate 150 and the second shielding gate 170 in the U-shaped trench 200; the base region 180 is located in the epitaxial layer 110 and on both sides of the U-shaped trench 200; the source regions 181 are respectively located in the base regions 180 on each side.

[0057] Further, the MOSFET further includes: a field oxide layer 120, and the field oxide layer 120 covers the bottom wall and all side walls of the U-shaped trench 200 and the surface of the epitaxial layer 110 to isolate the first shielding gate 130 and the control gate 150 in the U-shaped trench 200 from the external epitaxial layer 110.

[0058] Preferably, the MOSFET further includes: an interlayer insulating layer 190, and the interlayer insulating layer 190 covers the field oxide layer 120, the control gate 150, the second gate oxide layer 160, and the second shielding gate 170. Among them, a plurality of first contact holes 191 are formed in the interlayer insulating layer 190.

[0059] Further, metal 210 is filled in the first contact holes 191 to obtain metal plugs so as to electrically lead out the control gate 150 and the source regions 181 to the interlayer insulating layer 190 respectively, and the control gate 150 and the source regions 181 are insulated from each other. A second contact hole (not shown) is formed in the first gate oxide layer 140. By filling metal 210 in the first contact holes 191 and the second contact hole, the first shielding gate 130 can be electrically led out to the interlayer insulating layer 190 and interconnected with the source regions 181.

[0060] Obviously, the above embodiments are merely examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or alterations can be made based on the above description. It is not necessary and impossible to list all implementation manners here. And the obvious changes or alterations derived therefrom still fall within the protection scope of this application for invention.

Claims

1. A MOSFET, characterized in that, Comprising: A substrate, on which an epitaxial layer is formed, and a U-shaped trench is formed in the epitaxial layer; A first shielding gate, which covers the bottom wall and the lower half of the side walls of the U-shaped trench; A first gate oxide layer, which is located in the U-shaped trench and covers the first shielding gate; A control gate, which covers the upper half of the side walls of the U-shaped trench and projects onto the first shielding gate in a top view; A second shielding gate, which is located in the U-shaped trench and covers the first gate oxide layer; A second gate oxide layer, which is located between the control gate and the second shielding gate in the U-shaped trench; A base region, which is located in the epitaxial layer and on both sides of the U-shaped trench; and, Two source regions, which are respectively located in the base regions on each side, wherein the source regions are electrically interconnected with the first shielding gate.

2. The MOSFET according to claim 1, characterized in that, The MOSFET further comprises: a field oxide layer, which covers the bottom wall and all side walls of the U-shaped trench and the surface of the epitaxial layer to isolate the first shielding gate and the control gate in the U-shaped trench from the external epitaxial layer.

3. The MOSFET according to claim 2, characterized in that, The thickness of the field oxide layer is 200 nm to 300 nm.

4. The MOSFET according to claim 2, characterized in that, The MOSFET further comprises: an interlayer insulating layer, which covers the field oxide layer, the control gate and the second shielding gate, wherein a plurality of first contact holes are formed in the interlayer insulating layer.

5. The MOSFET according to claim 4, characterized in that, By filling metal in the first contact holes, the control gate and the source regions are respectively electrically led out to the interlayer insulating layer, and the control gate and the source regions are insulated from each other.

6. The MOSFET according to claim 4, characterized in that, A second contact hole is formed in the first gate oxide layer. By filling metal in the first contact hole and the second contact hole, the first shielding gate is electrically led out to the interlayer insulating layer and is electrically interconnected with the source regions.

7. The MOSFET according to claim 1, characterized in that, The thickness of the first gate oxide layer is 300 nm to 330 nm.

8. The MOSFET according to claim 1, characterized in that, The thickness of the second gate oxide layer is 9. The MOSFET according to claim 1, characterized in that, The materials of the first shielding gate, the control gate and the second shielding gate are all polysilicon.

10. A manufacturing method of a MOSFET, characterized in that, Comprising: Providing a substrate, on which an epitaxial layer is formed, and a U-shaped trench is formed in the epitaxial layer; Forming a first shielding gate, which covers the bottom wall and the lower half of the side walls of the U-shaped trench; Forming a first gate oxide layer, which is located in the U-shaped trench and covers the first shielding gate; Forming a control gate, which covers the upper half of the side walls of the U-shaped trench and projects onto the first shielding gate in a top view; Forming a second gate oxide layer, which is located in the U-shaped trench and covers the side surface of the control gate; Forming a second shielding gate, which is located in the U-shaped trench and covers the first gate oxide layer; Forming a base region, which is located in the epitaxial layer and beside the U-shaped trench; and, Forming two source regions, which are respectively located in the base regions on each side.

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