A method, system, device and medium for improving error detection performance of Jelling code error correction

Abstract

The present invention discloses a method, system, device and medium for improving the error detection performance of Jelling code error correction. Since data is transmitted in a symmetrical discrete memoryless channel, errors may occur. Related schemes need to be carried out 2 m The error correction action is completed by checking once, and the amount of calculation is large. In order to solve the problem of fast verification of related schemes, the present invention uses "odd numbers cannot divide even numbers" as a condition to perform byte operations on the binary sequence V on the basis of the related schemes, and uses mathematical methods to give the binary sequence V a definite error detection judgment basis. After receiving the data, the receiving end implements fast verification through the error detection judgment basis. Half of the errors can be realized by fast error verification through this method. This method will not reduce the transmission rate of data in a symmetrical discrete memoryless channel, nor will it increase the length of the encoded bytes, and will not change the encoding code rate. It can effectively reduce the complexity of verification judgment and improve the calculation efficiency of related schemes.

Description

Technical Field

[0001] The present invention relates to the field of information coding technology, and in particular to a method, system, device and medium for improving the error detection performance of Jelling code error correction. Background Art

[0002] The Jelin code error correction is currently the first original channel coding algorithm in my country. It can be proven to reach the channel capacity and has important application value in the fields of information technology and communication transmission in the future. Figure 1 As shown, the process is as follows: the sending end (i.e., the encoding end) converts a binary sequence X = (x1, x2, ..., x) with a length of n into n ) weighted probability arithmetic coding (also called weighted probability coding) result L l Convert to a binary sequence V = (v1, v2, ..., v m ), V is transmitted through the DMC (Discrete Memoryless Channel, symmetrical discrete memoryless channel) channel, U = (u1,u2,…,u m ) is the binary sequence received by the receiving end (ie, the decoding end). The DMC channel includes the BSC (Binary Symmetric Channel) and the BEC (Binary Erasure Channel) channels.

[0003] In the related scheme, the receiving end performs forward error correction after performing Jelling code error detection on the BSC or BEC channel, and needs to perform a negation operation on each bit. When m=32, 2 operations are required. m The error correction action is completed after checking for times. As m increases, the amount of calculation increases exponentially. Summary of the invention

[0004] The present invention aims to at least solve the technical problems existing in the prior art. To this end, the present invention proposes a method, system, device and medium for improving the error detection performance of Jelling code error correction. The method can effectively reduce the complexity of verification judgment and improve the computational efficiency of related schemes.

[0005] A first aspect of the present invention provides a method for improving the error detection performance of Jelling code error correction, comprising the following steps:

[0006] The sending end obtains the binary sequence V obtained by weighted probability arithmetic coding of the source sequence;

[0007] The transmitting end converts the binary sequence V into a first byte sequence V′, where y i ∈{0, 1, ..., 255}, m represents the sequence length of the binary sequence V, It means m / 8 is rounded down;

[0008] The transmitting end generates a second byte sequence Q according to the first byte sequence V′, wherein

[0009] The transmitting end generates a third byte sequence Q′ according to the second byte sequence Q, wherein Y i ′=Y i +Y i+1 , Y′ i+1 =Y i+1 -Y i ;

[0010] The transmitting end sends the third byte sequence Q′ to the receiving end through a symmetric discrete memoryless channel;

[0011] The receiving end receives the sequence output by the symmetric discrete memoryless channel, and restores the first byte sequence V′ by the following formula:

[0012]

[0013] when When the result of is a decimal, the first byte sequence y′ restored by the receiving end is wrong.

[0014] According to the embodiments of the present invention, there are at least the following technical effects:

[0015] Since data transmission in a symmetric discrete memoryless channel is error-prone, the relevant scheme needs to be 2 m The error correction action is completed by checking once, and the amount of calculation is large. In order to solve the problem of fast verification, this method uses the condition of "odd numbers cannot divide even numbers" to perform byte operations on the binary sequence V on the basis of related schemes, and uses mathematical methods to give the binary sequence V a definite error detection judgment basis. After receiving the data, the receiving end realizes fast verification of the data through the definite error detection judgment basis. This method will not reduce the transmission rate of data in the symmetric discrete memoryless channel, nor will it increase the length of the encoded bytes, and will not change the encoding code rate. It can effectively reduce the complexity of verification judgment and improve the calculation efficiency of related schemes.

[0016] A second aspect of the present invention provides a system for improving error detection performance of Jelling code error correction, including a transmitting end and a receiving end, wherein:

[0017] The transmitting end is used to convert the binary sequence V obtained by weighted probability arithmetic coding of the source sequence into a first byte sequence V′, where y i∈{0, 1, ..., 255}, m represents the sequence length of the binary sequence V, represents the rounding down of m / 8; generating a second byte sequence Q according to the first byte sequence V′, wherein A third byte sequence Q′ is generated according to the second byte sequence Q, wherein Y i ′=Y i +Y i+1 , Y′ i+1 =Y i+1 -Y i ; Sending the third byte sequence Q′ to the receiving end through a symmetric discrete memoryless channel;

[0018] The receiving end is used to receive the sequence output by the symmetric discrete memoryless channel, and restore the first byte sequence V′ through the following formula:

[0019]

[0020] and when When the result is a decimal, the restored first byte sequence V′ is wrong.

[0021] According to the embodiments of the present invention, there are at least the following technical effects:

[0022] Since data transmission in a symmetric discrete memoryless channel is error-prone, the relevant scheme needs to be 2 m The error correction action is completed by checking once, and the amount of calculation is large. In order to solve the problem of fast verification, based on the relevant scheme, the sender uses the condition of "odd numbers cannot divide even numbers" to perform byte operations on the binary sequence V, and uses mathematical methods to give the binary sequence y a definite error detection judgment basis. After receiving the data, the receiver implements fast verification of the data through the definite error detection judgment basis, which will not reduce the transmission rate of the data in the symmetric discrete memoryless channel, nor increase the length of the encoded byte, and does not change the encoding code rate. It can effectively reduce the complexity of verification judgment and improve the calculation efficiency.

[0023] According to a third aspect of the present invention, an electronic device is provided, comprising at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions executable by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the above-mentioned method for improving the error detection performance of the Jelling code error correction.

[0024] According to a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the above-mentioned method for improving the error detection performance of the Jelling code error correction.

[0025] It should be noted that the beneficial effects between the third aspect and the fourth aspect of the present invention and the prior art are the same as the beneficial effects between the above-mentioned method for improving the error detection performance of the Jelling code error correction and the prior art, and will not be described in detail here.

[0026] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0028] Figure 1 This is a flowchart of the error correction process of the Jelling code;

[0029] Figure 2 A schematic diagram of the structure of a system for improving the error detection performance of Jelling code error correction provided by an embodiment of the present invention;

[0030] Figure 3 A flowchart of a method for improving the error detection performance of Jelling code error correction provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0032] Related program introduction section;

[0033] To facilitate the understanding of those skilled in the art, the following briefly introduces the error correction process of the Jelling code:

[0034] First, the transmitter processes the source sequence X into sequence Y and performs weighted probability arithmetic coding on sequence Y (sequence Y is not listed separately):

[0035] (1) Initialization parameters, R0←1, L0←0, p←0, i←1. R0 represents the encoding variable R i The initial value of L0 represents the encoding variable L i The initial value of , ← represents the left assignment operator.

[0036] (2) The number of symbols 0 in the statistical sequence X is denoted by c.

[0037] (3) Where p represents the probability of symbol 0 in sequence Y, and n represents the sequence length of sequence X. Here, the source processing process of sequence X has been integrated into the encoding step. The source processing here is to replace each symbol "1" in sequence X with the symbol "10".

[0038] (4) r max Indicates the maximum value of the weight coefficient of weighted probability arithmetic coding.

[0039] (5) Get the i-th symbol x in sequence X i The sequence X here is the sequence X after the source processing in the above steps (1) and (2). Please pay attention to the distinction.

[0040] (6) If x i =0, then R i ←R i-1 r max p.

[0041] (7) If x i =1, then R i ←R i-1 r max 2 p(1-p) and L i ←L i-1 +R i-1 r max p.

[0042] (8)i←i+1.

[0043] (9) If i≤n, repeat the above steps (5) to (9).

[0044] (10) Convert L into a binary sequence V of length m. It should be noted that L here represents the sequence output after encoding the last symbol in the sequence X.

[0045] (11) Send sequence V to the receiving end through the DMC channel.

[0046] Second, the DMC channel outputs the sequence U. Assuming that the channel is transmitted error-free, the receiving end (i.e., the decoding end) obtains V, c, and n, and converts V into a real number v. According to Figure 1 , let q i is the i-th symbol in sequence Q, l = 2n-c. The decoding steps at the receiving end are as follows:

[0047] (1) Initialize parameters, R0←1, L0←0, i←1, H←0, s←0, p←0. Where s represents the last decoded symbol.

[0048] (2)

[0049] (3)

[0050] (4)H←L i-1 +R i-1 r max p.

[0051] (5) When u≥H and s=1, Q←null, and decoding ends.

[0052] (6) When L ≥ H and s = 0, q i ←1,s←1,R i ←R i-1 r max (1-p), L i ←L i-1 +R i-1 r max p.

[0053] (7) When L<H and s=1, s←0, R i ←R i-1 r max p.

[0054] (8) When L<H and s=0, q i ←0,s←0,R i ←R i-1 r max p.

[0055] (9)i←i+1.

[0056] (10) If i≤l, repeat the above steps (4) to (10).

[0057] (11) Return the sequence Q.

[0058] The receiving end compares sequence Q with sequence Y (adding a symbol 0 after each symbol 1 in source sequence X to obtain sequence Y). When sequence Q is consistent with sequence Y, source sequence X is restored based on sequence Q; when sequence Q is inconsistent with sequence Y, forward error correction is performed on sequence Q until sequence Q is consistent with sequence Y. Since the content sent by the transmitting end to the DMC channel does not contain sequence Y, the criterion for the receiving end to determine whether sequence Q is consistent with sequence Y is to determine whether the decoded sequence Q satisfies equation (1). Here and in the attached Figure 1 Formula (1) in is: The number of consecutive symbol 1s in the sequence is at most 1.

[0059] Third, the receiving end performs the forward error correction process as follows (taking BEC(ε) as an example):

[0060] Assume there are e erasure symbols in sequence U The value is {0, 1}, and the e erasure symbols are recorded in sequence as Let i=1, 2,...,2 e , and get Table 1.

[0061]

[0062] Table 1

[0063] As shown in Table 1, the i-th method assigns values ​​to e erasure symbols in sequence U. For example, when i=1 When i=2 Then, the sequence U is substituted into the above weighted probability arithmetic decoding and the decoding process is repeated. If Q≠null, the forward error correction decoding is completed. The steps are as follows:

[0064] (1) Initialization parameters, i←1.

[0065] (2) Assign values ​​to the e erasure symbols in sequence U according to the i-th method in Table 1.

[0066] (3) Substitute U into the weighted probability arithmetic decoding.

[0067] (4) If i≤2 e And Q≠null, decoding is completed and ends.

[0068] (5)If i<2 e And Q=null, i←i+1, repeat steps (2) to (5).

[0069] Because 2 e includes all possibilities, so 2 e There is at least one possibility among the possibilities that makes the sequence Q satisfy equation (1).

[0070] Examples section;

[0071] In the related scheme, the receiving end performs forward error correction after performing Jelling code error detection on the BSC or BEC channel, and needs to perform a negation operation on each bit. When m=32, 2 operations are required. m The error correction action is completed after checking for times. As m increases, the amount of computation increases exponentially. It should be noted that the embodiment of the present application mainly includes the error detection process, and does not involve a specific error correction process or a source processing process.

[0072] In order to solve the technical defects of the relevant solutions, refer to Figure 2 and Figure 3 An embodiment of the present application provides a system for improving the error detection performance of a Jelling code error correction, including a transmitting end (i.e., an encoding end) and a receiving end (i.e., a decoding end). The system mainly implements a method for improving the error detection performance of a Jelling code error correction. The process of the method is as follows:

[0073] Step S101: The transmitting end obtains a binary sequence V obtained by weighted probability arithmetic coding of a source sequence.

[0074] The related technology of obtaining the binary sequence V by weighted probability arithmetic coding of the sequence has been introduced in the above "introduction to related schemes" and will not be described in detail here.

[0075] The related scheme sends the sequence V directly to the receiving end through the DMC channel. The receiving end receives the sequence U, performs error detection by the Jellien code, and then performs forward error correction. When the length of the encoded byte is not increased and the encoding code rate is not changed, the mathematical properties of the channel capacity that can be reached by the Jellien code are not affected. In order not to reduce the transmission rate, only a certain error detection judgment basis can be given to the binary sequence V. Then the sending end performs the subsequent steps S102 to S104.

[0076] Step S102: The sending end converts the binary sequence V into a first byte sequence V′, where y i ∈{0, 1, ..., 255}, m represents the sequence length of the binary sequence V, Indicates the rounding down of m / 8.

[0077] Step S103: The sending end generates a second byte sequence Q according to the first byte sequence V′, where

[0078] Step S104: The sending end generates a third byte sequence Q′ according to the second byte sequence Q, where Y i ′=Y i +Y i+1 , Y′ i+1 =Y i+1 -Y i .

[0079] Step S105: The sending end sends the third byte sequence Q′ to the receiving end through the symmetric discrete memoryless channel.

[0080] Step S106: The receiving end receives the sequence output by the symmetric discrete memoryless channel, and restores the first byte sequence V′ by the following formula:

[0081]

[0082] Step S107: When the result is a decimal, the first byte sequence V′ restored by the receiving end is wrong.

[0083] It should be noted that in step S103, the same symbols "Q" and "Y" are used as in the above "Introduction to Related Solutions", but they represent different contents. Please be careful to distinguish them. For steps S106 and S107, since the third byte sequence Q' may contain errors after being transmitted through the DMC channel, and Y i ′,Y i and i are all integers. i ′-Y′ i+1 When is an odd number, You will get a decimal number, then Y i ' or Y' i+1 A bit error must have occurred. i ′-Y′ i+1 The probability of being an odd number is (In the integer domain, odd numbers and even numbers each account for half, so the probability of odd numbers and even numbers appearing is 1 / 2), let the DMC channel bit error rate be ξ, because "Y i ′-Y′ i+1 is an odd number" and "bit error occurs in the DMC channel" are independent events, so the bit error rate of the DMC channel is ξ and Y i ′-Y′ i+1 The probability of being an odd number is P(p,ξ), that is, the joint probability is:

[0084]

[0085] It can be obtained from the above formula of joint probability that half of the errors in the DMC channel bit error rate ξ can be quickly checked by this method.

[0086] Since data transmission in a symmetric discrete memoryless channel is error-prone, the relevant scheme needs to be 2 m The error correction action is completed by checking once, and the amount of calculation is large. In order to solve the problem of fast verification, this method uses the condition of "odd numbers cannot divide even numbers" to perform byte operations on the binary sequence V on the basis of related schemes, and uses mathematical methods to give the binary sequence V a certain error detection judgment basis. After receiving the data, the receiving end implements the soft judgment criterion of the data through the error detection judgment basis to achieve fast verification. Half of the errors can be realized by this method. Fast error verification will not reduce the transmission rate of data in a symmetric discrete memoryless channel, nor will it increase the length of the encoded byte, and will not change the encoding code rate. It can effectively reduce the complexity of verification judgment and improve the computational efficiency of related schemes.

[0087] An embodiment of the present invention provides an electronic device; the electronic device may be any type of intelligent terminal, such as a mobile phone, a tablet computer, a personal computer, etc. Specifically, the electronic device includes: one or more control processors and a memory, and this example takes a control processor as an example. The control processor and the memory may be connected via a bus or other means, and this example takes the connection via a bus as an example.

[0088] As a non-transitory computer-readable storage medium, the memory can be used to store non-transitory software programs, non-transitory computer executable programs and modules. The control processor implements the error detection performance improvement method of the Jelling code error correction in the above method embodiment by running the non-transitory software programs, instructions and modules stored in the memory. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function; in addition, the memory may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk storage device, a flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the control processor, and these remote memories may be connected to the electronic device via a network. Examples of the above network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof. The one or more modules are stored in the memory, and when executed by the one or more control processors, the error detection performance improvement method of the Jelling code error correction in the above method embodiment is executed. For example, the execution of the above description Figure 3 Method steps S101 to S107.

[0089] The embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are executed by one or more control processors, for example, so that the one or more control processors can execute the error detection performance improvement method of the Jelling code error correction in the above method embodiment. Figure 3 Method steps S101 to S107.

[0090] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a general hardware platform. Those skilled in the art can understand that all or part of the processes in the above embodiment method can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and the program can include the process of the embodiment of the above method when executed. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0091] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0092] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for improving the error detection performance of Jelling code error correction, characterized in that: The steps include: The sending end obtains the binary sequence V obtained by weighted probability arithmetic coding of the source sequence; The transmitting end converts the binary sequence V into a first byte sequence V′, where y i ∈{0,1,…,255}, m represents the sequence length of the binary sequence V, It means m / 8 is rounded down; The transmitting end generates a second byte sequence Q according to the first byte sequence V′, wherein The transmitting end generates a third byte sequence Q′ according to the second byte sequence Q, wherein Y′ i =Y i +Y i+1 ,Y′ i+1 =Y i+1 -Y i ; The transmitting end sends the third byte sequence Q′ to the receiving end through a symmetric discrete memoryless channel; The receiving end receives the sequence output by the symmetric discrete memoryless channel, and restores the first byte sequence V′ by the following formula: when When the result of is a decimal, the first byte sequence V′ restored by the receiving end is wrong.

2. The method for improving the error detection performance of the Jelling code error correction according to claim 1, characterized in that: The symmetric discrete memoryless channel includes a binary symmetric channel or a binary erasure channel.

3. A system for improving error detection performance of Jelling code error correction, characterized in that: It includes a sending end and a receiving end, where: The transmitting end is used to convert the binary sequence V obtained by weighted probability arithmetic coding of the source sequence into a first byte sequence V′, where y i ∈{0,1,…,255}, m represents the sequence length of the binary sequence V, represents the rounding down of m / 8; generating a second byte sequence Q according to the first byte sequence V′, wherein A third byte sequence Q′ is generated according to the second byte sequence Q, wherein Y′ i =Y i +Y i+1 ,Y′ i+1 =Y i+1 -Y i ; Sending the third byte sequence Q′ to the receiving end through a symmetric discrete memoryless channel; The receiving end is used to receive the sequence output by the symmetric discrete memoryless channel, and restore the first byte sequence V′ through the following formula: and when When the result is a decimal, the restored first byte sequence V′ is wrong.

4. An electronic device, characterized in that: It includes at least one control processor and a memory for communicating with the at least one control processor; the memory stores instructions that can be executed by the at least one control processor, and the instructions are executed by the at least one control processor so that the at least one control processor can execute the error detection performance improvement method of the Jelling code error correction as described in any one of claims 1 to 2.

5. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for improving the error detection performance of the Jelling code error correction according to any one of claims 1 to 2.

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