Manufacturing plant management with dynamic sampling planning, optimized wafer measurement paths, and optimized wafer transportation using quantum computing

Abstract

The present invention provides a system and method for optimizing wafer transportation and metrology measurement in a manufacturing plant. The method includes: deriving and updating a dynamic sampling plan that provides wafer-specific measurement sites and conditions; deriving an optimized wafer measurement path for metrology measurement of the wafer corresponding to the dynamic sampling plan; managing FOUP (front opening wafer transport box) transportation through the manufacturing plant, thereby transporting wafers to measurement tools, and providing the dynamic sampling plan and the wafer measurement path to the corresponding measurement tool before or when the FOUP and the corresponding wafer are transported to the corresponding measurement tool; and the corresponding measurement tool performs metrology and / or verification measurement of the corresponding wafer according to the derived wafer measurement path. Quantum computing resources can be used to solve corresponding specific optimization problems to reduce the time required, improve computing solutions, and improve the manufacturing plant yield and the accuracy of the produced wafers.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor production, and more particularly to the optimization of production and metrology processes using quantum computing. Background Art

[0002] As Moore's law progresses, various advancements and complexities of processes in semiconductor fabs (semiconductor manufacturing plants) emerge. Wafers typically move between production tools, which apply production steps (e.g., forming devices and target elements in layers on the wafer), and metrology and / or inspection tools, which measure target sites on the wafer and verify that the production steps are performed correctly (within defined specifications). Metrology tools perform metrology measurements using measurement variables, which are typically predetermined using initial training or simulation data and are consistently applied to all wafers (at least in one or more wafer batches) - to produce measurement data that is processed by one or more processors, which control the production process and the physical movement of wafers through the fab among production and metrology tools.

[0003] As examples of process complexity, (i) managing wafer transport (among thousands of FOUPs - front opening pods, which are components for holding and transporting silicon wafers between tools) between hundreds of tools (e.g., for performing process steps such as etching, CMP - chemical mechanical processing, deposition, implantation, and lithography, and for performing metrology and inspection steps) is a daunting optimization problem, especially in foundries that provide many process features to different customers with different urgency levels; (ii) there is an increase in required metrology sampling per wafer from hundreds of points per wafer to more than a thousand points per wafer due to increased sensitivity of measurements to process variations, matching between scanner types, etc.; (iii) metrology and inspection increase in both volume and sophistication as more data is collected and analyzed with complex methods (e.g., big data techniques, machine learning, etc.). These data analysis methods are expected to increase in sophistication and may challenge current tool computing infrastructure.

[0004] With respect to (i), manufacturing plant optimization processes include planning, scheduling, costing, statistical process control, etc., and are performed by specialized systems called manufacturing execution systems (MES). However, these optimization problems quickly grow in complexity and demand for computing resources and increasingly require more time than operating a manufacturing plant can afford.

[0005] With respect to (ii), predefined metrology sampling plans are typically adaptive per wafer or batch based on a priori knowledge, such as the results of different types of previous measurements indicating metrology sensitivity to process variations. For example, a previous overlapping measurement flag may be used to indicate that the next measurement of the same or adjacent site may be a fly-by (anomaly) or contribute to residuals and should therefore be omitted from the sampling plan. Another motivation for changing the sampling plan is to distribute overlapping measurements between batches of wafers to overcome known process variation distributions and reduce the number of samplings. As processes become more complex, sampling plans become more densely populated per wafer point and the points are less systematically distributed across the wafer, which may change the point distribution between wafers. In this reality, path optimization (i.e., the path that a wafer takes between measurement points in a metrology tool) becomes critical to the amount of time a wafer spends on the tool for measurement. This means that path optimization is important for throughput (TPT - throughput time). The optimal path optimization scheme currently used in overlapping tools is based on a nearest neighbor algorithm, which is a compromise between TPT and path optimization computation time. As computing power increases, more advanced algorithms can be used for path optimization. Summary of the invention

[0006] The following is a simplified summary to provide an initial understanding of the invention. The summary does not necessarily identify key elements nor limit the scope of the invention, but merely serves as an introduction to the following description.

[0007] One aspect of the present invention provides a method for optimizing wafer transportation and metrology measurements in a semiconductor fabrication plant (fab), the method comprising: deriving and updating a dynamic sampling plan that provides wafer-specific measurement locations and conditions, wherein the dynamic sampling plan differs between wafers; deriving an optimized wafer measurement path for metrology measurements of the wafer corresponding to the corresponding derived and updated dynamic sampling plan; managing FOUP (front opening wafer transport box) transportation through the fabrication plant to transport wafers to a metrology tool, and providing the dynamic sampling plan and the wafer measurement path to the corresponding measurement tool before or when the FOUP and the corresponding wafer are transported to the corresponding measurement tool; and performing metrology and / or inspection measurements of the corresponding wafer by the corresponding measurement tool according to the derived wafer measurement path.

[0008] One aspect of the present invention provides a system for optimizing wafer transportation and metrology measurements in a semiconductor fabrication plant (fab), the system comprising: a sampling plan optimization module configured to derive and update a dynamic sampling plan that provides wafer-specific measurement locations and conditions, wherein the dynamic sampling plan differs between wafers; a measurement path optimization module configured to derive an optimized wafer measurement path for metrology measurements of the wafer corresponding to the corresponding derived and updated dynamic sampling plan; a FOUP transportation optimization module configured to manage FOUP transportation through the fabrication plant, thereby transporting wafers to a measurement tool, and providing the wafer measurement path to the corresponding measurement tool before or when the FOUP and the corresponding wafer are transported to the corresponding measurement tool, wherein the corresponding measurement tool is configured to perform metrology and / or inspection measurements of the corresponding wafer according to the derived wafer measurement path.

[0009] These, additional and / or other aspects and / or advantages of the invention are set forth in the detailed description which follows; may be inferred from the detailed description; and / or may be learned by practice of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a better understanding of embodiments of the invention and to show how they may be practiced, reference will now be made, by way of example only, to the accompanying drawings in which like numerals designate corresponding elements or sections throughout.

[0011] In the attached picture:

[0012] Figure 1 is a high-level schematic illustration of a system for optimizing wafer transport and metrology measurements in a semiconductor fabrication facility (fab) according to some embodiments of the present invention.

[0013] Figure 2 is a high-level flow chart illustrating a method of optimizing wafer transport and metrology measurements in a fabrication plant, according to some embodiments of the present invention. DETAILED DESCRIPTION

[0014] In the following description, various aspects of the present invention are described. For the purpose of explanation, specific configurations and details are stated to provide a thorough understanding of the present invention. However, it will also be apparent to those skilled in the art that the present invention can be practiced without the specific details presented herein. In addition, well-known features may have been omitted or simplified so as not to obscure the present invention. With specific reference to the drawings, it should be emphasized that the details shown are presented only by way of example and only for the purpose of illustrative discussion of the present invention, and are presented in order to provide what is believed to be the most useful content and to make the explanation of the principles and concepts of the present invention easy to understand. In this regard, the level of detail of the structural details of the present invention shown is only necessary for a basic understanding of the present invention, and the description using the drawings makes it apparent to those skilled in the art how several forms of the present invention can be embodied in practice.

[0015] Before explaining at least one embodiment of the present invention in detail, it should be understood that the present invention is not limited in its application to the details of the construction and the arrangement of components set forth in the following description or illustrated in the drawings. The present invention is applicable to other embodiments and combinations of the disclosed embodiments that can be practiced or implemented in various ways. Likewise, it should be understood that the idioms and terms used herein are for illustrative purposes and should not be considered limiting.

[0016] Unless specifically stated otherwise as will be apparent from the following discussion, it should be understood that throughout this specification discussion, terms such as "processing," "computing," "calculating," "determining," "enhancing," "deriving," and the like are utilized to refer to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulates data represented as physical (e.g., electronic) quantities within registers and / or memories of the computing system and / or transforms the data into other data similarly represented as physical quantities within the memory, registers, or other such information storage, transmission, or display devices of the computing system. In certain embodiments, the illumination techniques may include electromagnetic radiation in the visible range, ultraviolet radiation such as x-rays, or even shorter wave radiation, and possibly even particle beams.

[0017] Embodiments of the present invention provide efficient and economical methods and mechanisms for optimizing and managing a range of semiconductor fab processes, such as wafer traffic, wafer sampling plan paths, and metrology data analysis, and thereby provide improvements in the field of semiconductor production technology. Systems and methods for optimizing wafer transportation and metrology measurements in a fab are provided. The method includes: deriving and updating a dynamic sampling plan that provides wafer-specific measurement locations and conditions; deriving an optimized wafer measurement path for metrology measurements of wafers corresponding to the dynamic sampling plan; managing FOUP (front opening wafer transport box) transportation through the fab, thereby transporting wafers to measurement tools, while providing the dynamic sampling plan and wafer measurement path to the corresponding measurement tool before or when the FOUP and the corresponding wafer are transported to the corresponding measurement tool; and performing metrology and / or inspection measurements of the corresponding wafer by the corresponding measurement tool according to the derived wafer measurement path. Quantum computing resources can be used to solve corresponding specific optimization problems to reduce the time required, improve computing solutions, and improve the fab yield and the accuracy of the produced wafers. It should be noted that the term "fab" as used herein refers to both a manufacturing plant, which includes design operations in addition to device fabrication operations, and a foundry, which typically handles only fabrication operations, typically for multiple customers.

[0018] Figure 1 is a high-level schematic illustration of a system 100 for optimizing wafer transport and metrology measurements in a semiconductor fabrication facility (fab) according to some embodiments of the present invention. The system 100 may be configured to improve the performance of a fabrication facility, which schematically includes: a plurality of processing tools 90 (denoted as P#1, P#2, P#3 ... P#n) configured to process wafers and deliver reports and log files 92; a plurality of metrology and / or inspection tools 80 (denoted as M / I#1, M / I#2, M / I#3 ... M / I#n) configured to measure wafers and provide results and flags 82; a FOUP (front opening pod) transport system 85 configured to deliver wafers to the processing tools 90 and the metrology and inspection tools 80.

[0019] In various embodiments, the system 100 includes modules and implements methods for enhancing throughput of a fabrication plant, improving process accuracy, and / or handling an increasing abundance of process-related data and metrology data about wafers. Advantageously, the system 100 and method 200 described herein may be configured to implement a dynamic sampling plan by providing a specific sampling plan and / or associated measurement path per wafer and / or per FOUP based on, for example, any of the following: previous metrology and / or verification measurements 82 of the same wafer made by the same tool 80; previous metrology and / or verification measurements 82 of the same wafer made by other tools 80; any a priori data about the wafer, such as processing tool log files 92, statistical distribution of sampling results within and between FOUPs for deriving improved modeling and reduced residuals and / or overall TPT (throughput time) data. The dynamic sampling plan may be calculated and / or optimized by the system 100, which may implement a quantum computer and / or processor, and may be sent by the system 85 to the respective tools 80, 90 in parallel with the FOUP transport, so that when the wafer is loaded to the tool, the tool is ready with the updated sampling plan and associated measurement path. The system 100 may be configured to provide the sampling plan and measurement path to the respective tool before or when the corresponding wafer is transported to the tool to enable immediate measurement and / or to reduce the computational load on the tool itself.

[0020] For example, in certain embodiments, the system 100 includes a dynamic sampling plan optimization module 115 configured to derive and update a dynamic sampling plan 110 that provides wafer-specific measurement sites and conditions and is located between wafers. For example, the dynamic sampling plan 110 may define specific sites and locations within those sites to be measured on each wafer. The dynamic sampling plan 110 may vary between wafers according to the relevant production process and stage, identifying process errors or inaccuracies and previous measurements of the same wafer in other wafers - all of which may be used to indicate preferred measurement sites that may be incorporated into the dynamic sampling plan 110 and changed as production of the wafers proceeds. The dynamic sampling plan optimization module 115 may be configured to update the dynamic sampling plan 110 according to the analyzed metrology and / or inspection measurements. The dynamic sampling plan 110 may be adjusted during the process to identify process errors as they occur and possibly correct them in real time.

[0021] The timing of deployment of the dynamic sampling plan 110 to the metrology and / or inspection tools 80 may be determined as part of the remainder of the production process, e.g., in relation to the (optimized) movement of wafers through the fabrication plant, the determined (optimized) movement patterns over the sites on each wafer, and the (optimized) selected metrology tools 80, as described below.

[0022] In various embodiments, the dynamic sampling plan optimization module 115 may include or be associated with a dedicated processor 112 configured to perform optimization of the dynamic sampling plan 110. The dedicated processor 112 may include at least one quantum computer (for a possible dedicated quantum processor, in Figure 1 Indicated as D / Q).

[0023] In certain embodiments, the system 100 includes a measurement path optimization module 135 configured to derive an optimized wafer measurement path 130 for metrology measurements of a wafer corresponding to a corresponding derived and updated dynamic sampling plan 110. The inventors have noted that measurement paths become more complex as the number of metrology measurement sites continues to increase due to shrinking device size and increasing device complexity (e.g., background art wafers typically include hundreds of metrology measurement sites, while future wafers are expected to include thousands of metrology measurement sites). Moreover, device complexity also requires tighter accuracy specifications resulting in smaller and more targets that may optionally be set per die and further complicate the measurement path. Ultimately, more complex devices and more targets are also produced and measured by more tools, thereby contributing to the complexity of the process and management of production. The disclosed measurement path optimization module 135 may be configured to handle the increased complexity by deriving more efficient measurement paths among targets on a wafer, thereby shortening measurement time and reducing required stage movement.

[0024] In various embodiments, the measurement path optimization module 135 may be configured to supplement and / or replace measurement path calculations at the metrology and / or inspection tool 80. For example, the optimized measurement path 130 may be derived from the respective dynamic sampling plan 110 and delivered to the respective tool 80 before or upon delivery of the wafer to the respective tool. Alternatively or in addition, the measurement path optimization module 135 may be configured to computationally support the respective metrology tool 80 as it derives wafer measurement paths for metrology measurements from the respective derived and updated dynamic sampling plan 110.

[0025] In various embodiments, the measurement path optimization module 135 may include or be associated with a dedicated processor 132 configured to perform optimization of the measurement path 130. The dedicated processor 132 may include at least one quantum computer (for a possible dedicated quantum processor, in Figure 110). For example, the measurement path optimization module 135 may be configured to optimize the wafer measurement path 130 with respect to the wafer measurement speed and according to a given measurement time specified by the dynamic sampling plan 110, for example, by implementing at least one TSP (traveling salesman problem) algorithm or an equivalent algorithm. In certain embodiments, the TSP algorithm or an equivalent algorithm may be adapted to be processed by at least one quantum computer, such as the dedicated processor 132.

[0026] The inventors have noted that the complex measurement path optimization problem can be understood as being similar to the TSP, with the goal of finding the shortest possible route that visits each city and returns to the starting city given a list of cities and the distances between each pair of cities. The measurement path optimization problem can be viewed as being analogous to the TSP, where the measurement sites on the wafer are analogous to the different cities, and the starting point is analogous to the measurement point of the wafer closest to the loader robot that loads and unloads the wafer from the tool. The shortest traveling salesman path is analogous to the shortest time a wafer spends on the tool. This understanding contrasts with current path selection methods, which include: systematically traversing the wafer in straight lines for continuous measurements using a single sampling plan per layer that is changed manually from time to time; using a nearest neighbor algorithm for path optimization for continuous measurements, using the tool's computer for path optimization - the path optimization therefore requires more points per wafer than is needed to give the best correction (metrology parameters) for a single sampling plan, and is fully optimized to overcome a specific process variation distribution on the wafer. Moreover, current methods are known to not produce the shortest TSP path. Because the TSP belongs to a class of problems known as "discrete optimization problems," it is, in principle, well suited to being solved by, for example, a type of quantum computer known as a "quantum annealer," which may be implemented as at least a portion of the measurement path optimization module 135, to provide a dramatic breakthrough in computational speed because the shortest path can be found through the quantum property of the computer enabling "tunneling" to the optimal solution.

[0027] For example, measurement path optimization may be initiated when the wafer is delivered to the production tool using, for example, prior knowledge, previous measurement results (of different types), multi-wafer optimization schemes, and / or other optimization inputs. The TSP algorithm may be configured to provide an optimal tradeoff between computation time and wafer measurement time for any given computation power and measurement speed. Moreover, in certain embodiments, the use of a measurement path optimization module 135 with a dedicated processor may remove background technical limitations of computation time and available computation power to avoid limiting wafer sampling process optimization. For example, a 5D infrastructure with past measurement history per wafer and modeling and / or accuracy preferences may be used to determine an optimal sampling plan per wafer. In certain embodiments, the measurement path optimization module 135 may be further configured to implement dynamic optimization with respect to multiple wafers and / or wafer batches. For example, a dynamic sampling plan may be used for improved performance, as discussed above. Advantageously, since the number of measurements per wafer and wafer measurement time are key business parameters, their optimization is very beneficial to improving overall semiconductor production efficiency. Advantageously, the use of a measurement path optimization module 135 may remove background technical limitations of computation time and available computation power to avoid limiting wafer sampling process optimization.

[0028] In certain embodiments, the measurement tool 80 may include at least one stepwise operation metrology tool and at least one scanning metrology tool. Examples for scanning metrology tools are provided in WIPO application No. PCT / US18 / 18588, which is incorporated herein by reference in its entirety, teaching real-time derivation of metrology target positions on a wafer and possible target focus positions during movement of the wafer on the stage of the system. Positioning data may be derived before the target reaches its position (in real time), thereby freeing up the time required to acquire the stage in the background art and increasing the throughput of the system and method. The collection channel may be split to provide an additional mobile imaging channel including at least one TDI (time delay and integration) sensor with an associated analysis unit, the associated analysis unit being configured to derive wafer surface information, positioning of the metrology target relative to the objective lens during wafer positioning movement toward the metrology target, and / or focus information. The derived position and / or focus information of the mobile module and possible feedback to the stage during additional focusing may enhance the accuracy of stopping of the stage. As the number of sites increases from hundreds to thousands per wafer, scanning metrology tools may be applied to multiple adjacent sites on a wafer, for example, as part of a dynamic sampling plan 110. For example, scanning metrology tools may be applied to stretches of adjacent sites, while step-operation metrology tools may be applied to sites that are far from each other. In certain embodiments, a sampling plan optimization module 115 may be configured to optimize the scanning / step-operation metrology tools used based on the desired metrology performance, for example, with respect to travel time within and between sites, and with respect to measurement parameters such as lighting and accuracy. The parameters of the scanning tools may be part of optimizing the dynamic sampling plan 110. The system 100 may further be configured to allocate sufficient memory and processing power for handling measurements by the scanning tools in a manner that compensates for the challenges of measurements during movement, such as lower lighting and integration of multiple grasps. Big data methods may be applied to scanning measurements, as discussed below. A dedicated (e.g., quantum) processor or computer 112 may be applied as a whole to handle the scanning metrology tools and optimize their integration within the dynamic sampling plan 110 and the production process in the manufacturing plant.

[0029] In certain embodiments, the system 100 may be configured to co-optimize the dynamic sampling plan 110 and the wafer measurement path 130 with respect to the assignment 117 of the step and scan metrology tools 80 to minimize wafer measurement time. For example, a scanning metrology tool may be assigned to measure a stretch of adjacent wafer sites as long as the transition between types of metrology tools does not incur too large a time penalty relative to the time saved by the scanning tool.

[0030] In certain embodiments, the system 100 includes a metrology big data analysis module 140 configured to apply a big data analysis process to analyze metrology and / or inspection measurements. In various embodiments, big data methods may be implemented on metrology measurements to enhance information derived from the measurements and to extract additional information from multiple previously unrelated measurements. For example, over-measurements that may currently be detrimental to metrology output may be exploited to derive more accurate results with big data methods (e.g., using artificial intelligence (AI) algorithms), such as identifying a global minimum of residual inaccuracy rather than a currently identified local minimum. In big data methods, metrology algorithms may be configured to utilize current as well as past measurements, and may not be limited to the types of metrology measurements used in modeling, such as both image and interferometric measurements, and measurements under multiple conditions (e.g., lighting parameters that may be exploited to derive metrology results). Moreover, big data methods may be used to analyze measurement data from scanning metrology tools, which may be more extensive and require more processing relative to data from step-wise operating metrology tools, as disclosed above. A dedicated (eg, quantum) processor or computer 142 may be applied as a whole to process big data from the metrology tool 80 and optimize its analysis, thereby enabling further or more frequent updates to the dynamic sampling plan 110 and improving the production process in the manufacturing plant.

[0031] In certain embodiments, the system 100 includes a FOUP (front opening wafer transfer box) transportation optimization module 120, which is configured to manage the transportation of FOUPs through the manufacturing plant (via the FOUP transportation system 85), thereby transporting wafers to the measurement tool 80, and providing a wafer measurement path 130 to the corresponding measurement tool before or when the FOUP and the corresponding wafer are transported to the corresponding measurement tool 80.

[0032] In various embodiments, the FOUP transport optimization module 120 may include or be associated with a dedicated processor 122 configured to perform optimization of FOUP transport among a large number of process tools 90 and metrology / inspection tools 80 in a manufacturing facility and with respect to the dynamic sampling plan 110 and the estimated durations of processes and measurements (e.g., associated with the measurement path 130). The dedicated processor 122 may include at least one quantum computer (for a possible dedicated quantum processor, in Figure 1 Indicated as D / Q).

[0033] In certain embodiments, the system 100 includes a fab management module 150 and / or a system controller 152 configured to provide the dynamic sampling plan 110 and the wafer measurement path 130 to the metrology tool 80 before or when the FOUP and the corresponding wafer are transported to the corresponding metrology tool, wherein the corresponding metrology tool 80 is configured to perform metrology and / or inspection measurements of the corresponding wafer according to the dynamic sampling plan 110 and the derived optimized wafer measurement path 130. The fab management module 150 and / or the system controller 152 may be further configured to assign the wafer to various processing tools 90 and metrology / inspection tools 80 to produce specific devices on the wafer and measure the produced features to ensure their compliance with specifications. When implemented, the fab management module 150 may include or be associated with the controller 152 and the dedicated processors 112, 122, 132, 142 of the management system 100 and modules 115, 120, 135, 140. The manufacturing plant management module 150 and / or the system controller 152 may include at least one of the following: a centralized quantum computer, a quantum computer network, a co-optimized quantum and classical computer network, and / or a network service including any of the same; and may be associated with any of the following: a dedicated (optional) quantum processor 112, 122, 132, and 142.

[0034] Certain embodiments include a system 100 for optimizing wafer transport and metrology measurements in a fabrication plant, the system comprising: a sampling plan optimization module 115 configured to derive and update a dynamic sampling plan 110 providing wafer-specific measurement locations and conditions that differ between wafers; a FOUP transport optimization module 120 configured to manage FOUP transport through the fabrication plant, thereby transporting wafers to metrology tools, and providing the dynamic sampling plan 110 to the respective metrology tools before or when the FOUPs and respective wafers are transported to the respective metrology tools. The respective metrology tools 80 may be configured to perform metrology and / or inspection measurements of the respective wafers according to a wafer measurement path 130 (e.g., provided by the system 100, calculated by the respective tool 80), optionally with computational support from the system 100 (e.g., via a measurement path optimization module 135 or a respective processor such as a dedicated processor 132).

[0035] Certain embodiments include a system 100 for optimizing wafer transportation and metrology measurements in a fabrication plant, the system comprising: a measurement path optimization module 135 configured to derive a corresponding optimized wafer measurement path 130 for metrology measurements of a wafer from a dynamic sampling plan 110; a FOUP transportation optimization module 120 configured to manage FOUP transportation through the fabrication plant, thereby transporting wafers to a metrology tool, while providing the wafer measurement path to the corresponding metrology tool before or when the FOUP and the corresponding wafer are transported to the corresponding metrology tool. The corresponding metrology tool 80 may be configured to perform metrology and / or inspection measurements of the corresponding wafer according to the wafer measurement path 130 and the dynamic sampling plan 110.

[0036] Advantageously, the disclosed embodiments provide a better solution to the fab optimization problem than current MES (manufacturing execution system) approaches, and furthermore enable real-time optimization of wafer handling processes in a fab. Alternatively or additionally, the MES algorithm may be modified for processing by a corresponding dedicated (e.g., quantum) computer of the system 100. Advantageously, the improved fab optimization may increase fab throughput and reduce its operating costs.

[0037] Advantageously, since quantum computers may be configured to handle certain difficult optimization problems more efficiently than classical computers, they may be applied to solve the wafer transport optimization problem (e.g., in TSP related formulations) within the system 100, e.g., via the FOUP transport optimization module 120. In certain embodiments, the quantum computer 115 may be configured to handle the problem of movement among sites on each wafer, e.g., via the measurement path optimization module 135, especially when the number of sites rises into the thousands. In certain embodiments, particularly where the fab is a foundry that supplies devices to many customers, the system 100 may be configured to optimize the production plan (e.g., via the fab management module 150) with respect to other optimization aspects of the production process as disclosed herein, such as specific customer requirements. In certain embodiments, a quantum computer may be used in the system 100 (e.g., in the fab management module 150 and / or in the controller 152) to handle the problem of finding a global (rather than a local) minimum in the fitting of metrology and / or inspection measurements to corresponding models to minimize corrections—a problem that becomes more difficult as the number of sites increases. In various embodiments, a dedicated quantum computer module may be integrated with a classical computer to provide rapid solutions to these or other optimization problems disclosed herein, thereby producing the hybrid controller 152 and / or the hybrid system 100 .

[0038] Elements from two or more disclosed embodiments of system 100 may be combined in any operable combination, and Figure 1The diagrammatic illustration of the modules in is for explanation purposes only and is non-limiting. Specifically, the disclosed combination can use quantum computing to optimize any of the following: wafer transport in a fabrication plant; wafer sampling planning paths and analysis of complex semiconductor metrology and inspection data.

[0039] Figure 2 is a high-level flow chart illustrating a method 200 of optimizing wafer transport and metrology measurements in a semiconductor fabrication facility (fab) (stage 205), according to some embodiments of the present invention. The method stages may be performed with respect to the system 100 described above, which may optionally be configured to implement the method 200. The method 200 may be implemented, at least in part, by at least one computer processor (e.g., as part of any of the modules in the system 100). Certain embodiments include a computer program product including a computer-readable storage medium having a computer-readable program embodied therewith and configured to perform the relevant stages of the method 200. In any of the disclosed embodiments, the computing resources may include any of the following: a centralized quantum computer, a network of quantum computers, a network of co-optimized quantum and classical computers, and / or a network service including any of the same. The method 200 may include the following stages, regardless of their order.

[0040] In various embodiments, the method 200 may include deriving and updating a dynamic sampling plan that provides wafer-specific measurement locations and conditions, wherein the dynamic sampling plan differs between wafers (stage 210) and / or deriving an optimized wafer measurement path for metrology measurements of the wafer corresponding to the respective derived and updated dynamic sampling plan (stage 220). The method 200 further includes managing FOUP (front opening pod) transportation through the fabrication facility to transport the wafers to the metrology tool (stage 230), providing the dynamic sampling plan and the wafer measurement path to the respective metrology tool before or while the FOUP and the respective wafer are transported to the respective metrology tool (stage 240); and performing metrology and / or inspection measurements of the respective wafer by the respective metrology tool according to the derived wafer measurement path (stage 250).

[0041] Method 200 may further include using a dedicated processor, which may include a quantum processor, to calculate and / or optimize a dynamic sampling plan (stage 212), calculate and / or optimize a wafer measurement path (stage 222), and / or calculate and / or optimize a FOUP transport (stage 232).

[0042] In certain embodiments, method 200 may include computing and / or optimizing the wafer measurement path using TSP or an equivalent algorithm, which may be adapted for implementation by a quantum computer or processor (stage 224).

[0043] In certain embodiments, method 200 may include computationally supporting a respective metrology tool in deriving an optimized wafer measurement path of metrology measurements from a respective derived and updated dynamic sampling plan (stage 225), e.g., to enhance computational power, reduce computational time, and relieve a processor of the metrology tool.

[0044] In certain embodiments, the metrology tools may include at least one step-operating metrology tool and at least one scanning metrology tool, and the method 200 may further include co-optimizing FOUP transport, dynamic sampling plan, and wafer measurement path with respect to allocation of the step and scan metrology tools to minimize wafer measurement time (stage 228), for example, where the scanning metrology tool is allocated to measure the spread of adjacent wafer sites.

[0045] In certain embodiments, method 200 may further include applying a big data analysis process to analyze metrology and / or verification measurements (stage 260) and optionally updating a dynamic sampling plan based on the analyzed metrology and / or verification measurements (stage 270). Method 200 may further include using a special purpose processor, which may include a quantum processor, to perform the big data analysis process (stage 262).

[0046] Aspects of the present invention are described above with reference to flowchart illustrations and / or partial diagrams of methods, devices (systems) and computer program products according to embodiments of the present invention. It will be understood that each part in the flowchart illustrations and / or partial diagrams and the combination of parts in the flowchart illustrations and / or partial diagrams are implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that instructions executed by the processor of the computer or other programmable data processing device establish means for implementing the functions / actions specified in the flowchart and / or one or more partial diagram portions.

[0047] These computer program instructions may also be stored in a computer-readable medium, which can direct a computer, other programmable data processing equipment or other devices to function in a specific manner so that the instructions stored in the computer-readable medium produce a product containing instructions for implementing the functions / actions specified in the flowchart and / or one or more portions of the diagram.

[0048] The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide a process for implementing the functions / actions specified in the flowchart and / or one or more partial diagram portions.

[0049] The foregoing flowcharts and diagrams illustrate the architecture, functionality and operation of possible implementation schemes of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each part in a flowchart or partial diagram may represent a module, a segment or a code portion, and the code includes one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative embodiments, the functions described in the part may not occur in the order described in the figure. For example, in fact, depending on the functionality involved, two parts of the continuous display may be executed roughly at the same time, or sometimes the parts may be executed in reverse order. It should also be noted that each part in the partial diagram and / or flowchart illustration and the combination of parts in the partial diagram and / or flowchart illustration can be implemented by a combination of a special-purpose hardware-based system or special-purpose hardware and computer instructions that performs a specified function or action.

[0050] In the above description, an embodiment is an example or implementation of the present invention. The various occurrences of "one embodiment", "embodiment", "certain embodiments", "some embodiments" do not necessarily all refer to the same embodiment. Although the various features of the present invention can be described in the context of a single embodiment, the features can also be provided individually or in any suitable combination. On the contrary, although the present invention can be described in the context of a single embodiment for clarity herein, the present invention can also be implemented in a single embodiment. Certain embodiments of the present invention may include features from different embodiments disclosed above, and certain embodiments may incorporate elements from other embodiments disclosed above. The disclosure of the elements of the present invention in the context of a particular embodiment should not be considered to limit the use of the elements alone in the particular embodiment. Moreover, it should be understood that the present invention can be implemented or practiced in various ways and that the present invention can be implemented in certain embodiments other than the embodiments outlined in the above description.

[0051] The present invention is not limited to those figures or corresponding specifications. For example, the process does not need to move through each illustrated frame or state, or in the order exactly the same as illustrated and described. Unless otherwise defined, the meaning of the technical and scientific terms used herein will generally be understood by a technician in the field of the technology to which the present invention belongs. Although the present invention has been described with respect to a limited number of embodiments, these embodiments should not be regarded as limitations on the scope of the present invention, but rather as demonstrations of some preferred embodiments in the preferred embodiments. Other possible changes, modifications and applications are also within the scope of the present invention. Therefore, the scope of the present invention should not be limited by what has been described so far, but by the appended claims and their legal equivalents.

Claims

1. A system for optimizing wafer transport and metrology measurements in a semiconductor manufacturing fab, the system comprising: At least one processor configured to: deriving and updating a dynamic sampling plan that provides wafer-specific measurement locations and conditions, wherein the dynamic sampling plan differs between wafers, deriving an optimized wafer measurement path for metrology measurements of the wafer corresponding to the derived and updated corresponding dynamic sampling plan, and managing front opening pod (FOUP) transport by the manufacturing plant so as to transport wafers to a metrology tool, and providing the optimized wafer measurement path to the corresponding metrology tool before or when the FOUP and the corresponding wafer are transported to the corresponding metrology tool, wherein the respective measurement tool is a metrology tool or an inspection tool configured to perform metrology and / or inspection measurements of the respective wafer according to the derived optimized wafer measurement path, and wherein the processor comprises at least one quantum computer.

2. The system of claim 1, wherein deriving and updating the dynamic sampling plan is associated with a special-purpose processor configured to perform the optimization of the dynamic sampling plan, wherein the special-purpose processor comprises at least one quantum computer.

3. The system of claim 1 , wherein deriving the optimized wafer measurement path is associated with a dedicated processor configured to perform the optimization of the wafer measurement path, wherein the dedicated processor comprises at least one quantum computer.

4. The system of claim 3, wherein deriving the optimized wafer measurement path is associated with optimizing the wafer measurement path with respect to wafer measurement speed and according to a given measurement time specified by the dynamic sampling plan.

5. The system according to claim 1, wherein the measuring tools include at least one step-by-step metrology tool and at least one scanning metrology tool, The processor is further configured to co-optimize the dynamic sampling plan and the wafer measurement path with respect to allocation of stepping and scanning metrology tools so that the dynamic sampling plan and the wafer measurement path have a minimum wafer measurement time, Wherein the scanning metrology tool is assigned to measure the extension of adjacent wafer sites.

6. The system of claim 1, wherein managing the FOUP transport is associated with a dedicated processor configured to perform the optimization of the FOUP transport, wherein the dedicated processor comprises at least one quantum computer.

7. The system of claim 1, wherein the processor is further configured to: applying a big data analysis process to analyze said metrology and / or inspection measurements; The dynamic sampling plan is updated based on the analyzed metrology and / or inspection measurements.

8. The system of claim 7, wherein applying the big data analytics process and updating the dynamic sampling plan are associated with a dedicated processor configured to perform the big data analytics, wherein the dedicated processor comprises at least one quantum computer.

9. The system of claim 1, further comprising a system controller configured to receive reports and log files from processing tools and / or control the wafer transport and metrology measurement optimization in the fabrication facility.

10. The system of claim 9, wherein the system controller comprises at least one of: a centralized quantum computer, a network of quantum computers, a co-optimized quantum and classical computer network, and / or a network service comprising any of the same.

11. A system for optimizing wafer transport and metrology measurements in a semiconductor manufacturing fab, the system comprising: At least one processor configured to: deriving and updating a dynamic sampling plan that provides wafer specific measurement locations and conditions, wherein the dynamic sampling plan differs between wafers, and managing the transportation of a front opening pod (FOUP) by the manufacturing plant so as to transport wafers to a measurement tool, and providing the dynamic sampling plan to the corresponding measurement tool before or when the FOUP and the corresponding wafers are transported to the corresponding measurement tool, wherein the measurement tool is a metrology tool or an inspection tool, Wherein the respective metrology tool is configured to perform metrology and / or inspection measurements of the respective wafer according to the provided dynamic sampling plan, and wherein the processor comprises at least one quantum computer.

12. The system of claim 11, wherein deriving and updating the dynamic sampling plan is associated with a special-purpose processor configured to perform the optimization of the dynamic sampling plan, wherein the special-purpose processor comprises at least one quantum computer.

13. The system of claim 11, wherein the processor is further configured to computationally support the respective metrology tool in deriving an optimized wafer measurement path of metrology measurements by the respective metrology tool from the derived and updated respective dynamic sampling plan.

14. The system according to claim 11, wherein the measuring tools include at least one step-by-step metrology tool and at least one scanning metrology tool, The processor is further configured to co-optimize the dynamic sampling plan and the wafer measurement path with respect to allocation of stepping and scanning metrology tools so that the dynamic sampling plan and the wafer measurement path have a minimum wafer measurement time, Wherein the scanning metrology tool is assigned to measure the extension of adjacent wafer sites.

15. The system of claim 11, wherein managing the FOUP transport is associated with a dedicated processor configured to perform the optimization of the FOUP transport, wherein the dedicated processor comprises at least one quantum computer.

16. The system of claim 11, wherein the processor is further configured to: apply a big data analysis process to analyze the metrology and / or inspection measurements; and update the dynamic sampling plan based on the analyzed metrology and / or inspection measurements.

17. The system of claim 16, wherein applying the big data analytics process and updating the dynamic sampling plan are associated with a dedicated processor configured to perform the big data analytics.

18. The system of claim 11, further comprising a system controller configured to receive reports and log files from processing tools and / or control the wafer transport and metrology measurement optimization in the fabrication facility.

19. The system of claim 18, wherein the system controller comprises at least one of: a centralized quantum computer, a network of quantum computers, a co-optimized quantum and classical computer network, and / or a network service comprising any of the same.

20. A system for optimizing wafer transport and metrology measurements in a semiconductor manufacturing fab, the system comprising: At least one processor configured to: deriving an optimized wafer measurement path for metrology measurements of the wafer based on a dynamic sampling plan that provides wafer specific measurement locations and conditions and that differs between wafers, and A front opening FOUP is transported by the manufacturing plant to transport the wafers to a measurement tool, and the derived wafer measurement path is provided to the corresponding measurement tool before or when the FOUP and the corresponding wafers are transported to the corresponding measurement tool, wherein the measurement tool is a metrology tool or an inspection tool, Wherein the respective measurement tool is configured to perform metrology and / or inspection measurements of the respective wafer according to the derived wafer measurement path, and wherein the processor comprises at least one quantum computer.

21. The system of claim 20, wherein deriving the optimized wafer measurement path is associated with a dedicated processor configured to perform the optimization of the wafer measurement path, wherein the dedicated processor comprises at least one quantum computer.

22. The system of claim 21, wherein deriving the optimized wafer measurement path is associated with optimizing the wafer measurement path with respect to wafer measurement speed and according to a given measurement time specified by the dynamic sampling plan.

23. The system of claim 21, wherein deriving the optimized wafer measurement path is associated with optimizing the wafer measurement path by implementing at least one traveling salesman problem (TSP) algorithm.

24. The system of claim 23, wherein the special purpose processor comprises at least one quantum computer, and wherein the at least one traveling salesman problem (TSP) algorithm is adapted to be processed by the at least one quantum computer.

25. The system according to claim 20, wherein the measuring tools include at least one step-by-step metrology tool and at least one scanning metrology tool, The processor is further configured to co-optimize the dynamic sampling plan and the wafer measurement path with respect to allocation of stepping and scanning metrology tools so that the dynamic sampling plan and the wafer measurement path have a minimum wafer measurement time, Wherein the scanning metrology tool is assigned to measure the extension of adjacent wafer sites.

26. The system of claim 20, wherein managing the FOUP transport is associated with a dedicated processor configured to perform the optimization of the FOUP transport, wherein the dedicated processor comprises at least one quantum computer.

27. The system of claim 20, wherein the processor is further configured to apply a big data analytics process to analyze the metrology and / or inspection measurements.

28. The system of claim 27, wherein applying the big data analytics process is associated with a dedicated processor configured to perform the big data analytics, wherein the dedicated processor comprises at least one quantum computer.

29. The system of claim 20, further comprising a system controller configured to receive reports and log files from processing tools and / or control the wafer transport and metrology measurement optimization in the fabrication facility.

30. The system of claim 29, wherein the system controller comprises at least one of: a centralized quantum computer, a network of quantum computers, a co-optimized quantum and classical computer network, and / or a network service comprising any of the same.

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