Optimized retrograde channel implantation for planar SiC MOSFETs

Abstract

Disclosed is a silicon carbide (SiC) planar transistor device, comprising: a first charge type SiC semiconductor substrate having a top surface and a bottom surface; a first charge type SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface; a first charge type source structure formed in the top surface of the SiC epitaxial layer, the source structure having a top surface; a first charge type drain structure formed on the bottom surface of the SiC semiconductor substrate; a gate structure comprising a gate oxide and a gate flow channel, wherein the gate oxide covers at least a portion of the source structure and the gate flow channel; a second charge type channel region located below the gate structure in a vertical direction and adjacent to the source structure, wherein a second charge type doping profile of the channel region comprises a first region and a second region, wherein the first region has a doping profile at 2*e 17 cm ‑3 To 3*e 18 cm ‑3 The first region is located vertically below the gate oxide and has a depth between 50 nm and 250 nm from the top surface of the SiC epitaxial layer, and the second region has a Pearson IV type distribution doping concentration with a peak doping concentration of 1.5*e 18 cm ‑3 To 8*e 18 cm ‑3 The second region is located below and adjacent to the first region in a vertical direction, wherein the peak position of the Pearson IV type distribution is within a range of 300 nm to 500 nm from the top surface of the SiC epitaxial layer.

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide (SiC) planar transistor device, and more particularly to an optimized retrograde channel implantation for a silicon carbide (SiC) planar transistor device. Background Art

[0002] This section provides background information related to the present disclosure which is not necessarily prior art.

[0003] US 9,922,977 B2 discloses a structure involving a deeply depleted channel (DDC) design and a method of fabricating the same, which allows CMOS-based devices to have reduced o·V compared to conventional bulk CMOS. T (In V T ) and can allow the threshold voltage V of a FET having a dopant in the channel region to be T The dopant profile indicating the unique groove enables tuning V within a precise range. T This V can be extended by properly selecting the metal of the gate electrode material. T setting range, so that a very wide V T The DDC design also has a strong body effect compared to conventional bulk CMOS transistors, which can allow significant dynamic control of the power dissipation in the DDC transistors. The result is independent control of V T (with lower o·V T ) and VDD (the operating voltage supplied to the transistor) so that for a given device, the body bias can be related to V T Tuning is performed separately.

[0004] US6255174 B1 discloses an improved semiconductor device (such as a MOSFET with delayed threshold voltage roll-off and short channel effect), so that the semiconductor device is more tolerant to gate variations of short gate length devices. The semiconductor device includes an asymmetric channel doping profile. A first pocket dopant implant with a 0° tilt is used to produce a first source dopant pocket and a drain dopant pocket. A second pocket dopant implant with a 30° to 60° tilt produces a second source dopant pocket without producing an additional drain dopant pocket, thereby producing an asymmetric doping profile.

[0005] JP 2009 054765 relates to a semiconductor with a channel region, which has a region with a high impurity concentration and a region with a low impurity concentration, and is formed in a self-matching manner by an implantation mask of two types of second conductive impurities different in diffusion coefficient, ion implantation of an extension of the implantation mask, ion implantation of a first conductive impurity, and diffusion of a second conductive impurity having a large diffusion coefficient due to activation annealing.

[0006] Wilson RG: "The pearson IV distribution and its application to ion implanted depth profiles", RADIATION EFFECTS, GORDON AND BREACH SCIENCE PUBLISHERSO NEW YORK NY, US, Vol. 46, January 1980, pp. 141-147, XP002969980, ISSN: 0033-7579, DOI: I 0.1080 / 00337578008209163 discusses the Pearson IV distribution system and its applicability to ion implantation profiles.

[0007] US 2012 / 097980A1 relates to a terminal configuration of a silicon carbide insulated gate semiconductor device, which comprises a semiconductor layer of a first conductivity type having a first main surface, a gate electrode and a source interconnection, and a circumferential reduced surface electric field region. The semiconductor layer comprises a body region of a second conductivity type, a source region of the first conductivity type, a contact region of the second conductivity type, and a circumferential reduced surface electric field region of the second conductivity type.

[0008] The object of the present invention is to improve the threshold V with respect to process variations. TH and channel length L CH control and pin the peak electric field away from the gate oxide / SiC interface to increase device reliability. Summary of the invention

[0009] This section provides a general summary of the disclosure, and is not a comprehensive disclosure of its full scope or all of its features.

[0010] The subject disclosure provides a silicon carbide (SiC) planar transistor device, the silicon carbide planar transistor device comprising: a first charge type SiC semiconductor substrate having a top surface and a bottom surface; a first charge type SiC epitaxial layer formed on the top surface of the SiC semiconductor substrate, the SiC epitaxial layer having a top surface; a first charge type source structure formed in the top surface of the SiC epitaxial layer, the source structure having a top surface; a first charge type drain structure formed on the bottom surface of the SiC semiconductor substrate; a gate structure comprising a gate oxide and a gate runner, wherein the gate oxide covers at least a portion of the source structure and the gate runner, and a second charge type channel region located vertically below the gate structure and adjacent to the source structure, wherein a doping profile of the second charge type of the channel region comprises a first region and a second region, wherein the first region has a doping profile of 2*e 17 cm -3 To 3*e 18 cm -3 The first region is located vertically below the gate oxide and has a depth between 50 nm and 250 nm from the top surface of the SiC epitaxial layer, and the second region has a Pearson type IV profile doping concentration with a peak doping concentration of 1.5*e 18 cm -3 To 8*e 18 cm -3 The second region is located vertically below and adjacent to the first region, wherein the peak position of the Pearson IV type distribution is within the range of 300nm to 500nm from the top surface of the SiC epilayer. Pearson type IV is widely used to fit observed distributions obtained from data or Monte Carlo simulations. The channel length (L Ch ) is in the range of 50nm to 250nm.

[0011] The subject disclosure also provides a silicon carbide (SiC) planar transistor device, wherein the planar transistor is one of a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).

[0012] According to another aspect of the subject disclosure, in a silicon carbide (SiC) planar transistor device, a threshold voltage (V th ) is in the range of 2V to 3.5V.

[0013] Further areas of applicability will become apparent from the description provided herein.The description and specific examples in this summary are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present disclosure.

[0015] Figure 1 An example of a cross section of a planar MOSFET structure is shown.

[0016] Figure 2 The channel doping contour of a MOSFET structure is shown.

[0017] Figure 3 A channel doping profile is shown according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] Examples of embodiments will now be described more fully with reference to the accompanying drawings.

[0019] Example embodiments are provided so that the present disclosure will be thorough and the concept will be fully conveyed to those skilled in the art. Many specific details (such as examples of specific components, devices and methods) are set forth to provide a thorough understanding of the embodiments of the present disclosure. It will be apparent to those skilled in the art that specific details do not need to be adopted, and the example embodiments can be implemented in many different forms, and none of them should be construed as limiting the scope of the present disclosure. In some example embodiments, well-known processes, well-known device structures and well-known technologies are not described in detail.

[0020] The terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. As used herein, the singular forms "a", "an", and "the" may also be intended to include the plural forms unless the context clearly indicates otherwise. The terms "comprises, comprising", "including", and "having" are inclusive and thus specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein should not be construed as necessarily requiring them to be performed in the particular order discussed or shown, unless specifically identified as an order of execution.

[0021] It is also to be understood that additional or alternative steps may be employed.

[0022] When an element or layer is referred to as being "on another element or layer," "engaged to," "connected to," or "coupled to" another element or layer, it may be directly on, engaged to, connected to, or coupled to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on," "directly engaged to," "directly connected to," or "directly coupled to" another element or layer, there may be no intermediate elements or layers. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.). As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0023] Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or sections in this article, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms may only be used to distinguish an element, component, region, layer or section from another region, layer or section. When terms (such as "first", "second" and other numerical terms) are used in this article, order or sequence is not implied unless the context clearly indicates. Therefore, without departing from the teaching of the exemplary embodiment, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section.

[0024] For ease of description, spatially relative terms may be used herein, such as "inside", "outside", "below", "below", "lower", "above", "upper", etc. to facilitate description of the relationship between an element or feature and another (multiple) element or (multiple) feature as shown in the figure. In addition to the orientation depicted in the accompanying drawings, spatially relative terms may be intended to include different orientations of the device in use or operation. For example, if the device in the figure is turned over, the element described as "below" or "below" other elements or features will be oriented "above" the other elements or features. Therefore, the example term "below" can include both the orientation above and below. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein are interpreted accordingly.

[0025] Embodiments relate to MOS-based SiC planar devices, such as Figure 1 The metal oxide semiconductor field effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT) shown in FIG.

[0026] exist Figure 1 , an example of a cross-section of a typical planar SiC MOSFET structure is shown. Figure 1The silicon carbide (SiC) planar transistor device in the present invention includes a SiC semiconductor substrate 1 of a first charge type (e.g., p-type) having a top surface and a bottom surface. A SiC epitaxial layer 2 of the first charge type is formed on the top surface of the SiC semiconductor substrate 1, and the SiC epitaxial layer 2 has a top surface. A source structure 3 of the first charge type is formed in the top surface of the SiC epitaxial layer 2, and the source structure 3 has a top surface. A drain structure 4 of the first charge type is formed on the bottom surface of the SiC semiconductor substrate 1, and a gate structure 6, 7 includes a gate oxide 7 and a gate runner 6, wherein the gate oxide 7 covers at least a portion of the source structure 3 and the gate runner 6. A channel region 5 of a second charge type (e.g., n-type) is located vertically below the gate structures 6, 7 and adjacent to the source structure 3.

[0027] An example of a channel profile used in a planar MOSFET device is shown in Figure 2 Shown in.

[0028] Despite having Figure 2 The device with the channel outline shown in FIG. 1 is functional, but may suffer from the following defects:

[0029] Even when implanted through the nominal oxide thickness, the variation in doping concentration in the first 200nm is considerable. Depending on the amount of SiC removed by the oxidation process, V TH The shift may be significant. For example, removing 10 nm of SiC results in a 13% reduction in the surface channel concentration.

[0030] The thickness of the screen oxide significantly affects the surface channel concentration and thus V TH If 20nm of SiC is removed by thermal oxide growth, the channel profile is very similar. However, in the case of the deposited gate oxide, the surface concentration drops significantly, and thus V TH In the case of deposited oxides this can be compensated by adjusting the dose, but any very small change in the consumed SiC leads to a large change in the surface concentration.

[0031] The channel length L in a planar device Ch Theoretically determined by the gate spacer, but due to scattering during implantation, different channel profiles lead to different lateral shapes, which may also affect L CH For example, the channel length of a planar MOSFET device with channel doping increases as more SiC thickness is consumed during gate oxidation.

[0032] In order to overcome the above-mentioned deficiencies and provide improved planar SiC devices, tailored doping profiles in both vertical and horizontal directions have been designed for the channel region of planar SiC devices through mathematical optimization. Figure 3 Several implant combinations are shown (in the form of dashed lines), where the doses are selected by a mathematical optimization procedure, resulting in a new design curve (in the form of a solid line). The proposed profile is flat not only in the vertical direction, but also in the lateral direction, ensuring that L CH Stable against process variations. It is evident from Figure 6 that this new designed profile has negligible dopant concentration variation in the first 200nm.

[0033] The profile includes a 2e 17 and 3e 18 cm -3 constant doping between (which depends on the threshold V TH , oxide capacitance and interface defect concentration are chosen to allow a maximum variation of 8-10% from a constant value). Examples of dopants are Al, N, B, P.

[0034] The peak portion of the profile can be obtained using one or more injections to achieve Figure 3 The peak position between 300nm and 500nm in section II and at 1.5e 18 and 8e 18 cm -3 The peak concentration between

[0035] The silicon carbide (SiC) planar transistor device improved by the customized channel profile mentioned above thus comprises: a SiC semiconductor substrate of a first charge type having a top surface and a bottom surface; a SiC epitaxial layer of a first charge type formed on the top surface of the SiC semiconductor substrate; a SiC epitaxial layer having a top surface; a source structure of a first charge type formed in the top surface of the SiC epitaxial layer, the source structure having a top surface; a drain structure of a first charge type formed on the bottom surface of the SiC semiconductor substrate; a gate structure comprising a gate oxide and a gate runner, wherein the gate oxide covers at least a portion of the source structure and the gate runner; a channel region of a second charge type located vertically below the gate structure and adjacent to the source structure, wherein a doping profile of the second charge type of the channel region comprises a first region and a second region, wherein the first region has a doping profile of 2*e 17 cm -3 To 3*e 18 cm -3The first region is located vertically below the gate oxide and has a depth between 50 nm and 250 nm from the top surface of the SiC epitaxial layer, and the second region has a Pearson IV type distribution doping concentration with a peak doping concentration of 1.5*e 18 cm -3 To 8*e 18 cm -3 In one embodiment, the flat first region is located vertically below the gate oxide and has a depth between 75 nm and 150 nm. In another embodiment, the oxide capacitance and the interface defect concentration are allowed to have a maximum variation of 2%-5% from a constant value.

[0036] Improved channel profile ensures constant L CH Furthermore, the optimized channel profile of the planar SiC device enables accurate and robust control of the threshold voltage V with respect to process variations (i.e., variations and non-uniformities in the thickness of the implanted screen oxide or variations in the thickness of the SiC consumed during gate formation, depending on, for example, oxidation conditions, etc.). TH and channel length L CH , and pins the peak electric field away from the gate oxide / SiC interface to increase device reliability.

[0037] Furthermore, the improved channel profile ensures that V TH and L CH These values ​​are independent of the process variability (the thickness of the shield oxide and the consumed SiC are not uniform over the wafer surface). TH and L CH A constant value of achieves smaller variations in device characteristics and better yield.

[0038] The foregoing description of the embodiments has been provided for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable where applicable and may be used in selected embodiments, even if not specifically shown or described. The same may also differ in many ways. Such variations should not be considered as departures from the present disclosure, and all such modifications are intended to be included within the scope of the present disclosure.

Claims

1. A silicon carbide (SiC) planar transistor device, comprising: a SiC semiconductor substrate (1) of a first charge type having a top surface and a bottom surface, A SiC epitaxial layer (2) of a first charge type is formed on the top surface of the SiC semiconductor substrate (1), the SiC epitaxial layer (2) having a top surface, a source structure (3) of a first charge type formed in the top surface of the SiC epitaxial layer (2), the source structure (3) having a top surface, a drain structure (4) of a first charge type formed on the bottom surface of the SiC semiconductor substrate (1), A gate structure (6, 7) comprising a gate oxide (7) and a gate flow channel (6), wherein the gate oxide (7) covers at least a portion of the source structure (3) and the gate flow channel (6), a channel region (5) of a second charge type located below the gate structure (6, 7) in the vertical direction and adjacent to the source structure (3), Characterized in that the doping profile of the second charge type of the channel region (5) comprises a first region (I) and a second region (II), wherein The first region (I) has a 17 cm -3 To 3*e 18 cm -3 The first region has a constant doping concentration within a range of , and the first region is located vertically below the gate oxide (7) and has a depth between 50nm and 250nm from the top surface of the SiC epitaxial layer (2), The second region (II) has a Pearson IV type distribution doping concentration, wherein the peak doping concentration is at 1.5*e 18 cm -3 To 8*e 18 cm -3 and the second region is located below the first region (I) in the vertical direction and adjacent to the first region, wherein the peak position of the Pearson IV type distribution is within a range of 300 nm to 500 nm from the top surface of the SiC epitaxial layer (2), and The channel length (L Ch ) is in the range of 50nm to 250nm. 2 . The silicon carbide (SiC) planar transistor device of claim 1 , wherein the planar transistor is one of a metal oxide semiconductor field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).

3. The silicon carbide (SiC) planar transistor device according to any one of claims 1 to 2, wherein the threshold voltage (V th ) in the range of 2V to 3.5V.

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