A hierarchical word line preprocessing circuit for flash FPGA
By designing a hierarchical word line preprocessing circuit in a flash FPGA, and managing word line signals using layer control circuits and decoding circuits, the problem of providing appropriate gate voltage for the memory cells is solved, and efficient memory cell operation and fast integration are achieved.
Patent Information
- Application Number
- CN202111469888.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-03
- Publication Date
- 2025-04-15
- Estimated Expiration
- 2041-12-03
AI Technical Summary
In flash FPGAs, how to efficiently provide the gate voltage required for memory cells during erasing, programming and reading has become a key issue in achieving rapid integration.
A hierarchical word line preprocessing circuit is designed, including a layer control circuit and a decoding circuit. Each decoding unit forms a word line gate signal based on the read and write signals, erase signals and the path selection signals output by the control units at different levels, for pull-up or pull-down word line control signals, and provide appropriate gate voltage.
The decoding circuit is simplified through hierarchical management, reducing hardware logic resource overhead, reducing interference between different block control units, and achieving efficient operation of memory cell arrays, which is especially suitable for the rapid integration of large-scale flash-type programmable devices.
Smart Images
Figure CN114171090B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of FPGA, in particular to a hierarchical word line preprocessing circuit of a flash type FPGA. Background Art
[0002] Flash FPGA is based on reconfigurable flash storage technology. By reprogramming the flash storage unit, the logical relationship inside the circuit is changed, thereby realizing different logical functions for users. Since the flash storage unit is a non-volatile storage, the information will not be lost after the chip is powered off and restarted, so it has become the mainstream of programmable logic devices and is widely used in signal processing and control fields. The configuration of the storage unit (flash cell) in the flash FPGA is the premise of the logic application of programmable logic devices. The word line (WL) is connected to the gate of the flash cell, and it needs to be given the corresponding voltage during the erasing, programming, and reading of the flash cell. How to prepare to realize this function efficiently plays a key role in the rapid integration of flash FPGA. Summary of the invention
[0003] In view of the above problems and technical requirements, the inventors have proposed a hierarchical word line preprocessing circuit for a flash type FPGA. The technical solution of the present invention is as follows:
[0004] A hierarchical word line preprocessing circuit for a flash type FPGA, the hierarchical word line preprocessing circuit comprising layer control circuit and a decoding circuit, ;
[0005] The first layer of control circuit includes a plurality of first control units, Each layer in the control circuit The control unit corresponds to Several first-level control circuits Control unit, is a parameter and , No. Each layer in the control circuit The control unit corresponds to a decoding unit in the decoding circuit; each decoding unit leads out a word line control signal and connects to a word line in the FPGA;
[0006] Each decoding unit is controlled by the read / write signal, the erase signal and the corresponding The control units at different levels output The decoding unit is used to pull up the word line control signal to a variable positive voltage according to the acquired signal, and provide the gate voltage required for performing read and write operations for the connected word line controlled storage unit, and to pull down the word line control signal to a negative voltage according to the acquired signal, and provide the gate voltage required for performing erase operations for the connected word line controlled storage unit.
[0007] The beneficial technical effects of the present invention are:
[0008] The present application discloses a hierarchical word line preprocessing circuit for a flash type FPGA, which provides word line signals for the storage cell array when erasing, programming and reading the storage cells in the flash type FPGA through a hierarchical management method, simplifies the decoding circuit, reduces the resource overhead of the hardware logic, and can reduce the interference between different block control units when operating the storage cells. At the same time, the address of the flash type FPGA when operating the storage cell array is continuous, and the address counter automatically adds 1. After each group control unit completes the read and write operation, it feeds back a completion signal to the upper level until all group control units complete the read and write operation. This bottom-up signal feedback flexibly realizes the selection of the flash cell array block (corresponding to a block control unit Bank), which plays a key role in the rapid integration of large-scale flash type programmable devices. BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Figure 1 The figure is a schematic diagram of the corresponding relationship between control circuits at different levels when three layers of control circuits are formed and there are 9216 word lines in total.
[0010] Figure 2 It is a schematic diagram of the circuit structure of a block control unit and its corresponding group control unit in an embodiment.
[0011] Figure 3 The present invention is a schematic diagram of the circuit structure of each address latch unit corresponding to a group control unit and its corresponding block control unit, group control unit and decoding unit in an embodiment. DETAILED DESCRIPTION
[0012] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.
[0013] The present application discloses a hierarchical word line preprocessing circuit for a flash type FPGA. The flash type FPGA includes a plurality of memory cells (flash cells) forming a row-column structure. Each word line WL controls the gates of a plurality of memory cells. Specifically, the gates of a plurality of memory cells in the same row are generally connected. Each group of bit lines BL / BLN controls the drain and source of a plurality of memory cells. Generally, the drain and source of a plurality of memory cells in the same column are connected. The word lines and bit lines cooperate to realize the read, write and erase operations of the memory cell array. In this process, the word lines need to provide the required gate voltage to the memory cells, and the hierarchical word line preprocessing circuit of the present application is used to realize this function.
[0014] The word line preprocessing circuit includes layer control circuit and a decoding circuit, The first layer of control circuit includes a plurality of first control units, Each layer in the control circuit The control unit corresponds to Several first-level control circuits Control unit, is a parameter and . No. Each layer in the control circuit The control unit corresponds to a decoding unit in the decoding circuit. Each decoding unit leads out a word line control signal and connects to a word line in the FPGA.
[0015] Among them, the control units of the next level corresponding to any two control units at the same level do not overlap, and the control units of the next level corresponding to all control units at the same level cover all control units of the next level. The number of control units at each level is determined according to the number of word lines actually included in the flash FPGA, or sometimes the layout structure of the storage unit and the word line needs to be considered.
[0016] Optionally, the number of control units at the next level corresponding to any two control units at the same level is the same or different. For example, a first control unit corresponds to 12 second control units, and another first control unit may also correspond to 12 second control units, then the two first control units correspond to the same number of second control units. Alternatively, another first control unit corresponds to 16 second control units, then the two first control units correspond to different numbers of second control units. However, in general, a regular structure is adopted in which any two control units correspond to the same number of control units at the next level.
[0017] In one embodiment, , the hierarchical word line preprocessing circuit includes three layers of control circuits. The first layer of control circuits includes several block control units (Bank) as the first control unit, the second layer of control circuits includes several group control units (Group) as the second control unit, and the third layer of control circuits includes several address latch units (Latch) as the third control unit. This is a commonly used architecture in practice.
[0018] Based on this architecture, assuming that the flash FPGA includes a total of 9216 word lines, a specific implementation of the hierarchical word line preprocessing circuit is as follows: Figure 1 Schematic diagram: The first-layer control circuit includes 16 block control units, which are respectively recorded as Bank 0 to Bank 15. The block control unit Bank 0 corresponds to the 12 group control units of the second-layer control circuit, which are respectively recorded as Group0 to Group11. The group control unit Group0 corresponds to the 48 address latch units of the third-layer control circuit, which are respectively recorded as Latch0 to Latch47. The address latch units Latch0 to Latch47 correspond to a decoding unit, which are respectively recorded as Decode0 to Decode47. Each decoding unit leads to a word line control signal and connects to a word line in the FPGA, which is respectively recorded as WL <0> ~WL <47> The remaining block control units, group control units and address latch units are similar.
[0019] It can be seen that based on the structure of the present application, each decoding unit corresponds to Different levels of A control unit, that is, including the first The control unit and other levels have corresponding control units respectively. Specifically, the decoding unit corresponds to the first Control unit, its corresponding The control unit corresponds to the previous layer Control unit..., and so on until the first control unit. Each decoding unit will obtain its corresponding The control units at different levels output The word line selection signal is recorded as the word line selection signal. When each decoding unit obtains a word line selection signal formed by three selection signals outputted by its corresponding address latch unit, group control unit, and block control unit respectively.
[0020] Each decoding unit is controlled by the read / write signal PG_RD_b, the erase signal ERASE, and the received word line selection signal, and pulls up the word line control signal to the variable positive voltage VPC according to the three types of signals obtained, and provides the gate voltage required for the connected word line controlled storage unit to perform the read / write operation. In addition, the decoding unit is also used to pull down the word line control signal to the negative voltage VGC according to the three types of signals obtained, and provide the gate voltage required for the connected word line controlled storage unit to perform the erase operation.
[0021] Optionally, the read and write operations performed on the memory cell controlled by the word line include programming operations and reading operations, then: the decoding unit pulls up the derived word line control signal to a variable positive voltage whose voltage value is the programming voltage value, so as to provide the gate voltage required for the memory cell controlled by the connected word line to perform the programming operation. Alternatively, the decoding unit pulls up the derived word line control signal to a variable positive voltage whose voltage value is the reading voltage value, so as to provide the gate voltage required for the memory cell controlled by the connected word line to perform the reading operation. Among them, the programming voltage value is greater than the reading voltage value, and generally the reading voltage value is equal to the core voltage value, which is 1.5V, while the programming voltage is a high voltage, such as 12.5V, and the negative voltage VGC can be, for example, -16.5V.
[0022] During the memory cell erasing process, all decoding units obtain the read / write signal PG_RD_b of the invalid level and the erase signal ERASE of the valid level. All decoding units obtain the word line selection signal for indicating the selection of the connected word line and pull the derived word line control signal down to the negative voltage VGC, so as to simultaneously provide the gate voltage required to perform the erase operation to the memory cells controlled by each word line, so that all the memory cells of the whole chip are erased together.
[0023] During the reading and writing process of the storage unit, all decoding units obtain the read and write signal PG_RD_b of the valid level and the erase signal ERASE of the invalid level, and each decoding unit obtains the word line selection signal for indicating the selection of the connected word line in turn and pulls up the derived word line control signal to a variable positive voltage, so as to provide the gate voltage required to perform the read and write operations to the storage cells controlled by each word line in turn, so that all the storage cells of the whole chip are read and written in turn according to the word line selection signal of the connected word line.
[0024] In the above process, when each decoding unit obtains the output of each corresponding control unit, When a valid selection signal is received, it is confirmed that a word line selection signal for indicating the selection of the connected word line is received, that is, it is confirmed that a valid word line selection signal is received. When the word line selection signal obtained by each decoding unit for indicating the selection of the connected word line includes three effective selection signals output by the corresponding address latch unit, group control unit, and block control unit respectively. Taking a typical embodiment of the hierarchical word line preprocessing circuit as an example, each block control unit in the hierarchical word line preprocessing circuit sequentially outputs a valid selection signal; and when a block control unit outputs a valid selection signal, it controls its corresponding group control units to sequentially output a valid selection signal; and when a group control unit outputs a valid selection signal, it controls its corresponding address latch units to sequentially output a valid selection signal, so that each decoding unit sequentially obtains a word line selection signal for indicating the selection of the connected word line.
[0025] Please refer to Figure 2 and Figure 3 In the specific circuit diagram shown, each group control unit is implemented based on a D flip-flop. The D flip-flops in the group control units Group0~Group11 are respectively recorded as DFF0~DFF11. The Q end of each D flip-flop in each group control unit corresponding to the same block control unit is connected to the D end of the next level D flip-flop to form a cascade structure. The D end of the first level D flip-flop is connected to the shift enable signal shift_EN, and the Q end of each level of D flip-flop also outputs the selection signal of the group control unit to which it belongs. During the reading and writing process of the storage unit, the shift enable signal shift_EN is at a high level, and the CP end of each D flip-flop is connected to the sampling clock CP. After the sampling clock CP becomes high, the output end Q end of the D flip-flop is high, and then a valid selection signal is output. Specifically, the Q end of each level of D flip-flop sequentially outputs the selection signal of the group control unit to which it belongs through a buffer powered by the configuration voltage VCC and the ground end and a buffer powered by the variable positive voltage VPC and the negative voltage VGC. Optionally, one selection signal output by each control unit of each layer of control circuit includes a first signal and a second signal with opposite phases, so each valid selection signal actually includes a first signal and a second signal with valid levels. For example Figure 2 As shown, the selection signal output by a group control unit Group0 includes a first signal Group <0> and its inverted second signal Group_b <0> , the first signal is valid at a high level and the second signal is valid at a low level, then the valid selection signal output by Group0 includes the first signal at a high level and the second signal at a low level, and the same applies to other group control units.
[0026] Each group control unit also includes a pull-down NMOS tube, and the pull-down NMOS tubes in the group control units Group0~Group11 are respectively recorded as G_N0~G_N11. The source of the pull-down NMOS tube is grounded, and the gate is connected to the Q end of the D flip-flop in the group control unit. The drains of the pull-down NMOS tubes in each group control unit corresponding to the same block control unit are connected and connected to the feedback end of the block control unit. When any group control unit outputs a valid selection signal, that is, when the Q end of the D flip-flop in any group control unit is high, the pull-down NMOS tube is pulled down to the ground, and the block control unit receives a feedback signal Fb of a valid level through the feedback end, that is, receives a low level. When the block control unit receives a valid block selection signal WL_SEL and receives a feedback signal Fb of a valid level through the feedback end, the block control unit outputs a valid selection signal.
[0027] Please refer to Figure 2 Each block control unit includes a PMOS inverse ratio tube P0 and NMOS tubes N0, N1 and N2. The source of P0 is connected to the core voltage, the drain is connected to the drain of N0, the source of N0 is grounded, the gate of P0 is connected to the gate of N0 and connected to the low-level effective configuration enable signal CFG_B, and the common end of P0 and N0 is connected to the output selection signal through an inverter and a buffer in turn. The inverter is powered by the configuration voltage VCC and the ground terminal, and the buffer is powered by the variable positive voltage VPC and the ground terminal. The configuration voltage VCC is 3.3V. The common end of P0 and N0 is also connected to the drain of N2, the source of N2 is connected to the drain of N1, and the source of N1 is grounded. The block selection signal WL_SEL is connected to the gate of N2. The block selection signal WL_SEL is also connected to the gate of N1 through an inverter powered by the core voltage VDD and the ground terminal. The common end of N1 and N2 is used as the feedback end of the block control unit to obtain the feedback signal Fb. When the block control unit obtains a high-level valid block selection signal WL_SEL and simultaneously receives a low-level valid feedback signal Fb, it outputs a valid selection signal. Similarly, the selection signal output by the block control unit also includes a first signal and a second signal with opposite phases. Figure 2 As shown, the selection signal output by a block control unit Bank0 includes a first signal Bank <0> and its inverted second signal Bank_b <0> , the first signal is valid at a high level and the second signal is valid at a low level, then the valid selection signal output by Bank0 includes the first signal at a high level and the second signal at a low level, and the same applies to other block control units.
[0028] Each address latch unit is built based on a latch, such as Figure 3As shown in the figure, each address latch unit corresponding to a group control unit Group0 is recorded as Latch0~Latch47, and the D end of each latch obtains the corresponding address signal and is recorded as A <0> ~ A <47> At the same time, the address signal is continuous when the array formed by the storage unit is read and written, and the address counter automatically adds 1. The CP terminal of the latch obtains the sampling clock. After the sampling clock CP becomes high, the address latch unit is turned on, the address signal takes effect, and the latch outputs a high level through the Q terminal and a low level through the QN terminal. Similarly, the selection signal output by the address latch unit also includes a first signal and a second signal with opposite phases. For example Figure 3 As shown, the selection signal output by an address latch unit Latch0 includes a first signal Addr output through the Q terminal of the latch. <0> and the second signal Addr_b outputted through the QN terminal of the latch inversely <0> , the first signal is valid at a high level and the second signal is valid at a low level, then the valid selection signal output by the address latch unit Latch0 includes a high-level first signal and a low-level second signal, and the same applies to other block control units.
[0029] Each decoding unit includes a pull-up component and a pull-down component connected in series. The decoding unit is connected to a variable positive voltage VPC through the pull-up component and to a negative voltage VGC through the pull-down component. The common end of the pull-up component and the pull-down component leads to a word line control signal and is connected to the word line WL. <0> ~ WL <47> The pull-up component of the decoding unit is controlled by the read / write signal PG_RD_b and the corresponding The control units at different levels output The second signal of the pull-down component is controlled by the erase signal ERASE and the corresponding decoding unit. The control units at different levels output When the decoding unit receives the first signal The first signal of the effective level and When a second signal of a word line effective level is received, it is determined that a word line selection signal for instructing selection of a connected word line is received.
[0030] Specifically, the circuit structure of each decoding unit is the same. Take the decoding unit Decode0 as an example: the pull-up component includes four PMOS tubes, namely W_P0, W_P1, W_P2 and W_P3. The source of W_P3 is connected to the variable positive voltage VPC, and the drain is connected to the source of W_P2. The drain of W_P2 is connected to the source of W_P1, and the drain of W_P1 is connected to the source of W_P0. The drain of W_P0 is used to connect the pull-down component and lead out the word line control signal. The gate of W_P3 is controlled by the low-level effective read and write signal PG_RD_b. The gate of W_P0 is controlled by the second signal Bank_b output by the block control unit corresponding to the decoding unit. <0> The gate of W_P1 is controlled by the second signal Group_b output by the group control unit corresponding to the decoding unit <0> The gate of W_P2 is controlled by the second signal Addr_b output by the address latch unit corresponding to the decoding unit. <0> , the three second signals are all valid at low level.
[0031] The pull-down component includes four NMOS tubes, namely W_N0, W_N1, W_N2 and W_N3. The source of W_N0 is connected to the negative voltage VGC, the drain is connected to the source of W_N1, the drain of W_N1 is connected to the source of W_N2, the drain of W_N2 is connected to the source of W_N3, the drain of W_N3 is used to connect the pull-up component and lead out the word line control signal, and the gate of W_N0 is controlled by the high-level effective erase signal ERASE. The gate of W_N3 is controlled by the first signal Bank output by the block control unit corresponding to the decoding unit <0> The gate of W_N2 is controlled by the first signal Group output by the group control unit corresponding to the decoding unit <0> The gate of W_N1 is controlled by the first signal Addr output by the address latch unit corresponding to the decoding unit. <0> , the three first signals are all valid at high level.
[0032] When the decoding unit receives three high-level first signals and three low-level second signals, it determines that a word line selection signal for indicating selection of the connected word line is received.
[0033] based on Figure 2 and Figure 3 The circuit shown in the figure, the working process of the hierarchical word line preprocessing circuit is:
[0034] During the memory cell erasing process, all decoding units obtain the invalid high-level read / write signal PG_RD_b and the valid high-level erase signal ERASE, so that W_P3 is turned off and W_N0 is turned on. All block control units output the high-level first signal Bank<> and the low-level second signal Bank_b<>, all group control units output the high-level first signal Group<> and the low-level second signal Group_b<>, all address latch units output the high-level first signal Addr<> and the low-level second signal Addr_b<>, and all decoding units receive their corresponding word line selection signals for indicating the selection of the connected word lines. In each decoding unit, the PMOS tube W_P3 is turned off, the PMOS tubes W_P0, W_P1 and W_P2 are turned on, and the NMOS tubes W_N0, W_N1, W_N2 and W_N3 are all turned on. The decoding unit pulls down the derived word line control signal to the negative voltage VGC, and at the same time provides the gate voltage required to perform the erase operation to the storage cells controlled by each word line, so that all the storage cells of the entire chip are erased together.
[0035] In the process of reading and writing storage cells, the reading and writing process is similar, except that the voltage value of VPC is different, so only the programming process of storage cells is taken as an example. All decoding units obtain the effective low-level read and write signal PG_RD_b and the invalid low-level erase signal ERASE, making W_P3 turned on and W_N0 turned off. The D end of DFF0 is high level, and after the CP end becomes high level, the Q end of DFF0 is high level, making Group <0> is high level, Group_b <0> When WL_SEL is high, Bank0 is selected. Combined with the low level of N1 drain, Bank0 is selected. <0> High level, Bank_b <0> After Group0 is selected, Latch0 is turned on and address A <0> Effective,Addr <0> High level, Addr_b <0> At this time, in the Decode0 circuit, PMOS tubes W_P0, W_P1, W_P2 and W_P3 are all turned on, NMOS tube W_N0 is turned off, NMOS tubes W_N1, W_N2, and W_N3 are turned on, and Decode0 pulls up the derived word line control signal to a variable positive voltage, so that the word line WL <0> The controlled memory cell provides the gate voltage required to perform read and write operations. Then Latch1 is turned on, and address A <1> The word line control signal is pulled up to a variable positive voltage by Decode1, similar to the above, so that the word line WL <1> The controlled storage unit provides the gate voltage required to perform read and write operations. According to the above process, Latch0~Latch47 are opened in sequence, and address A <0> ~ A <47> It takes effect in sequence. After all address latch units corresponding to Group0 are traversed, Group1 and subsequent groups are selected in sequence and traversed according to the above process, and each group can provide feedback signals to the block control unit of the next level after completing the read and write operations until all groups complete the read and write operations, thus achieving flexibility. In this cyclic process, the gate voltage required to perform the read and write operations is provided to the storage units controlled by each word line in turn, so that all storage units of the entire chip are read and written in sequence according to the word line selection signals of the connected word lines.
[0036] The above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included in the protection scope of the present invention.
Claims
1. A hierarchical word line preprocessing circuit for a flash type FPGA, characterized in that: The hierarchical word line preprocessing circuit includes layer control circuit and a decoding circuit, ; The first layer of control circuit includes a plurality of first control units, Each layer in the control circuit The control unit corresponds to Several first-level control circuits Control unit, is a parameter and , No. Each layer in the control circuit The control unit corresponds to a decoding unit in the decoding circuit; each decoding unit leads out a word line control signal and connects to a word line in the FPGA; Each decoding unit is controlled by a read / write signal, an erase signal, and a corresponding The control units at different levels output The decoding unit is used to pull up the word line control signal to a variable positive voltage according to the acquired signal, and provide the gate voltage required for performing read and write operations for the connected word line controlled storage unit, and to pull down the word line control signal to a negative voltage according to the acquired signal, and provide the gate voltage required for performing erase operations for the connected word line controlled storage unit.
2. The hierarchical word line preprocessing circuit according to claim 1, characterized in that: All decoding units obtain a read / write signal of a valid level and an erase signal of an invalid level, and each decoding unit sequentially obtains a word line selection signal for indicating the selection of the connected word line and pulls up the derived word line control signal to a variable positive voltage, so as to sequentially provide the gate voltage required for performing the read / write operation to the storage unit controlled by each word line; Alternatively, all decoding units obtain read / write signals of invalid levels and erase signals of valid levels, and all decoding units obtain word line selection signals for indicating the selection of the connected word lines and pull down the derived word line control signals to a negative voltage, so as to simultaneously provide the gate voltages required to perform erase operations to the storage cells controlled by each word line.
3. The hierarchical word line preprocessing circuit according to claim 1 or 2, characterized in that: The read and write operations performed on the memory cells controlled by the word lines include programming operations and reading operations. Then: The decoding unit pulls up the derived word line control signal to a variable positive voltage whose voltage value is a programming voltage value, so as to provide a gate voltage required for performing a programming operation for a memory cell controlled by the connected word line; Alternatively, the decoding unit pulls up the derived word line control signal to a variable positive voltage whose voltage value is a read voltage value, so as to provide a gate voltage required for performing a read operation to a memory cell controlled by the connected word line; The programming voltage value is greater than the reading voltage value.
4. The hierarchical word line preprocessing circuit according to claim 2, characterized in that: , the hierarchical word line preprocessing circuit includes three layers of control circuits, the first layer of control circuits includes a plurality of block control units as first control units, the second layer of control circuits includes a plurality of group control units as second control units, and the third layer of control circuits includes a plurality of address latch units as third control units; the word line selection signal obtained by each decoding unit for indicating the selection of the connected word line includes three effective selection signals outputted by the corresponding address latch unit, group control unit, and block control unit respectively; And each block control unit in the hierarchical word line preprocessing circuit sequentially outputs a valid selection signal; When a block control unit outputs a valid selection signal, the corresponding group control units are controlled to output valid selection signals in sequence; and when a group control unit outputs a valid selection signal, the corresponding address latch units are controlled to output valid selection signals in sequence, so that each decoding unit can obtain the word line selection signal used to indicate the selection of the connected word line in sequence.
5. The hierarchical word line preprocessing circuit according to claim 4, characterized in that: Each group control unit is implemented based on a D flip-flop, and the Q end of each D flip-flop in each group control unit corresponding to the same block control unit is connected to the D end of the next-level D flip-flop to form a cascade structure, the D end of the first-level D flip-flop is connected to the shift enable signal, and the Q end of each level of the D flip-flop also outputs the selection signal of the group control unit to which it belongs.
6. The hierarchical word line preprocessing circuit according to claim 5, characterized in that: Each group control unit also includes a pull-down NMOS tube, the source of which is grounded and the gate is connected to the Q end of the D flip-flop in the group control unit; the drains of the pull-down NMOS tubes in the group control units corresponding to the same block control unit are connected and connected to the feedback end of the block control unit, and when any group control unit outputs a valid selection signal, the block control unit receives a feedback signal of a valid level through the feedback end; when the block control unit receives a valid block selection signal and receives a feedback signal of a valid level through the feedback end, the block control unit outputs a valid selection signal.
7. The hierarchical word line preprocessing circuit according to claim 6, characterized in that: Each block control unit includes a PMOS inverse ratio tube P0 and NMOS tubes N0, N1 and N2, the source of P0 is connected to the core voltage, the drain is connected to the drain of N0, the source of N0 is grounded, the gate of P0 is connected to the gate of N0 and connected to the configuration enable signal, and the common end of P0 and N0 is connected to the output selection signal through an inverter and a buffer in turn; the common end of P0 and N0 is also connected to the drain of N2, the source of N2 is connected to the drain of N1, the source of N1 is grounded, the block selection signal is connected to the gate of N2, and the block selection signal is connected to the gate of N1 through an inverter, and the common end of N1 and N2 serves as the feedback end of the block control unit.
8. The hierarchical word line preprocessing circuit according to claim 4, characterized in that: Each control unit of each layer of control circuit outputs a selection signal including a first signal and a second signal with opposite phases, each decoding unit includes a pull-up component and a pull-down component connected in series, the decoding unit is connected to the variable positive voltage through the pull-up component and to the negative voltage through the pull-down component, and the common end of the pull-up component and the pull-down component leads to a word line control signal; the pull-up component of the decoding unit is controlled by the read-write signal and the corresponding The control units at different levels output The second signal of the pull-down component is controlled by the erase signal and the corresponding The control units at different levels output The first signal of the channel; when the decoding unit receives The first signal of the effective level and When a second signal of a word line effective level is received, it is determined that a word line selection signal for instructing selection of a connected word line is received.
9. The hierarchical word line preprocessing circuit according to claim 8, characterized in that: For each decoding unit: The pull-up component includes four PMOS tubes, namely W_P0, W_P1, W_P2 and W_P3, the source of W_P3 is connected to the variable positive voltage, the drain is connected to the source of W_P2, the drain of W_P2 is connected to the source of W_P1, the drain of W_P1 is connected to the source of W_P0, the drain of W_P0 is used to connect the pull-down component and lead out the word line control signal, the gate of W_P3 is controlled by the low-level effective read and write signal, the gate of W_P0 is controlled by the second signal output by the block control unit corresponding to the decoding unit, the gate of W_P1 is controlled by the second signal output by the group control unit corresponding to the decoding unit, and the gate of W_P2 is controlled by the second signal output by the address latch unit corresponding to the decoding unit, and the three second signals are all low-level effective; The pull-down component includes four NMOS tubes, namely W_N0, W_N1, W_N2 and W_N3. The source of W_N0 is connected to the negative voltage, the drain is connected to the source of W_N1, the drain of W_N1 is connected to the source of W_N2, the drain of W_N2 is connected to the source of W_N3, the drain of W_N3 is used to connect the pull-up component and lead out the word line control signal, the gate of W_N0 is controlled by a high-level effective erase signal, the gate of W_N3 is controlled by a first signal output by a block control unit corresponding to the decoding unit, the gate of W_N2 is controlled by a first signal output by a group control unit corresponding to the decoding unit, and the gate of W_N1 is controlled by a first signal output by an address latch unit corresponding to the decoding unit, and all three first signals are high-level effective; When the decoding unit receives three high-level first signals and three low-level second signals, it determines that a word line selection signal for indicating selection of the connected word line is received.
10. The hierarchical word line preprocessing circuit according to claim 1, characterized in that: The number of control units at the next level corresponding to any two control units at the same level is the same or different.