Metal Oxide Semiconductor Device and Method of Manufacturing the Same

Abstract

The present invention provides a metal oxide semiconductor device and a manufacturing method thereof. The metal oxide semiconductor device includes: a semiconductor substrate, a field oxide layer, a first JFET injection region, and a second JFET injection region. The upper surface of the semiconductor substrate defines an active region and a plurality of gate regions, each active region is surrounded by a plurality of gate regions, and the plurality of gate regions are staggered with each other to form an overlapping gate intersection region. The field oxide layer locally covers the gate intersection region. The first JFET injection region is formed by injecting ions into the upper surface of the semiconductor substrate and is located in the gate intersection region, wherein the first JFET injection region is configured to surround the projection region of the field oxide layer in the gate intersection region. The second JFET injection region is formed by injecting ions into the upper surface of the semiconductor substrate and is located in the plurality of gate regions. The present invention improves the breakdown voltage, thereby improving the voltage withstand performance of the device in the diagonal direction of the gate intersection region and improving the stability of the device.

Description

Technical Field

[0001] The present invention relates to semiconductor devices, and particularly to a manufacturing method of a metal oxide semiconductor device capable of improving breakdown voltage and its manufacturing method. Background Art

[0002] Figure 1 As for Figure 2 it is a conventional planar MOS device. Figure 1 is a top view of the cell-level structure in the horizontal direction, Figure 2 is a top view of the cell-level structure in the horizontal direction. In the manufacturing process of the MOS device, a photomask is not used for the JFET implantation process. The JFET implantation region 150 and the semiconductor substrate 130 have the same conductivity type. At the same time, the doping concentration of the JFET implantation region 150 is greater than that of the semiconductor substrate 130.

[0003] Figure 2 On the right side in, it is along the diagonal direction of the gate intersection region 123 in the cell unit ( Figure 1 in the A-A' direction in the figure), and on the left side in the figure is the vertical cross-sectional structure along the width direction of the gate region 121 (or the gate region 122) ( Figure 1 in the B'-B direction in the figure). Due to the limitation of the cell structure itself, the length of the JFET implantation region 150 in the diagonal direction in the gate intersection region 123 is greater than the width of the JFET implantation region 150 in the gate region 121 (or the gate region 122). When a reverse voltage is applied, compared with the gate region 121 (or the gate region 122), the depletion regions at both ends in the gate intersection region 123 are not easily combined, resulting in a decrease in breakdown voltage, thus causing the operation of the planar MOS device to be unstable and the applicable operating range to be small. Summary of the Invention

[0004] Aiming at the deficiencies of the prior art, the technical problem to be solved by the present invention is that in the existing planar MOS device, the length of the JFET implantation region in the diagonal direction under the gate intersection region is too long, making it difficult for the depletion regions at both ends to combine, resulting in a decrease in breakdown voltage. The present invention provides a metal oxide semiconductor device, including: a semiconductor substrate, a field oxide layer, a first JFET implantation region, and a second JFET implantation region. The upper surface of the semiconductor substrate defines active regions and a plurality of gate regions. Each active region is surrounded by a plurality of gate regions, and the plurality of gate regions are staggered with each other to form an overlapping gate intersection region. The field oxide layer locally covers the gate intersection region. The first JFET implantation region is formed by implanting ions into the upper surface of the semiconductor substrate and is located in the gate intersection region, wherein the first JFET implantation region is configured to surround the projection region of the field oxide layer in the gate intersection region. The second JFET implantation region is formed by implanting ions into the upper surface of the semiconductor substrate and is located in the plurality of gate regions.

[0005] Preferably, the field oxide layer is located at the middle position of the gate intersection region.

[0006] Preferably, the ion doping concentration in the first JFET region and the second JFET region is greater than that in the semiconductor substrate.

[0007] Furthermore, the metal oxide semiconductor device further includes a gate electrode disposed above the plurality of gate regions and the gate intersection region.

[0008] Preferably, the gate electrode includes a gate dielectric layer formed above the plurality of gate regions and the gate intersection region, and a gate electrode layer stacked on the gate dielectric layer.

[0009] Preferably, the metal oxide semiconductor device further includes a second-conductivity-type source region and a second-conductivity-type well region. The second-conductivity-type well region is located on both sides of the plurality of gate regions. The second-conductivity-type source region is located between the active region and the plurality of gate regions, and between the active region and the gate intersection region, and the lower surface of the second-conductivity-type source region is in contact with the lower surface of the gate electrode.

[0010] Furthermore, the metal oxide semiconductor device further includes a second-conductivity-type contact body disposed in the second-conductivity-type well region and exposed.

[0011] Furthermore, the metal oxide semiconductor device further includes a source electrode stacked on the upper surface of the contact body, and the contact body and the second-conductivity-type well region simultaneously contact the lower surface of the source electrode.

[0012] Furthermore, the metal oxide semiconductor device further includes a drain electrode located on the lower surface of the semiconductor substrate.

[0013] The present invention also provides a method for manufacturing a metal oxide semiconductor device, characterized in that it includes: providing a semiconductor substrate of a first conductivity type; forming a field oxide layer on the upper surface of the semiconductor substrate, and etching the field oxide layer to expose a ring injection region and cover an area predetermined as a cell region; wherein the cell region defines an active region and multiple gate regions, the active region is surrounded by multiple gate regions, and the multiple gate regions are staggered to form overlapping gate intersection regions; performing ring injection on the semiconductor substrate in the ring injection region and pushing the ring injection region to form the ring injection region, and continuing to grow the field oxide layer after pushing the ring injection; etching the field oxide layer again to partially cover the gate intersection region; wherein the uncovered portion of the gate intersection region surrounds the field oxide layer; and performing JFET injection processing on the gate region and the gate intersection region using the field oxide layer as a photomask to diffusely form a first JFET injection region located in the gate intersection region and a second JFET injection region located in the multiple gate regions; wherein the first JFET injection region is configured to surround the projection area of the field oxide layer on the gate intersection region.

[0014] Furthermore, the method for manufacturing the metal oxide semiconductor device further includes forming a gate electrode on the plurality of gate regions and the gate intersection region.

[0015] Preferably, the step of forming the gate electrode includes: forming a gate dielectric layer on the plurality of gate regions and the gate intersection region; and stacking a gate electrode layer on the gate dielectric layer to form the gate electrode.

[0016] Furthermore, the method for manufacturing the metal oxide semiconductor device further includes, after the gate electrode is formed, performing a second conductivity type well implantation and push-in junction on the active area through a self-aligned process to form a second conductivity type well region located on both sides of the plurality of gate regions.

[0017] Furthermore, the method for manufacturing a metal oxide semiconductor device also includes injecting first conductive type ions with high doping concentration between the active area and multiple gate areas and between the active area and the gate intersection area through a photolithography plate and performing push-in to form a first conductive type source area.

[0018] Furthermore, the method for manufacturing a metal oxide semiconductor device also includes depositing a passivation material on the upper surface of the semiconductor substrate to form a passivation layer, etching the passivation layer to form a through hole above the second conductive type well region; and injecting a high doping concentration of second conductive type ions into the through hole to form a second conductive type contact body located in the second conductive type well region and exposed.

[0019] Further, the method for manufacturing a metal oxide semiconductor device further includes: depositing a front metal layer on the upper surface of the semiconductor substrate, and etching the deposited front metal layer to form a source electrode stacked on the upper surface of the contact body, and the contact body and the second conductivity type well region simultaneously contact the lower surface of the source electrode; and depositing a back metal layer on the lower surface of the semiconductor substrate to serve as a drain electrode.

[0020] The beneficial effect of the present invention is that: the first JFET injection region formed by using the field oxide layer as a photomask substantially forms two JFET injection regions that are shorter (smaller in width) in the lateral direction, enabling the depletion regions at both ends of the gate intersection region to be more easily combined, thereby improving the breakdown voltage, and further enhancing the voltage withstand performance of the device in the diagonal direction of the gate intersection region and improving the stability of the device.

[0021] The above description is only an overview of the technical solution of the present invention. In order to understand the technical means of the present invention more clearly and implement it in accordance with the content of the specification, the following describes the present invention in detail with reference to the preferred embodiments of the present invention and the accompanying drawings. Brief Description of the Drawings

[0022] Figure 1 is a top view in the horizontal direction of the cell level structure in an existing planar MOS device.

[0023] Figure 2 is Figure 1 the vertical cross-sectional structure along the A-A' direction and the B-B' direction in.

[0024] Figure 3 is a top view in the horizontal direction of the cell level structure in the metal oxide semiconductor device according to the embodiment of the present invention.

[0025] <H Figure 4 is Figure 3 the vertical cross-sectional structure along the A-A' direction and the B-B' direction in.

[0026] Figure 5 and Figure 6 are top views in the horizontal direction of the cell level structure in the metal oxide semiconductor devices according to different embodiments of the present invention.

[0027] Figure 7A and Figure 7B is a flowchart of the method for manufacturing the metal oxide semiconductor device according to the present invention.

[0028] Figures 8 to 15 is the vertical cross-sectional structure of the metal oxide semiconductor device at different steps in the process of the manufacturing method according to the present invention.

[0029] 110 Active Region

[0030] 111 Second-conductivity-type source region

[0031] 112 Second-conductivity-type well region

[0032] 121, 122 Gate regions

[0033] 130 Semiconductor substrate

[0034] 131 Cell region

[0035] 132 Ring implantation region

[0036] 133 Substrate

[0037] 140 Field oxide layer

[0038] 151 First JFET implantation region

[0039] 152 Second JFET implantation region

[0040] 153 Gate dielectric layer

[0041] 154 Gate electrode layer

[0042] 160 Contact

[0043] 170 Source electrode

[0044] 180 Drain electrode

[0045] S110 to S190 Steps Detailed implementation manners

[0046] The following describes the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0047] The present invention will be described in more detail below with reference to the accompanying drawings. In each drawing, the same elements are denoted by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps may be described in one drawing.

[0048] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "above", "upper surface" or "above" another layer or another region, it may mean directly above the other layer or another region, or there may be other layers or regions between it and the other layer or another region. And if the device is flipped, this layer or region will be located "below", "lower surface" or "below" the other layer or another region.

[0049] In this application, the term "semiconductor structure" refers to the general term for the entire semiconductor structure formed in each step of manufacturing a semiconductor device, including all the layers or regions that have been formed. The term "laterally extending" means extending along a direction substantially perpendicular to the depth direction of the gate regions 121, 122; the term "vertical" means perpendicular to the first surface and arranged based on the normal direction of the first surface parallel to the semiconductor substrate or body.

[0050] Refer to Figure 3 As shown, it is a top view of the cell-level structure of the metal oxide semiconductor device according to an embodiment of the present invention in the horizontal direction. As Figure 3 shown, the cell-level structure is an array arrangement structure of regular polygons. The dotted box column part in the figure represents a cell, and the cell-level structure can be composed of multiple cells. The cell-level structure includes a plurality of active regions 110 connected in parallel and gate regions 121, 122 distributed around each active region 110. That is, a plurality of active regions 110 and a plurality of gate regions 121, 122 are provided on the upper surface of the semiconductor substrate 130. The gate regions 121, 122 are arranged around the active regions 110 and connected into a gate grid to isolate each active region 110. Taking Figure 3 the longitudinal and transverse directions in it as an example, the plurality of gate regions 121, 122 include spaced-apart transverse gate regions 121 and spaced-apart longitudinal gate regions 122. The transverse gate regions 121 and the longitudinal gate regions 122 are staggered to form a gate intersection region 123 where the transverse gate regions 121 and the longitudinal gate regions 122 overlap. The shape formed after enclosing the plurality of gate regions 121, 122 is the same as the cell shape of a single cell unit in the horizontal direction, which is a polygon, such as a square, a rectangle, a hexagon, etc.; affected by the shape of the cell unit, the shape of the gate intersection region 123 in the horizontal direction is also a regular polygon.

[0051] Please refer to Figure 4 As shown, on the right side of the figure is the vertical cross-sectional structure along the diagonal direction of the gate intersection region 123 ([[]]END]] Figure 3 the A-A' direction in it), and on the left side of the figure is the vertical cross-sectional structure along the width direction of the gate region 121 (or the gate region 122) ([[]]END]] Figure 3 the B'-B direction in it). As Figure 4As shown, the metal oxide semiconductor device includes a semiconductor substrate 130, which is doped to a first conduction type. A plurality of gate intersection regions 123 and a plurality of gate regions 121 are located on the upper surface of the semiconductor substrate 130. The active region 110 is generally composed of adjacent source regions of a second conduction type and well regions of a second conduction type. Both the gate intersection regions 123 and the gate regions 121 are located between a plurality of adjacent active regions 110, and a field oxide layer 140 is formed on the gate intersection regions 123, and the field oxide layer 140 partially covers the gate intersection regions 123. Using the field oxide layer 140 as a photomask, JFET implantation is performed on the gate intersection regions 123, such that the semiconductor substrate 130 under the field oxide layer 140 is not subjected to JFET implantation, but a configuration surrounding the projection region of the field oxide layer 140 in the gate intersection regions 123 is formed, and a first JFET implantation region 151 surrounding the field oxide layer 140 is formed, that is, the first JFET implantation region 151 is basically not included under the field oxide layer 140. In the gate intersection regions 123, the gate electrodes 150 basically cover the field oxide layer 140 and other parts of the gate intersection regions 123. On the contrary, other parts of the gate regions 121, 122 are not covered by the field oxide layer 140, so that second JFET implantation regions 152 corresponding to the entire gate regions 121, 122 can be formed. The JFET implantation regions 151, 152 and other structural regions on both sides form two relatively distributed PN junctions and depletion layers corresponding to the PN junctions; each depletion layer is distributed on both sides of the JFET implantation regions 151, 152 and is relatively distributed.

[0052] As Figure 4 shown, overall, the vertical structure of the gate intersection regions 123 still forms a first JFET implantation region 151, but this first JFET implantation region 151 surrounds a non-implanted region, and the non-implanted region is located under the field oxide layer 140. Figure 4 Although two first JFET implantation regions 151 are presented in Figure 4 , actually the first JFET implantation region 151 in

[0053] As Figure 4 , Figure 5 and Figure 6As shown, the field oxide layer 140 partially covers the middle area of the gate intersection region 123, while leaving an uncovered area substantially surrounding the field oxide layer. The shape of the field oxide layer 140 can be polygonal, circular or even complex. Figure 4 As shown, the field oxide layer 140 is substantially in the shape of a square, with its sides forming a 45-degree angle with the vertical / horizontal gate regions 121 , 122 . However, the corners of the square extend into horizontal or vertical extension blocks, making the field oxide layer 140 present a complex shape. Figure 5 The shape of the field oxide layer 140 is shown to be a simple square or quadrilateral. Figure 6 The shape of the field oxide layer 140 is shown to be circular.

[0054] See also Figure 7A and Figure 7B The flowchart shown, together with the following figures and description, further illustrates the detailed structure and manufacturing method of the metal oxide semiconductor device.

[0055] like Figure 8 and Figure 9 As shown, first, a semiconductor substrate 130 is provided, a field oxide layer 140 is formed on the upper surface of the semiconductor substrate 130, and the field oxide layer 140 is etched through a photoresist to expose the Ring injection area 132 and cover the area predetermined as the cell area 131, as shown in step S110.

[0056] Next, a ring implant is performed on the semiconductor body 130 in the ring implant region 132, and a push-up is performed to form the ring implant region 132. After the push-up, the field oxide layer 140 is grown, as shown in step S120. The semiconductor body 130 can be an epitaxial layer formed on a substrate 133 having a first conductivity type, thereby forming a semiconductor body layer 130 having the first conductivity type as a whole.

[0057] like Figure 10 As shown, the cell region 131 of the semiconductor substrate 130 may be defined as a plurality of active regions 110 and a plurality of gate regions 121, 122 ( Figure 10 (Only the lateral gate region 121 is shown as an example) wherein the active region 110 is surrounded by multiple gate regions 121, 122, and the multiple gate regions 121, 122 are staggered to form an overlapping gate intersection region 123. Next, the field oxide layer 140 is etched again to remove the field oxide layer 140 from the active region 110 and the gate regions 121, 122, leaving the field oxide layer 140 partially covering the gate intersection region 123, as shown in step S130. The field oxide layer 140 is substantially located in the middle of each gate intersection region 123, such that the uncovered portion of each gate intersection region 123 surrounds the field oxide layer 140.

[0058] like Figure 10As shown, using the field oxide layer 140 as a photomask, JFET implantation is performed on the gate regions 121, 122 and the gate intersection region 123, as shown in step S140.

[0059] The above JFET implantation process includes using the field oxide layer 140 as a photomask to implant ions of a first conductivity type into the cell region 131 of the semiconductor substrate 130, and diffusing to form a first JFET implantation region 151 located in the gate intersection region 123 and a second JFET implantation region 152 located in the gate regions 121, 122; the ion doping concentration in the JFET regions 151, 152 is greater than the ion doping concentration in the semiconductor substrate 130. Using the field oxide layer 140 as a photomask, the semiconductor substrate 130 under the field oxide layer 140 does not undergo JFET implantation, such that the corresponding first JFET implantation region 151 in the gate intersection region 123 is configured to surround the projection region of the field oxide layer 140 in the gate intersection region 123, and there is basically no JFET implantation region in the projection region of the field oxide layer 140 in the gate intersection region 123 (i.e., under the field oxide layer 140).

[0060] As Figure 11 shown, a gate dielectric layer 153 is formed over the gate regions 121, 122 and the gate intersection region 123, and a gate electrode layer 154 is stacked on the gate dielectric layer 153 to form a gate electrode 150, as shown in step S150.

[0061] As Figure 11 shown, in the gate intersection region 123, the gate electrode 150 basically covers the field oxide layer 140 and other parts of the gate intersection region 123, and in the part corresponding to the field oxide layer 140, the gate electrode 150 is raised. The gate dielectric layer 153 includes, but is not limited to, an oxide layer, an interlayer dielectric, or other insulating materials; the gate electrode layer 154 includes, but is not limited to, polysilicon, metal, or other conductive materials. In one embodiment, the process of stacking the gate electrode layer 154 is to directly deposit polysilicon on the semiconductor substrate 130 and etch the polysilicon to retain the polysilicon on the gate dielectric layer 153 as the gate electrode layer 154.

[0062] As Figure 12 shown, after the gate electrode 150 is formed, through a self-alignment process, a well implantation of a second conductivity type is performed on the active region 110 and a push junction is carried out to form second conductivity type well regions 112 on both sides of the gate regions 121, 122, as shown in step S160. When the second conductivity type is P, the second conductivity type well regions 112 are Pbody and correspond to the gate regions 121, 122.

[0063] As Figure 13As shown, first conductive type ions (such as N plus) with high doping concentration are then implanted between the active area 110 and the gate areas 121, 122, and between the active area 110 and the gate intersection area 123 through a photomask, and push-up is performed to form a first conductive type source area 111, as shown in step S170.

[0064] like Figure 14 As shown, a passivation material is deposited on the upper surface of the semiconductor substrate 130 to form a passivation layer, and the passivation layer is etched to form a through hole above the second conductive type well region 112; and second conductive type ions (such as P plus) with a high doping concentration are injected into the through hole to form a second conductive type contact body 160 located in the second conductive type well region 112 and exposed, as shown in step S180.

[0065] like Figure 15 As shown, after each contact 160 is formed, a front metal layer is deposited on the upper surface of the semiconductor substrate 130 and the deposited front metal layer is etched to form a source electrode 170 stacked on the upper surface of the contact 160. The contact 160 and the second conductivity type well region 112 simultaneously contact the lower surface of the source electrode 170, as shown in step S190. At the same time or thereafter, a back metal layer can also be deposited on the lower surface of the semiconductor substrate 130 to serve as the drain electrode 180.

[0066] The above-described fabrication method yields a metal oxide semiconductor device of the present invention. In the metal oxide semiconductor device, the first JFET implant region 151 formed by using the field oxide layer 140 as a photomask essentially forms two laterally shorter (smaller) JFET implant regions. This facilitates the integration of the depletion regions at both ends of the gate intersection region 123, thereby increasing the breakdown voltage and, in turn, improving the device's withstand voltage performance in a diagonal direction across the gate intersection region 123, thereby improving device stability.

[0067] Those skilled in the art will also understand that for purposes of clarity, the elements (e.g., components, regions, layers, etc.) in the various figures are not drawn to scale. Furthermore, the elements in the figures are not necessarily their actual shapes. Those skilled in the art will understand that these shapes are for illustrative purposes only. For example, actual doping profiles typically have a transition region, slope, or gradient, rather than a profile where the gradient is infinite at a certain point or boundary.

[0068] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A metal oxide semiconductor device, characterized in that, include: A semiconductor substrate having an upper surface defining an active region and a plurality of gate regions, each of the active regions being surrounded by the plurality of gate regions, and the plurality of gate regions being interlaced to form overlapping gate intersection regions; a field oxide layer partially covering the gate intersection region; a first JFET implantation region formed by implanting ions into the upper surface of the semiconductor substrate and located in the gate intersection region, wherein the first JFET implantation region is configured to surround a projection of the field oxide layer on the gate intersection region; as well as The second JFET implantation region is formed by implanting ions into the upper surface of the semiconductor substrate and is located in the plurality of gate regions.

2. The metal oxide semiconductor device according to claim 1, wherein The field oxide layer is located in the middle of the gate intersection region.

3. The metal oxide semiconductor device according to claim 1, characterized in that, The ion doping concentration of the first JFET implantation region and the second JFET implantation region is greater than the ion doping concentration in the semiconductor substrate.

4. The metal oxide semiconductor device according to claim 1, wherein The invention also includes a gate electrode, which is arranged on the multiple gate regions and the gate intersection region.

5. The metal oxide semiconductor device according to claim 4, wherein The gate electrode includes a gate dielectric layer formed on the plurality of gate regions and the gate intersection region, and a gate electrode layer stacked on the gate dielectric layer.

6. The metal oxide semiconductor device according to claim 4, wherein It also includes a second conductive type source region and a second conductive type well region, the second conductive type well region is located on both sides of the multiple gate regions, the second conductive type source region is located between the active region and the multiple gate regions, and between the active region and the gate intersection region, and the second conductive type source region is in contact with the lower surface of the gate electrode.

7. The metal oxide semiconductor device according to claim 6, wherein The device further comprises a contact body of the second conductive type, which is disposed in the second conductive type well region and exposed.

8. The metal oxide semiconductor device according to claim 7, wherein The device further includes a source electrode stacked on the upper surface of the contact body, and the contact body and the second conductive type well region are in contact with the lower surface of the source electrode at the same time.

9. The metal oxide semiconductor device according to claim 7, wherein It also includes a drain electrode located on the lower surface of the semiconductor substrate.

10. A method for fabricating a metal oxide semiconductor device, characterized in that, include: providing a semiconductor substrate of a first conductivity type; forming a field oxide layer on the upper surface of the semiconductor substrate and etching the field oxide layer to expose the ring injection region and cover the area predetermined as the cell region; wherein the cell region defines an active region and a plurality of gate regions, the active region is surrounded by the plurality of gate regions, and the plurality of gate regions are interlaced to form overlapping gate intersection regions; Performing ring implantation on the semiconductor substrate in the ring implantation region and pushing the junction to form the ring implantation region, and continuing to grow the field oxide layer after pushing the junction; Etching the field oxide layer again so that the field oxide layer partially covers the gate intersection region; wherein the uncovered portion of the gate intersection region surrounds the field oxide layer; and Using the field oxide layer as a photomask, JFET injection processing is performed on the gate region and the gate intersection region to diffusely form a first JFET injection region located in the gate intersection region and a second JFET injection region located in the multiple gate regions; wherein the first JFET injection region is configured to surround the projection area of the field oxide layer on the gate intersection region.

11. The manufacturing method of the metal oxide semiconductor device according to claim 10, characterized in that, The method further includes forming a gate electrode on the plurality of gate regions and the gate intersection region.

12. The manufacturing method of the metal oxide semiconductor device according to claim 11, characterized in that, The steps of forming the gate electrode include: forming a gate dielectric layer over the plurality of gate regions and the gate intersection region; and stacking a gate electrode layer on the gate dielectric layer to form the gate electrode.

13. The manufacturing method of the metal oxide semiconductor device according to claim 12, characterized in that, It further includes, after the gate electrode is formed, performing a well implantation of a second conductivity type and a drive-in on the active region through a self-alignment process to form second conductivity type well regions on both sides of the plurality of gate regions.

14. The method for manufacturing a metal oxide semiconductor device according to claim 13, wherein It further includes implanting ions of a first conductivity type with a high doping concentration and performing a drive-in between the active region and the plurality of gate regions and between the active region and the gate intersection region through a photomask to form a first conductivity type source region.

15. The method for fabricating a metal oxide semiconductor device according to claim 14, wherein, It further includes depositing a passivation material on the upper surface of the semiconductor substrate to form a passivation layer, etching the passivation layer to form a through hole above the second conductivity type well region; and implanting ions of a second conductivity type with a high doping concentration into the through hole to form a contact of the second conductivity type located in the second conductivity type well region and exposed.

16. The method for manufacturing a metal oxide semiconductor device according to claim 15, wherein It further includes: depositing a front metal layer on the upper surface of the semiconductor substrate, and etching the deposited front metal layer to form a source electrode stacked on the upper surface of the contact, and the contact and the second conductivity type well region simultaneously contact the lower surface of the source electrode; and depositing a back metal layer on the lower surface of the semiconductor substrate to serve as a drain electrode.

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