Digital Line Management for Memory Arrays

Abstract

This application relates to digital line management for a memory array. The memory array may include a common plate shared by multiple memory cells. Each memory cell associated with the common plate may be coupled to a respective digital line. One or more memory cells sharing the common plate may be accessed by selectively activating the common plate and each digital line associated with the common plate in parallel. Parallel selection of all digital lines associated with the common plate may be supported by shield lines between the selected digital lines. Additionally or alternatively, selection of all digital lines associated with the common plate may be supported by an improved sensing scheme and associated amplifier configuration.

Description

[0001] Cross-reference

[0002] This patent application claims priority to PCT Application No. PCT / US2020 / 038060, filed Jun. 17, 2020, by Guo et al., entitled "DIGIT LINE MANAGEMENT FOR A MEMORY ARRAY", which claims priority to U.S. Patent Application No. 16 / 450,033, filed Jun. 24, 2019, by Guo et al., entitled "DIGIT LINE MANAGEMENT FOR A MEMORY ARRAY", each of which is assigned to the assignee hereof and each of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] This technical field relates to digit line management for a memory array. BACKGROUND OF THE DISCLOSURE

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming different states of the memory device. For example, binary devices most often store one of two states, typically represented by a logic 1 or a logic 0. In other devices, more than two states may be stored. To access the stored information, components of the device may read or sense at least one of the stored states in the memory device. To access the information, components of the device may write or program the states in the memory device.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), etc. Memory devices may be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain its stored logical state for a long time even in the absence of an external power source. Volatile memory devices, such as DRAM, may lose their stored states when disconnected from an external power source. FeRAM can achieve a density similar to volatile memory but can have non-volatile characteristics because it uses a ferroelectric capacitor as the storage device.

[0006] In general, improving a memory device may include increasing memory cell density, increasing read / write speed, increasing reliability, increasing data retention, reducing power consumption, reducing manufacturing cost, and other metrics. SUMMARY OF THE INVENTION

[0007] Describe a method. In some instances, the method may include: selecting a plate shared by a group of ferroelectric memory cells, each of the group of ferroelectric memory cells being coupled to a respective digit line of a group of digit lines corresponding to the plate; selecting the group of digit lines corresponding to the plate based on the selection of the plate; when selecting the group of digit lines corresponding to the plate, selecting a word line coupled to a subset of the group of ferroelectric memory cells; and sensing a respective charge stored by each ferroelectric memory cell of the subset based on the selection of the word line.

[0008] Describe a device. In some instances, the device may include a group of sense amplifiers, a memory array including a group of plates each of which is common to a respective group of ferroelectric memory cells, where each respective group of ferroelectric memory cells is coupled to a respective digit line of a group of digit lines, the group of digit lines corresponding to the plate in the group of plates, and the group of digit lines corresponding to the plate in the group is configured to be coupled to a respective sense amplifier in the group in parallel.

[0009] Describe a method. In some instances, the method may include: selecting a first digit line coupled to a first ferroelectric memory cell and a second digit line coupled to a second ferroelectric memory cell, the first ferroelectric memory cell and the second ferroelectric memory cell being coupled to a plate, and wherein the first digit line is electrically isolated from the second digit line by a shield line; and performing an access operation on the first ferroelectric memory cell when selecting the second digit line.

[0010] Describe a device. The device may include: a first digit line coupled to a first ferroelectric memory cell; a second digit line coupled to a second ferroelectric memory cell; a plate common to the first ferroelectric memory cell and the second ferroelectric memory cell; and a shield line positioned between the first digit line and the second digit line and configured to electrically isolate the first digit line from the second digit line during an access operation associated with the first ferroelectric memory cell, the second ferroelectric memory cell, or both. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 Illustrate an example of a system that supports digit line management for a memory array according to the examples disclosed herein.

[0012] Figure 2Describe examples of memory dies that support digital line management for a memory array according to the examples disclosed herein.

[0013] Figure 3A and 3B Describe examples of hysteresis curves that support digital line management for a memory array according to the examples disclosed herein.

[0014] Figure 4 Describe examples of memory arrays that include a common board that supports digital line management for a memory array according to the examples disclosed herein.

[0015] Figure 5 Describe examples of memory arrays that include a board that supports digital line management for a memory array according to the examples disclosed herein.

[0016] Figure 6 Describe examples of memory arrays that include a selected board that supports digital line management for a memory array according to the examples disclosed herein.

[0017] Figure 7A and 7B Describe example shield lines that support digital line management for a memory array according to the examples disclosed herein.

[0018] Figure 8 Describe examples of memory arrays that include a selected board that supports digital line management for a memory array according to the examples disclosed herein.

[0019] Figure 9 Describe examples of sense amplifiers that support digital line management for a memory array according to the examples disclosed herein.

[0020] Figure 10 Describe examples of timing diagrams that operate sense amplifiers that support digital line management for a memory array according to the examples disclosed herein.

[0021] Figure 11 Show a block diagram of a memory array that supports digital line management according to aspects of the present disclosure.

[0022] Figure 12 and 13 Show a flowchart that illustrates a method or methods that support digital line management for a memory array according to the examples disclosed herein. Detailed Description

[0023] Read or sense operations in accordance with aspects of the present disclosure may be used to concurrently detect the logical states of multiple memory cells. In some memory architectures, memory cells (e.g., ferroelectric memory cells) may be coupled to digit lines, word lines, and plates (e.g., plates coupled to plate lines). In some cases, a single plate may be shared (e.g., shared by, coupled to) by multiple ferroelectric memory cells. This may reduce, for example, the complexity of the control scheme and associated circuitry (e.g., decoder circuitry) compared to each memory cell having a unique, separately controlled plate.

[0024] A single memory array may include one or more sub-blocks, and each sub-block may include any number of plates. Additionally, the plates within a sub-block may be grouped into any number of plate groups (e.g., units, sets of plates). For example, a sub-block may include 10 plate groups, and each plate group may include 32 plates. These and other numerical examples used herein are for illustrative clarity only and are merely examples; any numerical examples herein do not limit the scope of the claims. In some cases, as part of a set of parallel access operations (e.g., parallel read or write operations to multiple memory cells within an array), one plate within each plate group may be activated (selected), and one or more memory cells coupled thereto may be activated. For example, multiple plates within a sub-block may be activated simultaneously, but each simultaneously activated plate may be within a different plate group, where one plate is activated for each plate group.

[0025] Each plate may be shared by any number of memory cells. Thus, in an array in which memory cells are arranged in columns and rows, memory cells sharing (corresponding to, having) the same plate may include (be arranged in) any number of columns and rows. Each row of memory cells may correspond to (be coupled to) the same word line, and each column of memory cells may correspond to (be coupled to) the same digit line. In some cases, a word line may span multiple plates (e.g., may span all plate groups and thus all plates within a sub-block). For example, the memory cells of an array may be arranged in rows such that each row spans multiple plates and multiple plate groups, and each such row may correspond to the same word line. In some cases, digit lines may each be specific to one plate. For example, the memory cells of an array may be arranged in columns each dedicated to (specific to) one plate (e.g., columns may not cross plate boundaries). Thus, digit lines corresponding to columns of memory cells sharing (having) a common plate may be referred to as digit lines for the plate (associated with the plate, corresponding to the plate). For example, each plate may be associated with 8 columns of memory cells and thus 8 digit lines.

[0026] In some memory architectures, it may not be possible (at least without an undesirable performance impact) to select (activate, access the memory cells coupled thereto) each digital line (all digital lines) of a bank in parallel. For example, selecting adjacent digital lines may result in an unintended cross-coupling effect (e.g., capacitive cross-coupling or crosstalk) between two selected digital lines. When cross-coupling occurs, the data read from or written to the memory cells of the selected digital lines may be corrupted. Thus, in such architectures, only a subset of the digital lines associated with a selected bank (e.g., every other digital line, every fourth digital line, or other non-adjacent digital lines) can be selected in parallel, with one or more unselected digital lines between each pair of selected digital lines.

[0027] In the case of selecting only a subset of the digital lines corresponding to a bank, a physically larger bank may be used to accommodate the larger number of digital lines associated with the bank, e.g., such that a desired total number of parallel selected digital lines (bandwidth) per bank can be achieved without selecting adjacent digital lines. For example, if for one byte bandwidth per selected bank, it is desired to access 8 memory cells in parallel per selected bank, and if only every fourth digital line corresponding to the bank is selected in parallel, the bank must correspond to at least 32 digital lines, which may make the bank physically larger than a bank that can only correspond to 8 selected digital lines. The power required to select a bank (e.g., increase or decrease the voltage of the bank) may be proportional to the physical size of the bank, and thus a physically larger bank (e.g., a bank corresponding to more digital lines) may result in an increased power consumption of the array.

[0028] In addition, when only a subset of the digital lines corresponding to a bank are selected and as part of an access operation, the voltage of the selected bank is increased or decreased, the unselected digital lines corresponding to the bank may be shunted (shorted, coupled) to the bank. This shunting may be intended to maintain a constant (e.g., zero) voltage difference across the unselected memory cells (memory cells coupled to the unselected digital lines) when the voltage of the selected bank changes. However, when the voltage of the selected bank changes, the voltage of the shunted (unselected) digital lines may follow the voltage of the bank with some delay (hysteresis) - e.g., due to the resistance-capacitance (RC) effects or other characteristics of the bank (and associated bank lines) and the digital lines. This hysteresis may result in an undesirable change (e.g., increase) in the voltage difference between the selected bank and the shunted digital lines, at least until the digital line voltage reaches the final bank voltage. Moreover, the faster the bank voltage changes (the greater the rate of increase or decrease of the voltage, or slew rate), the greater the undesirable change in the voltage difference between the selected bank and the shunted digital lines may be (e.g., the difference may become greater when the bank voltage changes).

[0029] Thus, in some memory architectures, the speed (rate) at which the board voltage changes - i.e., the slew rate of the board voltage - can be limited (controlled, artificially slowed down) in order to reduce the voltage difference between a selected board and the shunted (unselected) digital lines, and thereby reduce the risk of interference with the memory cells coupled to the shunted digital lines. Limiting the slew rate of the board voltage may increase the amount of time required for access operations of the memory cells sharing the board (e.g., may increase the row cycle time (tRC) or other time intervals associated with the access operation), and thus may slow down the overall speed at which reads, writes, and other accesses can occur.

[0030] In addition, in some memory architectures, as part of an access operation, the voltage of a selected digital line can be increased or decreased (toggle). When a subset of digital lines corresponding to a board is selected, the toggle voltage of the selected digital lines may interfere with the memory cells coupled to the unselected digital lines corresponding to the board (e.g., due to capacitive coupling between the digital lines). Thus, in some memory architectures, the speed (rate) at which the voltage of a selected digital line changes - i.e., the slew rate of the digital line voltage - can be limited (controlled, artificially slowed down) in order to reduce the risk of interference with the memory cells coupled to the unselected digital lines. However, just as limiting the slew rate of the board voltage, limiting the slew rate of the digital line voltage may increase the amount of time required for access operations of the memory cells sharing the board (e.g., may increase the row cycle time (tRC) or other time intervals associated with the access operation), and thus may slow down the overall speed at which reads, writes, and other accesses can occur.

[0031] Accordingly, a sensing scheme (e.g., the sensing schemes described herein) that allows for parallel (e.g., simultaneous) selection and access of adjacent digital lines (including adjacent digital lines associated with a shared board) can be beneficial. For example, such a sensing scheme can reduce power consumption - e.g., by allowing the board to correspond only to the number of digital lines that need to be selected for an access operation, and thus allowing for a reduced physical size of the board compared to some memory architectures in which only a subset of the corresponding digital lines are selected for a selected board. As another example, compared to some memory architectures in which only a subset of the corresponding digital lines are selected for a selected board, such a sensing scheme can allow for faster (e.g., uncontrolled) access (e.g., read or write) operations, for example, by allowing for a faster slew rate of the board and digital lines. Those skilled in the art will appreciate these and other benefits.

[0032] In some instances, the digital lines of a common board may be separated by one or more shield lines. A shield line may refer to any conductive wire that can be grounded to protect (e.g., "shield") adjacent digital lines from unintended cross-coupling effects. Different from digital lines, a shield line may be electrically isolated (not coupled to any memory cell) from any memory cell. Additionally, the voltage of the shield line may not be selectable (controllable), e.g., the shield line may be hard-wired to ground or to a virtual ground. For example, a memory array as described herein may include ten board groups, and each board group may include 32 boards. In some instances, each board may be associated with 8 digital lines, and at least 2 of the digital lines may be separated from each other by a shield line. As used herein, when a shield line is located between digital lines or otherwise configured to electrically isolate one of the digital lines from another of the digital lines, the digital lines may be said to be separated by the shield line. In other instances, any subset of the digital lines (including each of the 8 digital lines) may be separated by a shield line. Since each shield line may be grounded, each digital line may be selected in parallel without any unintended cross-coupling. That is, the shield line may allow increasing or decreasing the voltage of the board, selecting each digital line in parallel, and performing access operations on any one or more of the memory cells selected in parallel. Selecting each digital line in parallel and performing access operations on one or more of the memory cells may help reduce the power consumption of the memory array, and may improve the time required to access the memory cells associated with a single board, among other benefits.

[0033] Additionally or alternatively, the architecture of a sense amplifier for sensing memory cells may support selecting each of the digital lines of a common board in parallel. To sense a memory cell, a corresponding digital line may be selected, and a signal may be transmitted along the selected line. For example, to sense the logic state stored at a memory cell, a digital line may be selected, and a signal corresponding to the logic state of the memory cell may be transmitted along the digital line and transmitted to the sense amplifier. Based on the value of the received signal (e.g., based on the associated voltage value of the signal), the sense amplifier is capable of determining the stored logic state.

[0034] A sense amplifier according to aspects of the present disclosure can be a high-gain sense amplifier configured to sense a smaller change in the voltage of a digital line compared to some sense amplifiers, which can support the use of lower voltage swing (lower swing) signals on the digital line. By using lower swing signals on the selected digital lines, crosstalk effects can be reduced. Additionally, due to the structure of the sense amplifier (e.g., by having a higher gain sense amplifier), the voltage values associated with one or more memory cells can be accurately sensed in parallel. Thus, the sense amplifier as described herein can support selecting each digital line in parallel and performing access operations on one or more of the associated memory cells, which can reduce the power consumption of the memory array and can improve the time required to access the memory cells associated with a single board, among other benefits.

[0035] Features of the present disclosure are first described in the context of a memory system. Features of the present disclosure are described in the context of memory arrays, circuits, and timing diagrams that support digital line management for a memory array according to the examples disclosed herein. These and other features of the present disclosure are further illustrated by and described with reference to device diagrams, system diagrams, and flowcharts related to digital line management for a memory array.

[0036] Figure 1 An example of a system 100 that utilizes one or more memory devices according to the examples disclosed herein is illustrated. System 100 can include an external memory controller 105, a memory device 110, and a set of channels 115 that couple the external memory controller 105 to the memory device 110. System 100 can include one or more memory devices, but for ease of description, the one or more memory devices can be described as a single memory device 110.

[0037] System 100 can be part of an electronic device such as a computing device, a mobile computing device, a wireless device, or a graphics processing device. System 100 can be an example of a portable electronic device. System 100 can be an example of a computer, a laptop, a tablet, a smart phone, a cellular phone, a wearable device, an Internet-connected device, etc. The memory device 110 can be a component in the system configured to store data for one or more other components of system 100. In some examples, system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0038] At least a portion of system 100 may be an instance of a host device. Such a host device may be an instance of a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop, a tablet, a smart phone, a cellular phone, a wearable device, an Internet-connected device, some other fixed or portable electronic device, etc. In some cases, the host device may refer to hardware, firmware, software, or a combination thereof that implements the functions of the external memory controller 105. In some cases, the external memory controller 105 may be referred to as the host or host device.

[0039] In some cases, the memory device 110 may be a stand-alone device or component that is configured to communicate with other components of system 100 and provide physical memory addresses / spaces that system 100 may use or reference. In some instances, the memory device 110 may be configurable to work with at least one or a group of different types of systems 100. Signaling between the components of system 100 and the memory device 110 may be operable to support modulation schemes for modulating signals, different pin designs for transmitting signals, different packages of system 100 and the memory device 110, clock signaling and synchronization between system 100 and the memory device 110, timing conventions, and / or other factors.

[0040] The memory device 110 may be configured to store data for the components of system 100. In some cases, the memory device 110 may act as a slave device of system 100 (e.g., respond to and execute commands provided by system 100 via the external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. The memory device 110 may include two or more memory dies 160 (e.g., memory chips) that support the desired or specified capacity for data storage. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or package (also referred to as a multi-chip memory or package).

[0041] System 100 may further include a processor 120, a basic input / output system (BIOS) component 125, one or more peripheral components 130, and an input / output (I / O) controller 135. The components of system 100 may communicate with each other electronically using a bus 140.

[0042] The processor 120 can be configured to control at least a portion of the system 100. The processor 120 can be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or it can be a combination of these types of components. In such cases, the processor 120 can be an instance of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), or a system-on-chip (SoC), among other instances.

[0043] The BIOS component 125 can be a software component that includes BIOS operating as firmware, which can initialize and run various hardware components of the system 100. The BIOS component 125 can also manage the data flow between the processor 120 and various components of the system 100 (e.g., the peripheral components 130, the I / O controller 135, etc.). The BIOS component 125 can include programs or software stored in a read-only memory (ROM), flash memory, or any other non-volatile memory.

[0044] The peripheral components 130 can be any input device or output device, or an interface for such devices, which can be integrated into the system 100 or integrated with the system. Examples can include a disk controller, a sound controller, a graphics controller, an Ethernet controller, a modem, a universal serial bus (USB) controller, a serial or parallel port, or a peripheral card slot, such as a peripheral component interconnect (PCI) or a dedicated graphics port. The peripheral components 130 can be other components understood by those skilled in the art as peripheral devices.

[0045] The I / O controller 135 can manage data communication between the processor 120 and the peripheral components 130, the input device 145, or the output device 150. The I / O controller 135 can manage peripheral devices that are not integrated into the system 100 or not integrated with the system. In some cases, the I / O controller 135 can represent a physical connection or port to an external peripheral component.

[0046] The input 145 can represent a device or signal external to the system 100 that provides information, signals, or data to the system 100 or its components. This can include a user interface, or an interface with other devices or between other devices. In some cases, the input 145 can be a peripheral device interfacing with the system 100 via one or more peripheral components 130, or can be managed by the I / O controller 135.

[0047] Output 150 may represent a device or signal external to system 100 that is configured to receive an output from any one of system 100 or its components. Examples of output 150 may include a display, an audio speaker, a printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device interfaced with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0048] The components of system 100 may be composed of general-purpose or special-purpose circuitry designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as conductive wires, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive elements. For example, one or more memory arrays 170 may include a set of shield lines configured to isolate one or more selected access lines (e.g., one or more selected digital lines). In some instances, the shield lines may mitigate (e.g., prevent) unintended cross-coupling (e.g., capacitive cross-coupling or crosstalk) between adjacent selected access lines. In other instances, one or more memory arrays 170 may be coupled to sense amplifiers (e.g., high-gain sense amplifiers) configured to provide high-gain sensing when operating in the linear region of the amplifier, or otherwise reduce (e.g., eliminate) signal saturation. For example, each access line (e.g., each digital line) associated with the same board as memory array 170 may be selected, and at least one memory cell may be sensed while the access line is selected. A sense amplifier (e.g., high-gain sense amplifier) may support the use of low-swing signaling on the access line (e.g., a relatively small change in the digital line voltage, e.g., depending on the change in the sensed logical state), which may mitigate (e.g., prevent) unintended cross-coupling between adjacent selected access lines, and which may also enable the memory cell to be accurately sensed.

[0049] Memory device 110 may include device memory controller 155 and one or more memory dies 160. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170-N). Memory array 170 may be a collection (e.g., a grid) of memory cells, where each memory cell is configured to store at least one bit of digital data. Refer to Figure 2 Describe the characteristics of memory array 170 and / or memory cells in more detail.

[0050] Memory device 110 may be an instance of a two-dimensional (2D) memory cell array or may be an instance of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-N). In a 3D memory device, a set of memory dies 160-N may be stacked on top of one another or next to one another. In some cases, the memory dies 160-N in a 3D memory device may be referred to as stacks, tiers, levels, or dies. A 3D memory device may include any number of stacked memory dies 160-N (e.g., two high, three high, four high, five high, six high, seven high, eight high). Compared to a single 2D memory device, this may increase the number of memory cells that can be positioned on a substrate, which in turn may reduce production costs or improve the performance of the memory array, or both. In some 3D memory devices, different stacks may share at least one common access line such that some stacks may share at least one of word lines, digit lines, and / or plate lines.

[0051] Device memory controller 155 may include circuitry or components configured to control the operation of memory device 110. Thus, device memory controller 155 may include hardware, firmware, and software that enable memory device 110 to execute commands and may be configured to receive, transmit, or execute commands, data, or control information related to memory device 110. Device memory controller 155 may be configured to communicate with external memory controller 105, the one or more memory dies 160, or processor 120. In some cases, memory device 110 may receive data and / or commands from external memory controller 105. For example, memory device 110 may receive a write command instructing memory device 110 to store certain data on behalf of a component of system 100 (e.g., processor 120), or a read command instructing memory device 110 to provide certain data stored in memory die 160 to a component of system 100 (e.g., processor 120). In some cases, device memory controller 155 may control the operation of memory device 110 described herein in conjunction with local memory controller 165 of memory die 160. Examples of components included in device memory controller 155 and / or local memory controller 165 may include a receiver for demodulating signals received from external memory controller 105, a decoder for modulating and transmitting signals to external memory controller 105, logic, decoders, amplifiers, filters, etc.

[0052] The local memory controller 165 (e.g., local to the memory die 160) can be configured to control the operation of the memory die 160. Additionally, the local memory controller 165 can be configured to communicate (e.g., receive and transmit data and / or commands) with the device memory controller 155. The local memory controller 165 can support the device memory controller 155 in controlling the operation of the memory device 110, as described herein. In some cases, the memory device 110 does not include the device memory controller 155, and the local memory controller 165 or the external memory controller 105 can perform the various functions described herein. Thus, the local memory controller 165 can be configured to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 105 or the processor 120.

[0053] The external memory controller 105 can be configured to enable the communication of information, data, and / or commands between components of the system 100 (e.g., the processor 120) and the memory device 110. The external memory controller 105 can act as a liaison between the components of the system 100 and the memory device 110, such that the components of the system 100 need not be aware of the operational details of the memory device. The components of the system 100 can present requests (e.g., read commands or write commands) to the external memory controller 105 that the external memory controller 105 satisfies. The external memory controller 105 can translate or transpose the communications exchanged between the components of the system 100 and the memory device 110. In some cases, the external memory controller 105 can include a system clock that generates a common (source) system clock signal. In some cases, the external memory controller 105 can include a common data clock that generates a common (source) data clock signal.

[0054] In some cases, the external memory controller 105 or another component of the system 100 or its functionality described herein may be implemented by the processor 120. For example, the external memory controller 105 may be hardware, firmware, software, or some combination thereof implemented by the processor 120 or another component of the system 100. Although the external memory controller 105 is depicted as being external to the memory device 110, in some cases, the external memory controller 105 or its functionality described herein may be implemented by the memory device 110. For example, the external memory controller 105 may be hardware, firmware, software, or some combination thereof implemented by the device memory controller 155 or one or more local memory controllers 165. In some cases, the external memory controller 105 may be distributed across the processor 120 and the memory device 110 such that portions of the external memory controller 105 are implemented by the processor 120 and other portions are implemented by the device memory controller 155 or the local memory controller 165. Similarly, in some cases, one or more functions attributed to the device memory controller 155 or the local memory controller 165 herein may, in some cases, be performed by the external memory controller 105 (separate from or included within the processor 120).

[0055] The components of the system 100 may exchange information with the memory device 110 using multiple channels 115. In some instances, the channels 115 may enable communication between the external memory controller 105 and the memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with the components of the system 100. For example, the channel 115 may include a first terminal that includes one or more pins or pads at the external memory controller 105 and one or more pins or pads at the memory device 110. Pins may be examples of conductive input or output points of the devices of the system 100, and the pins may be configured to act as part of the channel. In some cases, the pins or pads of the terminals may be part of the signal path of the channel 115. Additional signal paths may be coupled to the terminals of the channel to route signals within the components of the system 100. For example, the memory device 110 may include signal paths (e.g., signal paths internal to the memory device 110 or its components, such as signal paths internal to the memory die 160) that route signals from the terminals of the channel 115 to the various components of the memory device 110 (e.g., the device memory controller 155, the memory die 160, the local memory controller 165, the memory array 170).

[0056] Channel 115 (and associated signal paths and terminals) may be dedicated to carrying a particular type of information. In some cases, channel 115 may be an aggregated channel and may thus contain multiple individual channels. For example, data channel 190 may be x4 (e.g., containing four signal paths), x8 (e.g., containing eight signal paths), xl6 (containing sixteen signal paths), etc. Signals transmitted over the channel may use a double data rate (DDR) timing scheme. For example, some symbols of the signal may be recorded on the rising edge of the clock signal, and other symbols of the signal may be recorded on the falling edge of the clock signal. Signals transmitted over the channel may use single data rate (SDR) signaling. For example, for each clock cycle, one symbol of the signal may be recorded.

[0057] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channel 186 may be configured to carry commands between external memory controller 105 and memory device 110, the commands including control information (e.g., address information) associated with the command. For example, CA channel 186 may carry a read command with the address of the desired data. In some cases, CA channel 186 may be recorded on the rising clock signal edge and / or the falling clock signal edge. In some cases, CA channel 186 may include any number of signal paths to decode the address and command data (e.g., eight or nine signal paths).

[0058] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channel 188 may be configured to carry one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between a high state and a low state and to coordinate the actions of external memory controller 105 and memory device 110. In some cases, the clock signal may be a differential output (e.g., CK_t signal and CK_c signal), and the signal paths of CK channel 188 may be configured accordingly. In some cases, the clock signal may be single-ended. CK channel 188 may include any number of signal paths. In some cases, clock signal CK (e.g., CK_t signal and CK_c signal) may provide a timing reference for command and addressing operations of memory device 110 or for other system-wide operations of memory device 110. Thus, clock signal CK may alternatively be referred to as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK may be generated by a system clock, which may include one or more hardware components (e.g., an oscillator, a crystal, logic gates, transistors, etc.).

[0059] In some cases, channel 115 may include one or more data (DQ) channels 190. The data channels 190 may be configured to transfer data and / or control information between the external memory controller 105 and the memory device 110. For example, the data channels 190 may transfer information (e.g., bidirectionally) to be written to the memory device 110 or read from the memory device 110.

[0060] In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may include any number of signal paths.

[0061] Channel 115 may couple the external memory controller 105 and the memory device 110 using a variety of different architectures. Examples of various architectures may include buses, point-to-point connections, crossbars, high-density interposers such as silicon interposers, or channels formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0062] The signals transmitted through channel 115 may be modulated using a variety of different modulation schemes. In some cases, a binary symbol (or binary level) modulation scheme may be used to modulate the signals transmitted between the external memory controller 105 and the memory device 110. The binary symbol modulation scheme may be an example of an M-ary modulation scheme where M equals two. Each symbol of the binary symbol modulation scheme may be configured to represent one bit of digital data (e.g., the symbol may represent a logic 1 or a logic 0). Examples of binary symbol modulation schemes include, but are not limited to, non-return-to-zero (NRZ), unipolar coding, bipolar coding, Manchester encoding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), etc.

[0063] Figure 2 An example of a memory die 200 in accordance with the examples disclosed herein is illustrated. The memory die 200 may be an example of the memory die 160 described with reference to Figure 1 In some cases, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205 that are programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one bit of digital logic (e.g., logic 0 and logic 1) at a time. In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one bit of digital logic (e.g., logic 00, logic 01, logic 10, or logic 11) at a time.

[0064] Memory cell 205 may store a state representing digital data (e.g., a polarization state or a dielectric charge). In a FeRAM architecture, memory cell 205 may include a capacitor that includes a ferroelectric material to store a charge and / or polarization representing a programmable state. In a DRAM architecture, memory cell 205 may include a capacitor that includes a dielectric material to store a charge representing a programmable state.

[0065] Operations such as reading and writing may be performed on memory cell 205 by activating or selecting access lines such as word line 210, digit line 215, and / or plate line 220. In some cases, digit line 215 may also be referred to as a bit line. References to access lines, word lines, digit lines, plate lines, or the like may be used interchangeably without affecting understanding or operation. Activating or selecting word line 210, digit line 215, or plate line 220 may include applying a voltage to the corresponding line.

[0066] Memory die 200 may include access lines (e.g., word line 210, digit line 215, and plate line 220) arranged in a grid pattern. Memory cell 205 may be located at the intersection of word line 210, digit line 215, and / or plate line 220. By biasing word line 210, digit line 215, and plate line 220 (e.g., applying a voltage to word line 210, digit line 215, or plate line 220), a single memory cell 205 may be accessed at their intersection.

[0067] Access to memory cell 205 may be controlled by row decoder 225, column decoder 230, and plate driver 235. For example, row decoder 225 may receive a row address from local memory controller 265 and activate word line 210 based on the received row address. Column decoder 230 receives a column address from local memory controller 265 and activates digit line 215 based on the received column address. Plate driver 235 may receive a plate address from local memory controller 265 and activate plate line 220 based on the received plate address. For example, memory die 200 may include multiple word lines 210 labeled WL_1 to WL_M, multiple digit lines 215 labeled DL_1 to DL_N, and multiple plate lines labeled PL_1 to PL_P, where M, N, and P depend on the size of the memory array. Thus, by activating word line 210, digit line 215, and plate line 220 (e.g., WL_1, DL_3, and PL_1), memory cell 205 may be accessed at their intersection. The intersection of word line 210 and digit line 215 in a two-dimensional or three-dimensional configuration may be referred to as the address of memory cell 205. In some cases, the intersection of word line 210, digit line 215, and plate line 220 may be referred to as the address of memory cell 205.

[0068] In some instances, as described herein, a plate (e.g., plate line 220 coupled to the plate) may be selected (e.g., whose voltage may be increased or decreased). Each plate of the memory array may be associated with a plurality of digit lines 215. In some instances, after the plate is selected, each corresponding digit line may be selected (e.g., simultaneously selected), and the memory cells 205 associated with the selected digit lines may be accessed. As described herein, the presence of one or more shield lines coupled to the selected digit lines and / or the configuration of one or more sense amplifiers (e.g., high-gain sense amplifiers) may support parallel selection of each digit line associated with the plate (and access to one or more associated memory cells). In some instances, the configuration of the shield lines and / or sense amplifiers may reduce any unintended cross-coupling between the selected digit lines 215, which may maintain the integrity of the data read from or written to the selected memory cells 205.

[0069] The memory cell 205 may include logic storage components such as a capacitor 240 and a switching component 245. The capacitor 240 may be an example of a ferroelectric capacitor. A first node of the capacitor 240 may be coupled to the switching component 245, and a second node of the capacitor 240 may be coupled to the plate line 220. The switching component 245 may be an example of a transistor or any other type of switching device that selectively establishes or cancels electronic communication between two components.

[0070] Selecting or deselecting the memory cell 205 may be achieved by activating or deactivating the switching component 245. The capacitor 240 may communicate electronically with the digit line 215 using the switching component 245. For example, when the switching component 245 is deactivated, the capacitor 240 may be isolated from the digit line 215, and when the switching component 245 is activated, the capacitor 240 may be coupled to the digit line 215. In some cases, the switching component 245 is a transistor and its operation is controlled by applying a voltage to the transistor gate, where the voltage difference between the transistor gate and the transistor source may be greater than or less than the threshold voltage of the transistor. In some cases, the switching component 245 may be a p-type transistor or an n-type transistor. The word line 210 may communicate electronically with the gate of the switching component 245 of the memory cell 205, and the switching component 245 may be activated / deactivated based on the voltage applied to the word line 210.

[0071] The word line 210 may be a conductive wire that communicates electronically with the memory cell 205 for performing access operations on the memory cell 205. In some architectures, the word line 210 may communicate electronically with the gate of the switching component 245 of the memory cell 205 and may be configured to control the switching component 245 of the memory cell. In some architectures, the word line 210 may communicate electronically with a node of the capacitor of the memory cell 205, and the memory cell 205 may not include a switching component.

[0072] The digital line 215 can be a conductive line connecting the memory cell 205 and the sensing component 250. In some architectures, the memory cell 205 can be selectively coupled to the digital line 215 during part of an access operation. For example, the word line 210 and the switching component 245 of the memory cell 205 can be configured to selectively couple and / or isolate the capacitor 240 of the memory cell 205 from the digital line 215. In some architectures, the memory cell 205 can be in electronic communication (e.g., constant) with the digital line 215. As described herein, a single board (e.g., a single board line 220) can be coupled to a group of digital lines 215. In some instances, one or more digital lines 215 coupled to the same board can be separated by a shield line. In some instances, the shield line can be or can be referred to as a "dummy" digital line, but unlike the digital line 215, the shield line may not be coupled to any memory cell 205 and can be grounded. Thus, two digital lines can be selected simultaneously, and the shield line can separate two originally adjacent digital lines 215, which can reduce any interference that might otherwise occur between the selected digital lines 215. Additionally or alternatively, as described herein, one or more digital lines 215 (e.g., one or more selected digital lines 215) can be coupled to corresponding sense amplifiers (e.g., as described with reference to Figure 8 and 9 ). In some instances, each sense amplifier can be configured to be coupled to the selected digital lines 215 of the board during an access operation.

[0073] The board line 220 can be a conductive line in electronic communication with the memory cell 205 for performing an access operation on the memory cell 205. The board line 220 can be in electronic communication with a node (e.g., the bottom of the cell) of the capacitor 240. The board line 220 can be configured to cooperate with the digital line 215 to bias the capacitor 240 during an access operation of the memory cell 205. As described with reference to Figure 5 , a memory device can include blocks, and the blocks can include a group of boards. In some instances, the boards within a block can be grouped into any number of board groups (e.g., units, sets of boards). Each board group can include a group of boards, and each board can be associated with a group of columns of the memory cells 205 and thus with a group of digital lines. For example, a block can include ten (10) units, and each unit can include thirty-two (32) boards. Each board can be associated with eight (8) digital lines 215. In some cases, within each board group, as part of an access operation (e.g., a read or write operation), one board can be activated (selected, access the memory cells coupled thereto), e.g., multiple boards within a block can be activated in parallel, but each parallel-activated board can be in a different board group, and one board is activated in each board group.

[0074] The sensing component 250 can be configured to determine the state (e.g., polarization state or charge) stored on the capacitor 240 of the memory cell 205, and determine the logical state of the memory cell 205 based on the detected state. In some cases, the charge stored by the memory cell 205 may be extremely small. Thus, the sensing component 250 can include one or more sense amplifiers to amplify the signal output of the memory cell 205. The sense amplifier can detect a small change in the charge of the digit line 215 during a read operation, and can generate a signal corresponding to a logic 0 or a logic 1 based on the detected charge. During a read operation, the capacitor 240 of the memory cell 205 can output (e.g., discharge) a signal to its corresponding digit line 215. The signal can cause a change in the voltage of the digit line 215. The sensing component 250 can be configured to compare the signal received from the memory cell 205 across the digit line 215 with a reference signal 255 (e.g., a reference voltage). The sensing component 250 can determine the stored state of the memory cell 205 based on the comparison. For example, in binary signaling, if the digit line 215 has a higher voltage than the reference signal 255, the sensing component 250 can determine that the stored state of the memory cell 205 is a logic 1, and if the digit line 215 has a lower voltage than the reference signal 255, the sensing component 250 can determine that the stored state of the memory cell 205 is a logic 0. The sensing component 250 can include various transistors or amplifiers to detect and amplify differences in the signal. The detected logical state of the memory cell 205 can be provided as an output of the sensing component 250 (e.g., provided to the input / output 260), and can indicate the detected logical state (e.g., directly or using the local memory controller 265) to another component of the memory device 110 that includes the memory die 200 (e.g., the device memory controller 155). In some cases, the sensing component 250 can communicate electronically with the row decoder 225, the column decoder 230, and / or the bank driver 235.

[0075] As described herein, a memory device can include one or more sensing components configured to sense one or more memory cells 205 when a set of adjacent digit lines 215 is selected. For example, each digit line 215 associated with a bank (e.g., the bank line 220) can be selected simultaneously. Each selected digit line 215 can be coupled to a corresponding sense amplifier included in the sensing component 250. In some instances, each sense amplifier can be configured to sense a smaller change in the voltage value of the digit line 215 (e.g., configured to support the use of lower swing signaling on the digit line). In some instances, each sense amplifier can be configured to sense one or more memory cells 205 associated with the selected digit line 215 while reducing or eliminating any signal interference (e.g., crosstalk).

[0076] The local memory controller 265 can control the operation of the memory cells 205 through various components (e.g., the row decoder 225, the column decoder 230, the bank driver 235, and the sense component 250). The local memory controller 265 can be an instance of the local memory controller 165 described in reference Figure 1 In some cases, one or more of the row decoder 225, the column decoder 230, the bank driver 235, and the sense component 250 may be in the same location as the local memory controller 265. The local memory controller 265 can be configured to receive one or more commands and / or data from the external memory controller 105 (or the device memory controller 155 described in reference Figure 1 ), translate the commands and / or data into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and transfer data from the memory die 200 to the external memory controller 105 (or the device memory controller 155) in response to performing one or more operations. The local memory controller 265 can generate row, column, and / or bank line address signals to activate the target word line 210, the target digit line 215, and the target bank line 220. The local memory controller 265 can also generate and control various voltages or currents used during the operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein can be adjusted or varied and can be different for the various operations discussed when operating the memory die 200.

[0077] In some cases, the local memory controller 265 can be configured to perform a precharge operation on the memory die 200. The precharge operation can include precharging one or more components and / or access lines of the memory die 200 to one or more predetermined voltage levels. In some cases, the memory cells 205 and / or portions of the memory die 200 can be precharged between different access operations. In some cases, the digit lines 215 and / or other components can be precharged before a read operation.

[0078] In some cases, the local memory controller 265 may be configured to perform a write operation (e.g., a programming operation) on one or more memory cells 205 of the memory die 200. During the write operation, the memory cells 205 of the memory die 200 may be programmed to store the desired logical state. In some cases, a group of memory cells 205 may be programmed during a single write operation. The local memory controller 265 may identify the target memory cells 205 on which the write operation will be performed. The local memory controller 265 may identify the target word line 210, the target digit line 215, and / or the target plate line 220 that are in electronic communication with the target memory cells 205 (e.g., the address of the target memory cells 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., by applying a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cells 205. The local memory controller 265 may apply a specific signal (e.g., a voltage) to the digit line 215 and a specific signal (e.g., a voltage) to the plate line 220 during the write operation to store a specific state in the capacitor 240 of the memory cell 205, the specific state indicating the desired logical state. In some instances, as described herein, the write operation may occur on one or more memory cells 205 associated with a plate (e.g., the plate line 220) for which each of its digit lines 215 has been selected. That is, each digit line 215 associated with a plate (e.g., the plate line 220) may be selected simultaneously, and the write operation may occur on one or more memory cells 205 associated with the selected digit lines.

[0079] In some cases, the local memory controller 265 may be configured to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cell 205 of the memory die 200 may be determined. In some cases, a group of memory cells 205 may be sensed during a single read operation. The local memory controller 265 may identify the target memory cell 205 on which the read operation will be performed. The local memory controller 265 may identify the target word line 210, the target digit line 215, and / or the target plate line 220 that is in electronic communication with the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 265 may activate the target word line 210, the target digit line 215, and / or the target plate line 220 (e.g., by applying a voltage to the word line 210, the digit line 215, or the plate line 220) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sense component 250 in response to the biased access lines. The sense component 250 may amplify the signal. The local memory controller 265 may trigger the sense component 250 (e.g., latch the sense component) and thereby compare the signal received from the memory cell 205 with the reference signal 255. Based on the comparison, the sense component 250 may determine the logical state stored on the memory cell 205. As part of the read operation, the local memory controller 265 may transmit the logical state stored on the memory cell 205 to the external memory controller 105 (or the device memory controller). In some instances, as described herein, a read operation may occur on one or more memory cells 205 associated with a plate when each of the digit lines 215 corresponding to the plate (e.g., the plate line 220) is selected. That is, each digit line 215 associated with a plate (e.g., the plate line 220) may be selected simultaneously, and a read operation may occur on one or more memory cells 205 associated with the selected digit lines.

[0080] In some memory architectures, accessing a memory cell 205 may degrade or corrupt the logical state stored in the memory cell 205. For example, a read operation performed on a ferroelectric memory cell may corrupt the logical state stored in the ferroelectric capacitor. In another example, a read operation performed in a DRAM architecture may partially or fully discharge the capacitor of the target memory cell. The local memory controller 265 may perform a rewrite operation or a refresh operation to return the memory cell to its original logical state. The local memory controller 265 may rewrite the logical state to the target memory cell after a read operation. In some cases, the rewrite operation may be considered part of the read operation. Additionally, activating a single access line (e.g., word line 210) may disturb the states stored in some memory cells that are in electronic communication with the access line. Accordingly, a rewrite operation or a refresh operation may be performed on one or more memory cells that may not have been accessed.

[0081] Figure 3A and 3B Examples are described that illustrate the non-linear electrical properties of ferroelectric memory cells having hysteresis curves 300-a and 300-b in accordance with various examples disclosed herein. Hysteresis curves 300-a and 300-b illustrate the write and read processes of example ferroelectric memory cells, respectively. Hysteresis curves 300-a and 300-b depict the charge Q that varies with the voltage difference V stored on a ferroelectric capacitor (e.g., capacitor 240 described with reference to Figure 2 the capacitor 240).

[0082] Ferroelectric materials are characterized by spontaneous polarization, i.e., they maintain a non-zero electric polarization in the absence of an electric field. Example ferroelectric materials include barium titanate (BaTiO3), lead titanate (PbTiO3), lead zirconate titanate (PZT), and strontium bismuth tantalate (SBT). The ferroelectric capacitors described herein may include these or other ferroelectric materials. The electric polarization within a ferroelectric capacitor creates a net charge at the surface of the ferroelectric material and attracts opposite charges through the capacitor terminals. Accordingly, charge is stored at the interface between the ferroelectric material and the capacitor terminals. Because the electric polarization can be maintained for a relatively long time, even indefinitely, in the absence of an externally applied electric field, charge leakage can be significantly reduced compared to capacitors employed in, for example, DRAM arrays. This can reduce the need to perform refresh operations.

[0083] The hysteresis curves 300-a and 300-b can be understood from the perspective of a single terminal of the capacitor. By way of example, if the ferroelectric material has a negative polarization, positive charges accumulate at the terminal. Similarly, if the ferroelectric material has a positive polarization, negative charges accumulate at the terminal. Additionally, the voltage in the hysteresis curves 300-a and 300-b represents the voltage difference across the capacitor and is directional. For example, a positive voltage can be achieved by applying a positive voltage to the relevant terminal (e.g., the cell plate) and maintaining the second terminal (e.g., the cell bottom) at ground (or approximately zero volts (0V)). A negative voltage can be applied by maintaining the relevant terminal at ground and applying a positive voltage to the second terminal, i.e., a positive voltage can be applied to negatively polarize the relevant terminal. Similarly, two positive voltages, two negative voltages, or any combination of positive and negative voltages can be applied to the appropriate capacitor terminals to generate the voltage differences shown in the hysteresis curves 300-a and 300-b.

[0084] As depicted in the hysteresis curve 300-a, the ferroelectric material can maintain a positive or negative polarization at zero pressure difference, resulting in two possible charged states: charge state 305 and charge state 310. According to Figure 3A and 3B example, charge state 305 represents logic 0 and charge state 310 represents logic 1. In some examples, the logic values of the corresponding charge states can be reversed to accommodate other schemes for operating memory cells.

[0085] By applying a voltage to control the polarization of the ferroelectric material and thus the charge on the capacitor terminals, a logic 0 or 1 can be written to the memory cell. For example, applying a net positive voltage 315 across the capacitor causes charge accumulation until charge state 305-a is reached. After removing voltage 315, charge state 305-a follows path 320 until it reaches charge state 305 at zero voltage. Similarly, charge state 310 is written by applying a net negative voltage 325, which produces charge state 310-a. After removing the negative voltage 325, charge state 310-a follows path 330 until it reaches charge state 310 at zero voltage. Charge states 305-a and 310-a can also be referred to as remanent polarization (Pr) values, i.e., the polarization (or charge) remaining after removing an external bias (e.g., voltage). The coercive voltage is the voltage at which the charge (or polarization) is zero.

[0086] To read or sense the stored state of a ferroelectric capacitor, a voltage can be applied across the capacitor. In response, the stored charge Q changes, and the degree of change depends on the initial charge state, i.e., the final stored charge (Q) depends on whether the initial stored charge state is 305-b or 310-b. For example, the hysteresis curve 300-b illustrates two possible stored charge states 305-b and 310-b. A voltage 335 can be applied across the capacitor 240 as discussed with reference to Figure 2 FIG. In other cases, a fixed voltage can be applied to the cell plate, and although depicted as a positive voltage, the voltage 335 can be negative. In response to the voltage 335, the charge state 305-b can follow path 340. Similarly, if the initial stored charge state is 310-b, it follows path 345. The final positions of the charge states 305-c and 310-c depend on one or more factors, including the specific sensing scheme and circuitry.

[0087] In some cases, the final charge can depend on the intrinsic capacitance of the digital line connected to the memory cell. For example, if the capacitor is electrically connected to the digital line and a voltage 335 is applied, the voltage of the digital line can rise due to its intrinsic capacitance. The voltage measured at the sensing component may not be equal to the voltage 335 and may actually depend on the voltage of the digital line. Therefore, the positions of the final charge states 305-c and 310-c on the hysteresis curve 300-b can depend on the capacitance of the digital line and can be determined by load line analysis, i.e., the charge states 305-c and 310-c can be defined relative to the digital line capacitance. Therefore, the voltage of the capacitor, voltage 350 or voltage 355, can be different and can depend on the initial state of the capacitor.

[0088] By comparing the digital line voltage with a reference voltage, the initial state of the capacitor can be determined. The digital line voltage can be the difference between the voltage 335 and the final voltage across the capacitor (voltage 350 or voltage 355), i.e., the difference between voltage 335 and voltage 350 or the difference between voltage 335 and voltage 355. A reference voltage can be generated such that its magnitude is between the two possible voltages of the two possible digital line voltages to determine the stored logical state, i.e., whether the digital line voltage is higher or lower than the reference voltage. After being compared by the sensing component, the sensed digital line voltage can be determined to be higher or lower than the reference voltage, and the stored logical value (i.e., logical 0 or 1) of the ferroelectric memory cell can be determined.

[0089] In some cases, a ferroelectric memory cell may maintain its initial logic state after a read operation. For example, if charge state 305-b is stored, the charge state may follow path 340 to charge state 305-c during the read operation, and after removing voltage 335, the charge state may return to the initial charge state 305-b by following path 340 in the opposite direction. In some cases, a ferroelectric memory cell may lose its initial logic state after a read operation. For example, if charge state 310-b is stored, the charge state may follow path 345 to charge state 305-c during the read operation, and after removing voltage 335, the charge state may relax to the initial charge state 305-b by following path 340.

[0090] Hysteresis curve 300-b illustrates an example of reading a memory cell configured to store charge state 305-b and charge state 310-b. For example, a read voltage 335 as a voltage difference may be applied via the digital line 215 and the plate line 220 described in reference Figure 2 The hysteresis curve 300-b may illustrate a read operation in which the read voltage 335 is a negative voltage difference Vcap (e.g., where Vbottom-Vplate is negative). A negative read voltage across the capacitor may be referred to as a "plate high" read operation, where the plate line 220 is initially at a high voltage and the digital line 215 is initially at a low voltage (e.g., ground voltage). Although the read voltage 335 is shown as a negative voltage across the ferroelectric capacitor 240, in an alternative operation, the read voltage may be a positive voltage across the ferroelectric capacitor 240, which may be referred to as a "plate low" read operation.

[0091] When a memory cell 205 is selected (e.g., by activating a switch component 245 as described in reference Figure 2 ), the read voltage 335 may be applied across the ferroelectric capacitor 240. After applying the read voltage 335 to the ferroelectric capacitor 240, charge may flow into or out of the ferroelectric capacitor 240 via the digital line 215 and the plate line 220, and different charge states may be generated depending on whether the ferroelectric capacitor 240 is in charge state 305-a (e.g., logic 1) or in charge state 310-a (e.g., logic 0).

[0092] Figure 4 An example of a memory array 400 including a common plate supporting digital line management for a memory array is illustrated in accordance with an example disclosed herein. In some examples, the memory array 400 may be or may represent a portion of a larger memory array. As described in reference Figure 4As shown, the memory array can include a plate 405, a set of memory cells (e.g., including memory cell 410 and memory cell 410-a), a set of word lines (e.g., including word line 425, word line 425-a, and word line 425-b), a set of digit lines (e.g., including digit line 430, digit line 430-a, and digit line 430-b), and a plate line 435. In some instances, each memory cell can include a transistor or other selector device (e.g., transistor 420 of memory cell 410) and a capacitor (e.g., capacitor 415 of memory cell 410). Additionally or alternatively, the memory array 400 can include a plate line 435 coupled to the plate 405, and can also include one or more shield lines (not shown).

[0093] As described herein, a memory cell can be located at the intersection of a word line and a digit line. For example, memory cell 410 can be located at the intersection of word line 425 and digit line 430. Memory cell 410 can include a logic storage component, such as capacitor 415 and transistor 420 (e.g., a switch or selector component). Capacitor 415 can be an example of a ferroelectric capacitor. A first node of capacitor 415 can be coupled to transistor 420, and a second node of capacitor 415 can be coupled to plate 405. To access memory cell 410, plate 405, digit line 430, and word line 425 can be selected (e.g., by adjusting the respective voltages of plate 405, digit line 430, and word line 425). In some instances, plate 405 can be selected by applying a voltage to plate 405 via plate line 435.

[0094] In some instances, plate 405 is shared for a set of memory cells. That is, plate 405 is shared for at least memory cell 410 and memory cell 410-a. As referenced Figure 5 as described, plate 405 can be or can represent a single plate included in a cell (e.g., a plate group including a set of plates), and each cell can be included in a block (e.g., a block that can also be referred to as a shard, or other array sub-segment including multiple plate groups). In some instances, plate 405 can be located above each of a set of memory cells in the memory array 400. In other words, each memory cell of the memory array 400 can be located below plate 405 (e.g., below plate 405 shared by each memory cell). In other instances, plate 405 can be located below each of a set of memory cells in the memory array 400, and each memory cell of the memory array 400 can be located above plate 405 (e.g., above plate 405 shared by each memory cell).

[0095] To access the memory cells of a memory array, corresponding voltages may be applied to the plate 405, to the digit lines, and to the word lines. For example, to access memory cell 410, corresponding voltages may be applied to the plate 405, to the digit line 430, and to the word line 425 (via the plate line 435). In some instances, applying a voltage to the digit line 430 may be referred to as selecting the digit line 430. However, a memory cell may be accessed only when the corresponding word line (e.g., word line 425) is also selected, which may cause a voltage to be applied to the gates of the transistors (select devices) of each memory cell coupled to the digit line 430.

[0096] In some instances, it may be advantageous to mitigate unintentional interference between adjacent selected lines. For example, selecting digit line 430 and digit line 430-a in parallel may create a risk of cross-coupling between the selected digit lines and, thus, may create a risk of unwanted data corruption. However, as described herein, one or more shield lines may be located between the digit lines of the memory array (e.g., between digit line 430 and digit line 430-a, and between digit line 430-a and digit line 430-b), such that the cross-coupling effect may be mitigated and each digit line may be selected in parallel without an unwanted performance impact. Selecting each digit line in parallel may also allow the memory array to consume less power (e.g., by allowing the plate 405 to correspond only to the number of digit lines that need to be selected in parallel for one or more access operations and, thus, allowing a reduction in the physical size of the plate 405 compared to some memory architectures in which only a subset of the corresponding digit lines are selected for a selected plate). Additionally, the sensing schemes and crosstalk mitigation techniques described herein may allow for faster access (e.g., read or write) operations (e.g., by allowing an increase in the transition rate of the plate and digit line voltages).

[0097] Figure 5 An example of a memory array 500 that supports digit line management for a memory array in accordance with examples disclosed herein is illustrated. As shown in reference Figure 5 The memory array may include blocks 505, which may include a set of cells 515 (e.g., cells 515-a to 515-j). In some instances, each cell 515 may include a set of plates 520 that may be referred to as a plate group. For example, cell 515-a may include a set of plates, including plate 520-a. Each of the plates 520 may be as described in reference Figure 4An example of the described plate 405. That is, each plate 520 may be coupled to a set of memory cells including a set of rows and columns (e.g., shared for multiple memory cells), each row being coupled to a corresponding word line and each column being coupled to a corresponding digit line. In some examples, the memory array 500 may include word lines 510, such as word line 510-a, which may span multiple plates 520 and multiple plate groups 515 (e.g., may be coupled to memory cells associated with multiple plates in multiple plate groups).

[0098] The memory cells coupled to the plate 520 may include any number of columns, and thus each plate 520 may be associated with any number of digit lines. Each digit line associated with a selected plate may be configured to be selected in parallel (e.g., simultaneously) during an access operation. To access a set of memory cells associated with a particular plate, the plate may be selected by applying a voltage to a plate line coupled to the plate 520 (e.g., refer to Figure 4 the described plate line 435). The voltage of the plate 520 may be increased (e.g., the plate may be taken as "high"), and each of the digit lines associated with the plate 520 may be selected in parallel. Subsequently, a particular word line 510 may be selected, and the memory cells at the intersection of the selected digit lines and the selected word line 510 may be accessed in parallel (e.g., if eight (8) digit lines correspond to the selected plate 520, eight (8) memory cells may be accessed in parallel by selecting the plate 520 coupled to the eight (8) memory cells, all eight (8) corresponding digit lines, and the word line 510).

[0099] As referred to Figure 4 it may be advantageous to mitigate any interference (e.g., crosstalk) caused by neighboring digit lines being selected. Thus, in some examples, as seen in Figure 6 the described, one or more shield lines may be employed in the memory array to mitigate such electrical interference. In some examples, the shield line may be or may include a grounded segment (e.g., a metal segment) that "shields" neighboring access lines (e.g., neighboring digit lines) (e.g., electrically isolates neighboring access lines from each other, is located between neighboring access lines, separates neighboring access lines). Thus, the presence of the shield line may allow each digit line associated with a common plate (e.g., plate 520-a) to be selected simultaneously during an access operation with reduced crosstalk, thereby enabling parallel selection of multiple memory cells with reduced crosstalk and other interference.

[0100] In some instances, the memory array 500 may further include a set of multiplexing components (e.g., multiplexing components 525-a through 525-j), each coupled to a corresponding cell (e.g., to each board group, respectively) and to a corresponding set of sense amplifiers (e.g., to one of a set of sense amplifiers 530-a through 530-j). In some instances, each multiplexing component (e.g., multiplexing component 525-a) may be configured to couple all of the digital lines of a selected board 520 in parallel to different sense amplifiers within the corresponding set of sense amplifiers (e.g., one of a set of sense amplifiers 530-a through 530-j) that correspond to the board group 515 that includes the selected board 520.

[0101] In some instances, each multiplexing component (e.g., multiplexing component 525-a) may include any number and arrangement of individual multiplexers. For example, multiplexing component 525-a may include a cascaded network of multiplexers. For example, using an example number for illustrative clarity only, one or more multiplexers may be configured as a 32:1 multiplexer with an 8-wide bus as both the input and output. For example, multiplexing component 525-a may include a set of four (4) 8:1 multiplexers in parallel with each other and a 4:1 multiplexer in series with the set of 8:1 multiplexers, where each multiplexer has an 8-wide bus as both the input and output, where the set of 8:1 multiplexers is configured to route (couple) all eight (8) digital lines of a selected board 520 within a cell 515 that includes thirty-two (32) boards to the 4:1 multiplexer, and where the 4:1 multiplexer is configured to route (couple) all eight (8) digital lines of a selected board 520 in a corresponding manner to eight (8) sense amplifiers included within a set of sense amplifiers 530 that corresponds to cell 515.

[0102] For example, and using the number of instances for illustrative purposes only, eight (8) sense amplifiers (e.g., as included in respective groups of sense amplifiers 530) may be coupled to each multiplexing component 525. Thus, one plate from each cell 515 may be selected in parallel (e.g., each of plates 520-a to 520-j may be selected). In parallel, for each selected plate 520 that may be associated with eight (8) digital lines: each of the eight (8) associated digital lines may be selected in parallel, and a respective multiplexing component (e.g., one multiplexing component 525) may couple each of the eight (8) selected digital lines to a respective sense amplifier within the respective group of sense amplifiers 530. Thus, in some instances, when each of plates 520-a to 520-j is selected, eighty (80) digital lines may be selected in parallel and may be respectively coupled in a 1:1 relationship to eighty (80) sense amplifiers collectively included in ten (10) illustrated groups of sense amplifiers 530.

[0103] Figure 6 Illustrate an example of a memory array 600 including a selected plate that supports digital line management for a memory array in accordance with the examples disclosed herein. In some instances, the memory array 600 may include a plate 605 (e.g., a selected plate) that may be an example of the plate 520 described in the reference Figure 5 That is, the plate 605 may be or may represent one of a set of plates associated with a single cell (e.g., a single plate group). In some instances, the cell may be one of a set of cells of a single block (e.g., the block 505 described in the reference Figure 5 That is described). In some instances, the plate 605 may correspond to a set of digital lines 610 (e.g., digital lines 610-a to 610-e), a set of word lines (e.g., word lines 615-a to 615-d), and a set of shield lines (e.g., shield lines 620-a to 620-f). In some instances, each digital line 610 may be coupled to a multiplexing component 635 corresponding to the cell and, thus, may be coupled (capable of being coupled) to a respective sense amplifier 640 within a group of sense amplifiers 655 corresponding to the cell. The multiplexing component 635 may be an example of the multiplexing component 525, and the group of sense amplifiers 655 may be an example of the group of sense amplifiers 530 described in the reference Figure 5 That is described. Each respective sense amplifier 640 may be configured to sense a memory cell when a digital line associated with the plate 605 is selected and is coupled to the sense amplifier 640.

[0104] As described herein, a set of memory cells can share a board (e.g., board 605), and each digit line associated with the board can be selected in parallel. For example, board 605 can be selected (e.g., by applying a voltage to a board line (not shown) coupled to board 605), which can cause the voltage across board 605 to increase. In some instances, each (all) digit lines corresponding to board 605 can be selected (e.g., digit lines 610-a to 610-e). Each of the digit lines can be selected simultaneously (e.g., in parallel, at the same time, for the same duration). To access a set of memory cells associated with board 605, a word line can be activated. For example, a first memory cell 645 (e.g., a first ferroelectric memory cell) can be located at the intersection of word line 615-a and digit line 610-d (e.g., the first digit line), and a second memory cell 650 (e.g., a second ferroelectric memory cell) can be located at the intersection of word line 615-a and digit line 610-e (e.g., the second digit line).

[0105] Because each digit line associated with board 605 can be selected during an access operation, the first memory cell 645 (e.g., in addition to various other memory cells associated with memory array 600) and the second memory cell 650 can be accessed (e.g., in parallel) by selecting word line 615-a. Thus, in some instances, an access operation can be performed on the first ferroelectric memory cell when the second digit line is selected. In other words, data can be written to or read from the first ferroelectric memory cell 645 when the digit line associated with the second ferroelectric memory cell 650 is selected (e.g., when digit line 610-a is activated). In some instances, other memory cells associated with memory array 600 can also be accessed while the first memory cell 645 and the second memory cell 650 are being accessed. For example, memory cells located at the intersection of the respective digit lines and word line 615-a can be accessed while the first memory cell 645 and the second memory cell 650 are being accessed (e.g., because each digit line of board 605 is selected).

[0106] In some instances, a memory array can include one or more boards that are not selected during an access operation. For example, board 605 can be selected while one or more boards (e.g., one or more boards that are the same or similar to board 605) are not selected. In some instances, corresponding board signal lines 630 can be used to bias each unselected board. The unselected boards can be coupled (e.g., shunted) to one or more corresponding digit lines (e.g., unselected digit lines). Biasing the unselected digit lines and the unselected boards at the same voltage (e.g., by shunting them together) can mitigate any unintended electrical interference to the associated memory cells.

[0107] As described herein, when adjacent access lines are selected, unexpected electrical interference (e.g., cross-coupling) may occur. However, the presence of shield lines (e.g., shield lines 620-a to 620-f) can mitigate (e.g., cancel, resist) such effects. For example, shield line 620-a can cancel such effects between digital line 610-a and digital line 610-b, shield line 620-b can cancel such effects between digital line 610-b and digital line 610-c, shield line 620-c can cancel such effects between digital line 610-c and digital line 610-d, and shield line 620-e can cancel such effects between digital line 610-d and digital line 610-e. In some instances, each of the shield lines can be coupled to a voltage sink 625 (e.g., ground) to shield the selected digital lines from each other.

[0108] Accordingly, during an access operation of memory cell 645, shield line 620-e can prevent unexpected data corruption due to the parallel selection of digital line 610-e. In other words, the presence of shield line 620-e can allow data to be written to or read from memory cell 645 without disturbing adjacent selected digital line 610-e. Each of the first memory cell 645 and the second memory cell 650 can be sensed in parallel. For example, shield line 620-e can allow a first signal to be transmitted to or from the first memory cell 645 (e.g., along digital line 610-d). When the first signal is transmitted, a second signal can be transmitted to or from the second memory cell 650 (e.g., along digital line 610-e). As discussed herein, the grounded shield line 620-e can prevent data read from or written to the first memory cell 645 and the second memory cell 650 from being corrupted.

[0109] In some instances, board 605 can be coupled to a multiplexing component 635, which is coupled to a corresponding plurality (a set) of sense amplifiers 655. The corresponding plurality (a set) of sense amplifiers 655 can include a plurality (a set) of sense amplifiers 640, which are thus coupled to the multiplexing component 635. Accordingly, the multiplexing component 635 can couple each activated digital line to a corresponding sense amplifier 640 within the corresponding plurality (a set) of sense amplifiers 655. Accordingly, in some instances, memory cells associated with each of the selected digital lines (e.g., digital lines 610-a to digital line 610-e) can be accessed in parallel.

[0110] As Figure 6As shown, the plate 605 can correspond to any number of digital lines. For example, the plate can correspond to eight (8) digital lines, and each digital line can be separated (e.g., isolated) by a respective ground conductive wire (e.g., via a shield wire). However, in other instances, the plate can correspond to any number of digital lines, and any combination of digital lines can be isolated from each other by shield wires. Additionally or alternatively, the plate can correspond to any number of multiplexing components and / or sense amplifiers that allow the memory cells associated with selected digital lines to be sensed in parallel (e.g., simultaneously).

[0111] Figure 7A An example of a memory array 700-a that supports digital line management for a memory array according to the examples disclosed herein is illustrated. In some examples, the memory array 700-a can illustrate the location of one or more shield wires (e.g., shield wire 710-a, shield wire 710-b) configured to isolate one or more digital lines that can be selected in parallel (e.g., isolate digital line 705-a from digital line 705-b). Thus, the memory array 700-a can include digital lines 705-a, 705-b, and 705-c, each of which is coupled to a memory cell (e.g., to a transistor included in the memory cell, such as a transistor including a selection device for the memory cell). For example, digital line 705-a can be coupled to transistor 715-a (e.g., the source of transistor 715-a), digital line 705-b can be coupled to transistor 715-b (e.g., the source of transistor 715-b), and digital line 705-c can be coupled to transistor 715-c (e.g., the source of transistor 715-c). In some cases, each transistor 715 (e.g., the drain of each transistor) can be coupled to a respective capacitor (e.g., capacitors 720-a to 720-c), which can be a storage element within the memory cell that includes the transistor, such as a ferroelectric capacitor. In some examples, each transistor 715 can include a respective channel region (e.g., channel regions 725-a, 725-b, and 725-c).

[0112] As described herein, during an access operation, each digital line of a common plate can be selected. In Figure 7AIn the example shown, each of digital lines 705-a, 705-b, and 705-c can be selected during an access operation. To perform an access operation on one or more memory cells associated with a selected digital line of a memory array, a corresponding word line can be selected. In some examples, the word line can be coupled to the gate of each transistor 715 (e.g., transistor 715-a, transistor 715-b, and transistor 715-c). Thus, by selecting the word line (e.g., by applying a voltage to the gate of a particular transistor), the memory cells at the intersection of the selected digital line and the selected word line can be accessed. In some examples, multiple (e.g., each) memory cells associated with a common plate can be accessed simultaneously during an access operation.

[0113] In some examples, shield lines can be located between each digital line in a memory array (e.g., adjacent to the digital lines). For example, shield line 710-a can be located between digital line 705-a and digital line 705-b. Additionally or alternatively, shield line 710-b can be located between digital line 705-b and digital line 705-c. By placing shield lines between each digital line of a plate, each digital line of the plate can be selected in parallel and crosstalk or other interference is reduced. For example, each shield line can be grounded, and the voltages (e.g., signals) across each digital line can shield each other. Thus, each digital line can be selected simultaneously without electrical interference affecting the data read from or written to the memory cells.

[0114] In some examples, each shield line 710 can be or can be referred to as a conductive line or a metal line. As described with reference to Figure 6 each shield line 710 can be connected to a zero voltage source or other voltage receiver (e.g., each line can be grounded). The shield line 710 can extend in the same plane as the digital line 705, i.e., each shield line can extend parallel to each digital line such that each digital line is shielded from adjacent (e.g., immediately adjacent) digital lines along its entire length. In other examples, one or more shield lines 710 can be located between portions of adjacent digital lines 705. In any case, the shield line 710 can be used to electrically isolate the signals transmitted along any digital line 705 along a common plate.

[0115] Figure 7BIllustrate an example of a memory array 700-b that supports digital line management for a memory array according to the examples disclosed herein. In some examples, the memory array 700-b may illustrate the location of one or more shield lines (e.g., shield line 710-c) configured to isolate one or more digital lines that may be selected in parallel (e.g., isolate digital line 705-e from digital line 705-f). Thus, the memory array 700-b may include digital lines 705-e and 705-f, each coupled to a memory cell (e.g., to a transistor included in the memory cell, e.g., a transistor including a selection device for the memory cell). For example, digital line 705-e may be coupled to transistor 715-e (e.g., the source of transistor 715-e), and digital line 705-f may be coupled to transistor 715-f (e.g., the source of transistor 715-f). In some examples, each transistor (e.g., the drain of each transistor) may be coupled to a corresponding capacitor (e.g., capacitors 720-d to 720-f), which may be a storage element within the memory cell that includes the transistor, such as a ferroelectric capacitor. In some examples, each transistor 715 may include a corresponding channel region (e.g., channel regions 725-d, 725-e, and 725-f).

[0116] As described herein, during an access operation, each digital line of a common plate may be selected. In Figure 7B the example shown, at least digital lines 705-e and 705-f may be selected during an access operation. To perform an access operation on one or more memory cells associated with the selected digital lines, a corresponding word line may be selected. In some examples, the word line may be coupled to the gate of each transistor 715 (e.g., transistor 715-d, transistor 715-e, and transistor 715-f). Thus, by selecting the word line (e.g., by applying a voltage to the gate of a particular transistor), the memory cell at the intersection of the selected digital line and the selected word line may be accessed.

[0117] In some instances, a shield line may be positioned between a subset of digit lines in a memory array (e.g., adjacent to the subset of digit lines). For example, shield line 710-c may be positioned between digit line 705-e and digit line 705-f. By design choice, the shield lines may be positioned between some (but not all) of the digit lines of a common board. This may allow each digit line of the board to be selected in parallel, but may allow access to a particular memory cell only when the risk of electrical interference is reduced. For example, due to shield line 710-c being positioned between digit line 705-e and digit line 705-f, a memory cell located at the intersection of digit line 705-f and a related word line (e.g., coupled to a gate of a transistor) may be accessed, and thus, in some instances, only digit lines 705 between which there is at least one shield line 710 may be selected (e.g., every other digit line 705 may be selected). For example, due to the presence of shield line 710-c, data transmitted along digit line 705-f may not be affected by a voltage across digit line 705-e (e.g., due to digit line 705-e being selected). In some instances, shield line 710-c may be grounded, and voltages (e.g., signals) across digit line 705-e and digit line 705-f may shield each other.

[0118] In some instances, each shield line 710 may be or may be referred to as a conductive line or a metal line, and may be positioned between any combination of digit lines 705. For example, any two digit lines 705 in a memory array may be separated by a shield line 710. As referenced Figure 6 as described, each shield line 710 may be connected to a zero voltage source or other voltage receiver (e.g., each line may be grounded). The shield lines 710 may extend in the same plane as the digit lines 705, i.e., each shield line may extend parallel to each digit line such that each digit line is shielded from an adjacent (e.g., immediately adjacent) digit line over its entire length. In other instances, one or more shield lines 710 may be positioned between portions of adjacent digit lines 705. In any case, the shield lines 710 may be used to electrically isolate signals transmitted along any digit line 705 of a common board.

[0119] Figure 8 Illustrate an example of a memory array 800 including a selected board that supports digit line management for a memory array in accordance with examples disclosed herein. In some instances, memory array 800 may include a board 805 (e.g., the selected board), which may be an example of board 520 as referenced Figure 5 as described. That is, board 805 may be or may represent one of a group of boards associated with a single unit (e.g., a single board group). In some instances, the unit may be a single block (e.g., referenced Figure 5One of a group of cells of the described block 505). In some instances, the plate 805 may correspond to a group of digit lines 810 (e.g., digit lines 810-a to 810-e) and a group of word lines (e.g., word lines 815-a to 815-d). In other instances, the memory array 800 may include one or more mask lines (not shown), as described with reference to Figure 6 and 7. In some instances, each digit line 810 may be coupled to a multiplexing component 825 corresponding to the cell and may thus be coupled to a respective sense amplifier 830 within a group of sense amplifiers 835 corresponding to the cell. The multiplexing component 825 may be an instance of the multiplexing component 525, and the group of sense amplifiers 835 may be an instance of the group of sense amplifiers 530 described with reference to Figure 5 Each sense amplifier 830 may be configured to sense one memory cell when the digit line associated with the plate 805 is selected and coupled to the sense amplifier 830.

[0120] As described herein, a plate shared by a group of memory cells (e.g., plate 805) may be selected, and each digit line associated with the plate may be selected in parallel. For example, plate 805 may be selected (e.g., by applying a voltage via plate line 820), which may cause the voltage across plate 805 to increase. In some instances, each (all) digit lines corresponding to plate 805 may be selected (e.g., digit lines 810-a to 810-e). Each of the digit lines may be selected simultaneously (e.g., in parallel, at the same time, for the same duration). To access a memory cell (or a group of memory cells) associated with plate 805, the associated word line may be activated. For example, a first memory cell 835 (e.g., a first ferroelectric memory cell) may be located at the intersection of word line 815-a and digit line 810-d (e.g., the first digit line), and a second memory cell 840 (e.g., a second ferroelectric memory cell) may be located at the intersection of word line 815-a and digit line 810-e (e.g., the second digit line).

[0121] Since each digital line associated with the plate 805 can be selected during an access operation, the first memory cell 835 and the second memory cell 840 can be accessed in parallel by selecting the word line 815-a. Thus, in some instances, an access operation can be performed on the first ferroelectric memory cell when the second digital line is selected. In other words, data can be written to or read from the first ferroelectric memory cell 835 when the digital line associated with the second ferroelectric memory cell 840 is selected (e.g., when the digital line is activated). In some instances, other memory cells associated with the memory array 800 can also be accessed while the first memory cell 835 and the second memory cell 840 are being accessed. For example, the memory cells located at the intersections of the respective digital lines and the word line 815-a can be accessed while the first memory cell 835 and the second memory cell 840 are being accessed (e.g., because each digital line of the plate 805 is selected).

[0122] As described herein, there may be a risk of unintended electrical interference (e.g., cross-coupling) when adjacent access lines are selected. However, in some instances, each of the sense amplifiers 830 can be configured to sense one or more memory cells in a manner that supports the parallel selection of multiple adjacent digital lines and such interference risk is reduced. For example, the sense amplifiers 830, each of which can be or can be referred to as a high-gain sense amplifier 830, can be configured to support the use of lower voltage swing signals on the digital line 810, and can also be configured (e.g., via one or more associated capacitors) to avoid signal saturation (e.g., for strong memory cells). In other words, the sense amplifiers 830 can be configured to sense the memory cell (e.g., the first memory cell 835) when one or more digital lines adjacent to the memory cell are selected (e.g., when the digital line 810-e is selected), and the risk of unintended electrical interference is reduced. Thus, during the access operation of the first memory cell 835, the configuration of the sense amplifiers 830 (as described with reference to Figure 9 and 10 can prevent any unintended data corruption caused by the parallel selection of multiple digital lines.

[0123] In some instances, the plate 805 can be coupled to a multiplexing component 825, which is coupled to a corresponding plurality (a group) of sense amplifiers 835. The corresponding plurality (a group) of sense amplifiers 835 can include a plurality (a group) of sense amplifiers 830, which can thus be coupled to the multiplexing component 825. Thus, the multiplexing component 825 can couple each activated digital line to a corresponding sense amplifier 830 within the corresponding plurality (a group) of sense amplifiers 835. Thus, in some instances, the memory cells associated with each of the selected digital lines (e.g., digital line 810-a to digital line 810-e) can be accessed in parallel.

[0124] As Figure 8 shown, board 805 may correspond to any number of digit lines. For example, board 805 may correspond to eight (8) digit lines each configured to be selected in parallel (e.g., simultaneously). However, in other instances, the board may correspond to any number of digit lines. Additionally or alternatively, the board may correspond to any number of multiplexing components and / or sense amplifiers that allow memory cells associated with the selected digit lines to be sensed in parallel (e.g., simultaneously).

[0125] Figure 9 Illustrate an example of a circuit 900 that supports digit line management for a memory array in accordance with examples disclosed herein. In some examples, circuit 900 may include one or more components described above with reference to Figures 4 to 8 . For example, circuit 900 may include memory cells 905, signal lines 910, and sense amplifier 920. Sense amplifier 920 may include an output 925 (e.g., output node 925), a first input 922 (e.g., first input node 922), and a second input 924 (e.g., second input node). The first input 922 may be coupled to switch 945, and the second input 924 may be coupled to a voltage source (e.g., a reference voltage, a target voltage, a digit line precharge voltage). Circuit 900 may include a first capacitor 950 (which may be referred to as a linear compensation capacitor, or LinCompCAP), a second capacitor 965 (which may be referred to as an amplifier capacitor, or AMPCAP), switches 940, 945, 955, 967, 974, 976, 977, and latch 970. The latch may include switch 972. In some examples, memory cell 905 may include a transistor (e.g., a switching component) 963 and a capacitor 971 (e.g., a storage component, which may be a ferroelectric capacitor). Memory cell 905 may be coupled to a digit line, a word line, and a board line 975. Each of switches 940, 945, 955, 967, 972, 974, 976, and 977 may include, for example, one or more transistors.

[0126] In some examples, memory cell 905 may be indirectly coupled to sense amplifier 920. For example, memory cell 905 may be coupled (e.g., selectively coupled and decoupled) to signal line 910 via switch 955, and the signal line may in turn be coupled (e.g., selectively coupled and decoupled) to sense amplifier 920 via switch 945.

[0127] The switch 945 can be in a first position or a second position. The first position of the switch 945 can place the circuit 900 in a sense mode, and the second position of the switch 945 can place the circuit 900 in a writeback mode. In the writeback mode, the switch 945 can couple the memory cell 905 with the latch 970.

[0128] Additionally, the memory cell 905 can be coupled to a switch 955 that can select digital lines and couple a selected digital line with the signal line 910. In one example, the switch 955 can be configured to select multiple digital lines (not shown) in parallel and couple each of the multiple digital lines with a corresponding one of multiple sense amplifiers (not shown) in parallel to sense multiple memory cells in parallel, one of which is the memory cell 905. The switch 955 can be in a first position or a second position. The first position of the switch 955 can decouple the memory cell 905 from the signal line 910, and the second position can couple the memory cell 905 with the signal line 910 (and thus to the sense amplifier 920 when the switch 945 is also in the first position).

[0129] In some examples, the switch 940 can be a double - throw switch and can be activated based on the application of a control signal (e.g., PRECH). In some examples, the switch 940 can include multiple single - throw switches that can operate together to provide the functionality ascribed to the switch 940 herein. When the switch 940 is in the first position, the switch 940 can decouple the sense amplifier output 925 from the first input 922 and can couple the sense amplifier output 925 with the plate of the second capacitor 965 and with the switch 967. When the switch 940 is in the second position, the switch can couple the sense amplifier output 925 with the sense amplifier first input 922 to form a feedback loop and can decouple the sense amplifier output 925 from the plate of the second capacitor 965 and the switch 967.

[0130] In some examples, the switch 967 can be coupled to a voltage source (e.g., 0.8V) and can be configured to be activated based on a control signal (e.g., PRECHD). In one example, the switch 967 can be configured to apply a voltage from the voltage source to the second capacitor 965 (and the sense amplifier output 925, depending on the position of the switch 940) based on the application of the control signal to the switch 967 (e.g., based on the control signal going “high”). The first position of the switch 967 can decouple the second capacitor 965 from the voltage source, and the second position can couple the second capacitor 965 with the voltage source.

[0131] In some instances, switch 972 may be configured to selectively couple or decouple latch 970 from a power supply (e.g., a 1.0V power supply). In some instances, switch 977 may be configured to couple or decouple latch 970 from a second power supply or a reference voltage (e.g., VSS) based on a control signal. When both switches 972 and 977 are closed, latch 970 may be activated, and when either of switches 972 and 977 is open, latch 970 may be deactivated. Activating latch 970 may be referred to as starting latch 970 in some cases, or alternatively as starting sense amplifier 920.

[0132] In some instances, switch 974 may be configured to selectively couple or decouple sense amplifier output 925 from latch 970 based on a control signal (e.g., ISO).

[0133] In some instances, switch 976 may be coupled to a voltage source (e.g., VSS, which may be a negative power supply voltage or a ground reference) and to a first input 922, and may be configured to be activated based on a control signal (e.g., Pre-PRECH). In one instance, switch 976 may be configured to apply a voltage from the voltage source to input node 922, and thus to the terminals of first capacitor 950 and / or second capacitor 965, based on the control signal being applied to switch 976 (e.g., based on the control signal going “high”). A first position of switch 976 may decouple first capacitor 950 and second capacitor 965 from the voltage source, and a second position may couple first capacitor 950 and second capacitor 965 to the voltage source.

[0134] In Figure 9 instances, sense amplifier 920 may be a differential amplifier. In one instance, reference Figures 4 to 10The described sense amplifier can be a differential amplifier. In some instances, the digital line can be precharged by the sense amplifier 920 to a voltage that can be or otherwise reflect an offset voltage (e.g., an inherent or native voltage associated with the sense amplifier 920, and which can be an undesirable or unpredictable voltage). For example, the target or desired precharge voltage can be the voltage at which the second input 924 of the sense amplifier 920 is biased, but the sense amplifier 920 can have an inherent offset of some voltage, and thus the first voltage to which the signal line 910 is precharged can be the target precharge voltage plus / minus the offset voltage. In some instances, the target precharge voltage can be zero (e.g., 0V), and thus the first voltage can be equal to the offset voltage of the sense amplifier 920 (e.g., 0.05V). However, in other instances, the target precharge voltage can be some other voltage (e.g., 1.5V), and thus the first voltage can be equal to the target precharge voltage plus / minus an offset voltage that may not be equal to the offset voltage of the sense amplifier 920 (e.g., 1.55V).

[0135] When configured as an open loop, the sense amplifier 920 can act like a comparator. When the voltage at the first input 922 is lower than the voltage at the second input 924, the sense amplifier 920 can drive the output 925 high. In some cases, the output of the sense amplifier 920 can have a “digital” characteristic such that the voltage can be high or low, and can be used to directly interface with the logic gates of the device (e.g., the logic gates included in the latch 970).

[0136] The voltage on the second input 924 can be a target voltage, which can be approximately zero in some cases. In some instances, the second input node 924 can be biased to a precharge voltage (e.g., the target voltage when the signal line 910 is precharged). In some instances, the first voltage can be based on the gain of the sense amplifier 920. Additionally, the sense amplifier 920 that facilitates the precharging of the signal line 910 can also be the sense amplifier 920 that senses the state of the memory cell.

[0137] In one instance, charge sharing between the memory cell 905 and the signal line 910 and charge sharing between the signal line 910 and the capacitors 950, 965 can occur during at least partially overlapping time periods. In another instance, charge sharing between the memory cell 905 and the signal line 910 can occur before charge sharing between the signal line 910 and the capacitors 950, 965.

[0138] In some instances, the sense amplifier first input 922 may be coupled to a first capacitor 950 (e.g., LinCompCAP). The sense amplifier first input 922 may be coupled to a second capacitor 965 (e.g., AMPCAP). In some instances, the first capacitor 950 may be coupled to a control line 960 (e.g., ARLinC) and to the first input 922. The second capacitor 965 may be coupled to a switch 967 and a switch 940 and to the first input 922. Thus, the first capacitor 950 may be coupled to the second capacitor 965, both of which may be coupled to the sense amplifier first input 922.

[0139] In some instances, the first capacitor 950 and the second capacitor 965 may be configured to share charge with a memory cell 905 (e.g., via digital and signal lines 910). In some instances, the memory cell 905 and the first capacitor 950 may share charge with the second capacitor 965. In some instances, the first capacitor 950 and the second capacitor 965 may share charge (or complete charge sharing) before the memory cell 905 and the first capacitor 950 share charge (or complete charge sharing). In some instances, ferroelectric characteristics (e.g., polarization characteristics) of the memory cell 905 and / or resistance and capacitance (RC impedance) of the digital and signal lines 910 (e.g., due to physical distance between the memory cell 905 and the second capacitor 965) may cause charge sharing between the memory cell 905 and the second capacitor 965 to be slower than charge sharing between the first capacitor 950 and the second capacitor 965 (e.g., the first capacitor 950 may be a linear capacitor, e.g., a CMOS-based capacitor, and may be physically closer to the second capacitor 965 relative to the memory cell 905). Thus, characteristics of the memory cell 905 and / or the digital line may cause charge sharing between the first capacitor 950 and the second capacitor 965 to occur more quickly (and thus stop earlier) than charge sharing between the ferroelectric memory cell 905 and the second capacitor 965. In some cases, charge sharing between the first capacitor 950 and the second capacitor 965 may include charge transfer from the second capacitor 965 to the first capacitor 950, and charge sharing between the memory cell 905 and the second capacitor 965 may include charge transfer from the memory cell 905 to the second capacitor 965. The first capacitor 950 and / or the second capacitor 965 may be configured (e.g., sized) to maintain the sense amplifier 920 within a linear operating range during a sense operation as described herein (e.g., when sensing the memory cell 905). That is, the first capacitor 950 and / or the second capacitor 965 may be configured (e.g., sized) to maintain the voltage at the first input 922 within a range that avoids saturating the sense amplifier 920.

[0140] In some instances, the latch 970 may vary depending on the desired characteristics of the circuit 900. For example, various implementations of the latch 970 may be configured to operate at different voltage levels or in view of various performance trade - offs such as component count or complexity, footprint, operating speed, etc. The latch 970 may thus be configured to accommodate but not significantly affect some of the functions discussed with respect to other aspects of the circuit 900. For example, the latch 970 may not affect the functionality of pre - charging the digital lines and signal lines 910 by the sense amplifier 920, and may also not affect the charge - sharing function between the signal line 910 and the memory cell 905, or the charge - sharing between the capacitor (e.g., the first capacitor 950 and / or the second capacitor 965) and the memory cell 905. Additionally, any suitable logical combination implementing similar functionality may be used, such as but not limited to flip - flop components or set - reset latches. In some cases, the latch 970 may be utilized in various scenarios. For example, the latch 970 may be configured to be used with components having a relatively low voltage tolerance.

[0141] As discussed herein, utilizing such sensing schemes may allow multiple digital lines (e.g., each digital line sharing the same board) to be selected in parallel. Thus, the sensing operations described herein with reference to Figure 9 may occur in parallel across multiple digital lines sharing the same board (e.g., using multiple sense amplifiers described with reference to Figure 5 , 6 and 8). Additionally, by utilizing the sense amplifiers described herein (e.g., high - gain sense amplifiers), the voltages across adjacent digital lines may be more easily distinguishable, resulting in greater reliability during access operations.

[0142] Figure 10 An example of a timing diagram 1000 supporting digital line management for a memory array in accordance with examples disclosed herein is illustrated. In some instances, the timing diagram 1000 may correspond to the operation of the circuit 900 as illustrated in Figure 9 .

[0143] Before t0, circuit 900 may be in an initial configuration. Switch 955 may be configured to decouple (isolate) the digital line from signal line 910. In some cases, switch 945 may be configured to couple the first input node 922 to signal line 910. In other cases, switch 945 may be configured to decouple (isolate) the first input node 922 from signal line 910. The Pre-PRECH signal 1005 may be low, and thus switch 976 may be open or otherwise configured to decouple (isolate) the first input node 922 from VSS. Accordingly, LinCompCAP 950 and AMPCAP 965 may be decoupled from the voltage source (e.g., decoupled from VSS). The PRECH signal 1010 may be low, and thus switch 940 may be configured to decouple the output 925 from the first input node 922 and couple the output 925 to the node of AMPCAP 965 and switch 967. The PRECHD signal 1015 may be low, and thus switch 967 may be configured to decouple (isolate) AMPCAP 965 and switch 940 from the voltage source (e.g., 0.8V) to which switch 967 is coupled. The ISO signal 1020 may be low, and thus switch 974 may be configured to decouple the output 925 from latch 970. The ARLinC signal 1025 may be high, and thus a voltage (e.g., a positive voltage) may be applied to one node of LinCompCAP 950.

[0144] At t0, board line 975 may be selected, and as shown by the PL waveform in Figure 10 , the voltage of board line 975 may be increased to a selected board line voltage (e.g., 1.5V), which may be referred to as the VMSA voltage.

[0145] At t1, which may be simultaneous with or after the voltage of board line 975 reaches the VMSA voltage, the digital line may be selected. In some cases, selecting the digital line may include coupling the digital line to the first input 922 of sense amplifier 920. This may include configuring switch 955 to couple the digital line to signal line 910. If signal line 910 has not been coupled to the first input node 922, selecting the digital line may further include configuring switch 945 to couple signal line 910 to the first input node 922.

[0146] In some instances, at t1, the Pre-PRECH signal 1005, the PRECH signal 1010, and the PRECHD signal 1015 may transition from their respective low states to their respective high states. The ARLinC signal 1025 may remain high, and the ISO signal 1020 may remain low. When the Pre-PRECH signal 1005 is high, the switch 976 may be activated (e.g., it may move to the second position). For example, when the switch 976 is in the second position, the first input node 922 (and thus, one node of the LinCompCAP 950 and one node of the AMPCAP 965) may be coupled to VSS, which may initialize the first input node 922 to VSS (e.g., ground the first input node 922). When coupled to VSS, the signal applied via the signal line 960 (the ARLinC signal 1025) may allow charge to be placed on the LinCompCAP 950 (e.g., if VSS is ground, the LinCompCAP 950 may be charged to the high state voltage of the ARLinC). Thus, the amount of charge stored on and shared by the first capacitor 950 may be based on the voltage of the signal applied via the control line 960.

[0147] In some instances, the Pre-PRECH signal 1005 may remain high for only a portion of the time between t1 and t2 (e.g., the Pre-PRECH signal 1005 may go "low" before t2). The PRECH signal 1010 and the PRECHD signal 1015 may remain high after the Pre-PRECH signal 1005 goes low.

[0148] In some instances, when the PRECH signal 1010 is high, the switch 940 may be in the second position. As described herein, the switch 940 may comprise a double-throw switch or multiple single-throw switches. As described herein, when the switch 940 is in the second position, the switch 940 may couple the output 925 of the sense amplifier 920 to the first input 922 of the sense amplifier 920, which may cause the sense amplifier 920 to pre-charge the digital line (and thus also the signal line 910 coupled thereto) to a first voltage or an initial sense voltage, which may be based on (e.g., equal to) the voltage applied to the second input 924 of the sense amplifier plus or minus any offset voltage that the sense amplifier 920 may inherently have. In some instances, switching the switch 940 to the second position may form a feedback loop. As discussed herein, the feedback loop may be formed by coupling the output 925 of the sense amplifier to the first input 922 of the sense amplifier. Figure 10 The DL_sel waveform in shows an example case where the sense amplifier 920 has a slight positive offset and thus DL_sel approaches but does not fully reach the target pre-charge voltage of 0V biased by the second input 924 for the digital line voltage.

[0149] In some instances, when the PRECHD signal 1015 is high, switch 967 may be in the second position. When switch 967 is in the second position, AMPCAP 965 may be coupled to a voltage source (e.g., coupled to 0.8V). In some instances, coupling AMPCAP 965 to a voltage source may allow charge to be placed on AMPCAP 965 (e.g., AMPCAP 965 may be charged to the voltage difference between the voltage source and VSS (e.g., Figure 9 0.8V in the instance where VSS is grounded)). Thus, the amount of charge stored on and shared by capacitor 965 may be based on the voltage applied via switch 967.

[0150] At t2, the PRECH signal 1010 may transition from a high state to a low state (e.g., the PRECH signal 1010 may go “low” at t2). In some instances, when the PRECH signal 1010 goes low (e.g., returns to low), switch 940 may switch to the first position, and the sense amplifier feedback loop may be deactivated due to the sense amplifier output 925 being decoupled (isolated) from the first input 922 of the sense amplifier. Deactivating the feedback loop may end (stop) precharging the digital line to the target voltage.

[0151] Additionally, when the PRECH signal 1010 goes low (e.g., returns to low), the output 925 of sense amplifier 920 may be coupled to a voltage source (e.g., Figure 9 0.8V in ) via switch 940 and switch 967, as the control signal PRECHD 1015 remains high. As shown by the DIFF_OUT waveform that starts rising to 0.8V at t2 in Figure 10 , this may “set” or initialize the output 925 to the voltage of the voltage source (e.g., 0.8V). When the PRECH signal 1010 goes low, the output 925 of sense amplifier 920 may also be coupled to AMPCAP 965, i.e., AMPCAP 965 may be coupled to both the output 925 and the first input 922 of sense amplifier 920.

[0152] In some instances, the PRECHD signal 1015 may remain high during the entire period between t1 and t2 (e.g., the PRECHD signal 1015 may remain “high” until after t2). Thus, the PRECHD signal 1015 may remain high after the PRECH signal 1010 and the Pre - PRECH signal 1005 have gone low. In some instances, after the signals transition from high to low, the Pre - PRECH signal 1005 and the PRECH signal 1010 may remain low for the remainder of the access operations described herein.

[0153] In some instances, the PRECHD signal 1015 may go low before t3. When the PRECHD signal 1015 goes low, the switch 967 may return to the first position, and thus the second capacitor 965 and the output 925 may be decoupled from the voltage source (e.g., decoupled from 0.8V). At this time, the input node 922 may be floating because the first input 922 of the sense amplifier 920 may have a high (theoretically infinite) input impedance, the transistor 963 may isolate the digital line from the memory cell 905, the switch 976 may isolate the first input node 922 from VSS, and the AMPCAP 965 and LinCompCAP 950 may present an open circuit to the first input node 922.

[0154] At t3, which may be after the PRECHD signal 1015 goes low, the word line may be selected (activated), which may cause the transistor 963 to couple the digital line to the memory cell 905 after the word line reaches the threshold voltage of the transistor 963, such that the memory cell 905 may share charge with one or more of the digital line (e.g., may be parasitic digital line capacitance), the signal line 910 (e.g., may be parasitic signal line 910 capacitance), the LinCompCAP 950, and the AMPCAP 965. In some instances, the enabling of the relevant word line may be indicated by an increasing word line voltage (e.g., WL voltage), as demonstrated by the WL waveform in Figure 10 as shown.

[0155] In some instances, charge sharing between the AMPCAP 965 and the LinCompCAP 950 (e.g., charge transfer from the AMPCAP 965 to the LinCompCAP 950) may occur or be completed before charge sharing between the memory cell 905 and the AMPCAP 965 (e.g., charge transfer from the memory cell 905 to the AMPCAP 965). For example, the ferroelectric properties of the memory cell 905, the resistance and capacitance (RC impedance) of the digital line, and the properties of the transistor 963 may delay the sharing of charge between the memory cell 905 and the AMPCAP 965. However, the LinCompCAP 950 may be a linear capacitor (with a linear dielectric), such as a CMOS capacitor, and may be physically close to the AMPCAP 965 (e.g., both the LinCompCAP 950 and the AMPCAP 965 may be within the same sense amplifier circuit), and thus charge sharing between the LinCompCAP 950 and the AMPCAP 965 may occur faster (at a faster rate) compared to charge sharing between the memory cell 905 and the AMPCAP 965.

[0156] For example, when a word line is selected at t3, memory cell 905 may not be coupled (or fully coupled) to the first input node 922 (and thus not to LinCompCAP 950 and AMPCAP 965) until the voltage of the word line increases to the threshold voltage of transistor 963, which may have a resistance that starts decreasing at t3 over time.

[0157] In some instances, at some time between t3 and t4 (e.g., soon after t3, at a time concurrent with or prior to when the voltage of the word line reaches the threshold voltage of transistor 963), the ARLinC signal 1025 may go low (e.g., transition from a high state to a low state). In some cases, when the ARLinC signal 1025 transitions from high to low, this may cause LinCompCap 950 to start charge sharing with AMPCAP 965 (e.g., extracting charge therefrom), which charge sharing may occur relatively quickly after t3 with respect to the charge sharing between memory cell 905 and AMPCAP 965 for reasons explained herein (e.g., closer proximity of LinCompCap 950, ferroelectric nature of memory cell 905). Thus, the charge sharing between memory cell 905 and AMPCAP 965 (e.g., charge transfer from the memory cell to AMPCAP 965) may continue after the ARLinC signal 1025 goes low and after the charge sharing between LinCompCAP 950 and AMPCAP 965 is complete. In some instances, after transitioning to low, the ARLinC signal 1025 may remain low for the remainder of the access operation described herein. In some instances, AMPCAP 965 may integrate (e.g., store) the charge shared (exchanged therebetween) with memory cell 905 and LinCompCAP 950 after t3.

[0158] LinCompCAP 950 and AMPCAP 965 may be configured (sized) to maintain sense amplifier 920 in a linear (non-saturated) operating mode (region) when charge is shared between one or more of capacitors 950, 965 and memory cell 905. For example, compared to some embodiments, one or both of first capacitor 950 and second capacitor 965 may be larger (have an increased capacitance).

[0159] Between t3 and t4, when charge sharing occurs between memory cell 905 and one or more other aspects of circuit 900 described herein, the voltage of first input 922 may change depending on the amount of charge stored by memory cell 905 prior to the sense operation (i.e., depending on the logic state stored by memory cell 905 prior to the sense operation), and thus the voltage of output 925 may change. This may occur in Figure 10Depicted as two different possible voltage levels output from the sense amplifier (e.g., two different voltages to which the DIFF_OUT waveform can transition between t3 and t4). Although Figure 10 Two voltages are illustrated as being output from sense amplifier 920, but this is for illustrative purposes only, and depending on the sensed logic state of memory cell 905, only one of the two voltages is output. The higher voltage level (DIFF_OUT) at output 925 can be higher than the reference voltage (VREF) and can indicate that the memory cell state is equivalent to a high or one (1) logic state, while the lower voltage level (DIFF_OUT) at output 925 can be lower than the reference voltage (VREF) and can indicate that the memory cell state is equivalent to a low or zero (0) value, or vice versa. Additionally, Figure 10 The voltage levels in

[0160] As Figure 10 Depicted in, the voltage levels output from sense amplifier 920 can all shift downward during charge sharing between capacitors 950, 965, and memory cell 905. The high and low voltage levels of the output can be pulled down and can be centered approximately around the sum of the target voltage and the offset voltage to which signal line 910 is precharged. The two voltage levels that are pulled down can be at least partially based on the access line that has been precharged by sense amplifier 920 previously, and thus can inherently reflect the offset voltage, which can inherently compensate for the offset voltage (e.g., eliminate its effect).

[0161] At t4, the ISO signal 1020 can be enabled (e.g., the ISO signal 1020 can go “high”). When the ISO signal 1020 goes high, sense amplifier 920 can be coupled to latch 970, which can allow latch 970 to store the state sensed by sense amplifier 920 for memory cell 905 (e.g., latch 970 can store whether DIFF_OUT corresponds to the upper voltage or the lower voltage at t4).

[0162] After t4 and before t5, the ISO signal 1020 can return low, which can decouple sense amplifier 920 from latch 970.

[0163] At t5, switch 972 can couple latch 970 to a power supply (e.g., 1.0V), and switch 977 can couple latch 970 to a second power supply or reference voltage (e.g., VSS, which can be a negative voltage supply or ground), which can be referred to as activating latch 970, or alternatively as activating sense amplifier 920.

[0164] In some instances, as referred to herein Figure 10The described sensing operations can occur in parallel across multiple digital lines sharing the same board (e.g., using multiple sense amplifiers described with reference to Figure 5 , 6 and 8). By leveraging the sense amplifiers described herein (e.g., high-gain sense amplifiers), the states of multiple memory cells 905 can be sensed in parallel via adjacent digital lines, where the correlated fluctuations of the voltages across the adjacent digital lines are minimized (e.g., using low-swing signaling on the digital lines), thereby reducing the risk of crosstalk and increasing the reliability during access operations. Accordingly, the scheme described with reference to Figure 10 can be used to sense multiple memory cells associated with a shared board in parallel.

[0165] Figure 11 FIG. 1100 is a block diagram showing an array management component 1105 that supports digital line management for a memory array according to an example disclosed herein. The array management component 1105 can perform one or more aspects of access operations on a memory array described with reference to Figures 4 to 10 . The array management component 1105 can include a selection component 1110, a sensing component 1115, a coupling component 1120, a biasing component 1125, a precharging component 1130, a decoupling component 1135, an application component 1140, an access component 1145, and a transmission component 1150. Each of these modules can communicate with each other directly or indirectly (e.g., via one or more buses).

[0166] The selection component 1110 can select a board shared by a group of ferroelectric memory cells, each of the group of ferroelectric memory cells being coupled to a respective digital line in a group of digital lines corresponding to the board. In some examples, the selection component 1110 can select the digital lines corresponding to the board based on selecting the board. In some examples, the selection component 1110 can select a word line coupled to a subset of the group of ferroelectric memory cells while selecting the digital lines corresponding to the board.

[0167] In some examples, the selection component 1110 can select a first digital line coupled to a first ferroelectric memory cell and a second digital line coupled to a second ferroelectric memory cell, the first ferroelectric memory cell and the second ferroelectric memory cell being coupled to the board, and wherein the first digital line is electrically isolated from the second digital line by a shield line. In some examples, the selection component 1110 can select all of the digital lines corresponding to the board simultaneously. In some examples, the selection component 1110 can select the first digital line and the second digital line simultaneously, where an access operation is performed based on simultaneously selecting the first digital line and the second digital line. In some examples, the selection component 1110 can select the digital lines of each of the group of ferroelectric memory cells during an access operation.

[0168] Based on the selected word line, the sensing component 1115 can sense the corresponding charge stored in each ferroelectric memory cell of the subset.

[0169] The coupling component 1120 can couple the digital line to the first input node of the sense amplifier. In some instances, the coupling component 1120 can couple the output node of the sense amplifier to a reference voltage. In some instances, the coupling component 1120 can couple the second node of the capacitor to a reference voltage. In some instances, the coupling component 1120 can couple the ferroelectric memory cell to the input node of the sense amplifier based on selecting the word line after precharging the corresponding digital line, wherein based on the coupling, a portion of the corresponding charge is transferred between the ferroelectric memory cell and the capacitor.

[0170] The biasing component 1125 can bias the second input node of the sense amplifier to a precharge voltage.

[0171] The precharging component 1130 can precharge the digital line to a precharge voltage based on coupling the output node of the sense amplifier to the first input node of the sense amplifier.

[0172] The decoupling component 1135 can decouple the output node of the sense amplifier from the first input node of the sense amplifier.

[0173] The applying component 1140 can apply a voltage to the capacitor when precharging the corresponding digital line, wherein the capacitor is coupled within the input node of the sense amplifier. In some instances, the applying component 1140 can apply a second voltage to a second capacitor before coupling the ferroelectric memory cell to the input node of the sense amplifier, wherein the second capacitor is coupled within the input node of the sense amplifier, and wherein based on the coupling, a second portion of the corresponding charge is transferred between the ferroelectric memory cell and the second capacitor.

[0174] The access component 1145 can perform an access operation on the first ferroelectric memory cell while selecting a second digital line.

[0175] The transmission component 1150 can transmit a first signal along a first digital line. In some instances, the transmission component 1150 can transmit a second signal along a second digital line, wherein the shielded line includes a ground conductor configured to isolate the first signal from the second signal.

[0176] Figure 12 FIG. shows a flowchart illustrating a method or methods 1200 for digital line management in support of a memory array according to aspects of the present disclosure. The operations of method 1200 can be implemented by a memory array or its components as described herein. For example, the operations of method 1200 can be performed with reference to Figure 11The described array management component performs. In some instances, a memory controller (e.g., the array management component) may execute a set of instructions to control functional elements of a memory array to perform the described functions. Additionally or alternatively, aspects of the described functions may be performed by the memory array using dedicated hardware.

[0177] At 1205, a board shared by a set of ferroelectric memory cells may be selected. In some instances, each of the set of ferroelectric memory cells may be coupled to a respective one of a set of digit lines corresponding to the board. The operation of 1205 may be performed according to the methods described herein. In some instances, aspects of the operation of 1205 may be performed by a selection component referenced Figure 11 as described.

[0178] At 1210, digit lines corresponding to the board may be selected based on the selection of the board. The operation of 1210 may be performed according to the methods described herein. In some instances, aspects of the operation of 1210 may be performed by a selection component referenced Figure 11 as described.

[0179] At 1215, word lines coupled to a subset of the set of ferroelectric memory cells may be selected while selecting the digit lines corresponding to the board. The operation of 1215 may be performed according to the methods described herein. In some instances, aspects of the operation of 1215 may be performed by a selection component referenced Figure 11 as described.

[0180] At 1220, the respective charges stored by each ferroelectric memory cell of the subset may be sensed based on the selection of the word lines. The operation of 1220 may be performed according to the methods described herein. In some instances, aspects of the operation of 1220 may be performed by a sensing component referenced Figure 11 as described.

[0181] In some instances, a device as described herein may execute methods such as method 1200 or multiple methods. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: selecting a board shared by a set of ferroelectric memory cells, each of the set of ferroelectric memory cells being coupled to a respective one of a set of digit lines corresponding to the board; selecting the set of digit lines corresponding to the board based on the selection of the board; selecting word lines coupled to a subset of the set of ferroelectric memory cells when selecting the set of digit lines corresponding to the board; and sensing the respective charges stored by each ferroelectric memory cell of the subset based on the selection of the word lines.

[0182] In some instances of the method 1200 and apparatus described herein, selecting the set of digit lines corresponding to the plate may include operations, features, components, or instructions for simultaneously selecting all of the set of digit lines corresponding to the plate.

[0183] In some instances of the method 1200 and apparatus described herein, selecting the digit lines corresponding to the plate may include operations, features, components, or instructions for: coupling a digit line to a first input node of a sense amplifier; biasing a second input node of the sense amplifier to a precharge voltage; and precharging the digit line to the precharge voltage based on coupling an output node of the sense amplifier to the first input node of the sense amplifier.

[0184] Some instances of the method 1200 and apparatus described herein may further include operations, features, components, or instructions for: decoupling an output node of the sense amplifier from the first input node of the sense amplifier; and coupling the output node of the sense amplifier to a reference voltage. Some instances of the method 1200 and apparatus described herein may further include operations, features, components, or instructions for: coupling a second node of a capacitor to the reference voltage.

[0185] In some instances of the method 1200 and apparatus described herein, sensing the respective charge stored by the subset of ferroelectric memory cells may include operations, features, components, or instructions for: applying a voltage to a capacitor when precharging a respective digit line, wherein the capacitor may be coupled within an input node of the sense amplifier; and coupling the ferroelectric memory cell to the input node of the sense amplifier based on selecting a word line after precharging the respective digit line, wherein based on the coupling, a portion of the respective charge may be transferred between the ferroelectric memory cell and the capacitor.

[0186] In some instances of the method 1200 and apparatus described herein, sensing the respective charge stored by the subset of ferroelectric memory cells may further include operations, features, components, or instructions for: applying a second voltage to a second capacitor before coupling the ferroelectric memory cell to the input node of the sense amplifier, wherein the second capacitor may be coupled within the input node of the sense amplifier, and wherein based on the coupling, a second portion of the respective charge may be transferred between the ferroelectric memory cell and the second capacitor.

[0187] Figure 13FIG. 1300 is a flow diagram showing a method or methods for supporting digital line management for a memory array in accordance with aspects of the present disclosure. Operations of method 1300 may be implemented by an array management component or components thereof as described herein. For example, operations of method 1300 may be performed by a memory controller (e.g., an array management component) as referenced Figure 11 as described. In some instances, a memory array may execute a set of instructions to control functional elements of the memory array to perform the described functions. Additionally or alternatively, the memory array may use dedicated hardware to perform aspects of the described functions.

[0188] At 1305, a first digital line coupled to a first ferroelectric memory cell and a second digital line coupled to a second ferroelectric memory cell may be selected. In some instances, the first ferroelectric memory cell and the second ferroelectric memory cell may be coupled to a board, and the first digital line may be electrically isolated from the second digital line by a shielded line. Operations at 1305 may be performed in accordance with methods described herein. In some instances, aspects of the operations at 1305 may be performed by a selection component as referenced Figure 11 as described.

[0189] At 1310, an access operation may be performed on the first ferroelectric memory cell when the second digital line is selected. Operations at 1310 may be performed in accordance with methods described herein. In some instances, aspects of the operations at 1310 may be performed by an access component as referenced Figure 11 as described.

[0190] In some instances, a device as described herein may execute a method or methods such as method 1300. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: selecting a first digital line coupled to a first ferroelectric memory cell and a second digital line coupled to a second ferroelectric memory cell, the first ferroelectric memory cell and the second ferroelectric memory cell being coupled to a board, and wherein the first digital line is isolated from the second digital line by a shielded line; and performing an access operation on the first ferroelectric memory cell when the second digital line is selected.

[0191] Some examples of the method 1300 and apparatus described herein may further include operations, features, components, or instructions for: simultaneously selecting a first digit line and a second digit line, wherein performing the access operation may be based on the simultaneous selection of the first digit line and the second digit line. Some examples of the method 1300 and apparatus described herein may further include operations, features, components, or instructions for selecting a digit line of each of the group of ferroelectric memory cells during an access operation. In some examples of the method 1300 and apparatus described herein, performing an access operation on a first ferroelectric memory cell may include operations, features, components, or instructions for: transmitting a first signal along the first digit line; and transmitting a second signal along the second digit line, wherein the shield line includes a ground conductive wire configured to isolate the first signal from the second signal.

[0192] Note that the methods described above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0193] An apparatus is described. The apparatus may include a group of sense amplifiers and a memory array including a group of plates that are each common to a corresponding group of ferroelectric memory cells, wherein each corresponding group of ferroelectric memory cells is coupled to a corresponding digit line in a group of digit lines, the group of digit lines corresponding to the plates in the group of plates, and the group of digit lines corresponding to the plates in the group are configured to be coupled in parallel to a corresponding sense amplifier in the group.

[0194] Some examples of the apparatus may include operations, features, components, or instructions for: a plate selection component configured to select a selected plate within each plate group of the group; and a group of multiplexing components, wherein for the selected plate within each plate group of the group, each multiplexing component of the group may be configured to couple in parallel all of the group of digit lines corresponding to the selected plate to a corresponding group of sense amplifiers for the plate group including the selected plate. In some examples, the corresponding group of sense amplifiers for the plate group may be configured to sense, in parallel, the respective amounts of charge stored by the corresponding ferroelectric memory cells for each of the group of digit lines corresponding to the selected plate.

[0195] In some examples, the sense amplifier in the set of sense amplifiers can include operations, features, components, or instructions for: a differential amplifier having a first input node, a second input node, and an output node, where the first input node of the differential amplifier can be configured to selectively couple to a digital line in the set of digital lines corresponding to the die, the output node of the differential amplifier can be configured to selectively couple to the first input node of the differential amplifier, and the differential amplifier can be configured to pre - charge the digital line based on a voltage at the second input node of the differential amplifier when the output node of the differential amplifier can be coupled to the first input node. In some examples, the sense amplifier in the set of sense amplifiers can include operations, features, components, or instructions for: an amplifier; and a first capacitor and a second capacitor, both coupled to an input node of the amplifier, where during an access operation for a corresponding set of ferroelectric memory cells, the first capacitor and the second capacitor can both be configured to share charge with the ferroelectric memory cells.

[0196] In some examples, the first capacitor can be configured to couple to an output node of the amplifier during a first part of the access operation. In some examples, a node of the second capacitor can be configured to be set to a first voltage during a first part of the access operation and to a second voltage during a second part of the access operation. Some examples can further include that all the sets of digital lines corresponding to the die can be below or above the die. In some examples, each respective digital line in the set of digital lines corresponding to the die can be located between a pair of ground conductive lines, and the ground conductive lines can be configured to electrically isolate the respective digital line from every other digital line in the set of digital lines corresponding to the die.

[0197] A device is described. The device can include: a first digital line coupled to a first ferroelectric memory cell; a second digital line coupled to a second ferroelectric memory cell; a die that is common to the first ferroelectric memory cell and the second ferroelectric memory cell; and a shield line positioned between the first digital line and the second digital line and configured to electrically isolate the first digital line from the second digital line during an access operation associated with the first ferroelectric memory cell, the second ferroelectric memory cell, or both.

[0198] Some examples of the device may include: a set of digital lines including a first digital line and a second digital line; a set of ferroelectric memory cells including a first ferroelectric memory cell and a second ferroelectric memory cell, wherein each ferroelectric memory cell of the set may have a common plate, and wherein each digital line of the set may be coupled to a corresponding ferroelectric memory cell of the set; and a set of shield lines including the shield lines, wherein each shield line of the set may be positioned between a corresponding pair of digital lines of the set and configured to electrically isolate the first digital line in the corresponding pair from the second digital line in the corresponding pair during an access operation.

[0199] In some examples, each digital line of the set may be configured to be selected in parallel during an access operation. In some examples, each digital line of the set may be configured to transfer data to or from a corresponding ferroelectric memory cell during an access operation. In some examples, the shield line includes a ground conductor wire that may be electrically isolated from each ferroelectric memory cell of the device.

[0200] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, those of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0201] As used herein, the term "virtual ground" refers to a circuit node that is maintained at a voltage of approximately zero volts (0V) without being directly coupled to ground. Thus, the voltage of the virtual ground may fluctuate temporarily and return to approximately 0V in a stable state. A virtual ground may be implemented using various electronic circuit elements such as a voltage divider consisting of an operational amplifier and a resistor. Other implementations are possible. "Virtual ground" or "virtual earth ground" means connected to approximately 0V.

[0202] The terms "electronically communicate", "electrically contact", "connect", and "couple" can refer to a relationship between components that supports the flow of signals between the components. Components are considered to be in electronic communication with each other (or in electrical contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between components that are in electronic communication with each other (or in electrical contact with each other, or connected to each other, or coupled to each other) can be an open circuit or a closed circuit. The conductive path between the connected components can be a direct conductive path between the components, or the conductive path between the connected components can be an indirect conductive path that can include intermediate components such as switches, transistors, or other components. In some cases, one or more intermediate components such as switches or transistors can be used, for example, to interrupt the signal flow between the connected components for a period of time.

[0203] The term "couple" refers to the condition of moving from an open-circuit relationship between components to a closed-circuit relationship between components, where in the open-circuit relationship, a signal cannot currently be transmitted between the components through the conductive path, and in the closed-circuit relationship, a signal can be transmitted between the components through the conductive path. When a component such as a controller couples other components together, the component initiates a change that allows a signal to flow between the other components through a conductive path that previously did not allow the signal to flow. The term "isolate" refers to a relationship between components where a signal cannot currently flow between the components. If there is an open circuit between the components, the components are isolated from each other. For example, the components separated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components from each other, the controller implements a change that prevents a signal from flowing between the components using a conductive path that previously allowed the signal to flow.

[0204] As used herein, the term "short" refers to a relationship between components where a conductive path is established between the components by activating a single intermediate component between the two relevant components. For example, a first component shorted to a second component can exchange signals with the second component when a switch between the two components is closed. Thus, a short can be a dynamic operation of charge flow between components (or lines) that enables electronic communication.

[0205] The devices described herein that include a memory array may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. The doping may be performed by ion implantation or by any other doping method during the initial formation or growth of the substrate.

[0206] The switching components or transistors described herein may represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. Each terminal may be connected to other electronic components by a conductive material such as metal. The source and the drain may be conductive and may include heavily doped semiconductor regions, such as degenerate semiconductor regions. The source and the drain may be separated by a lightly doped semiconductor region or a channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The conductivity of the channel may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be “turned on” or “activated”. When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be “turned off” or “deactivated”.

[0207] The description set forth herein in connection with the drawings describes example configurations and does not represent all examples that may be implemented or that are within the scope of the claims. The term “exemplary” as used herein means “serving as an example, instance, or illustration” and is not “preferred” or “superior to other examples”. The detailed description includes specific details for providing an understanding of the described techniques. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0208] In the figures, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that differentiates among the similar components. If only the first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label regardless of the second reference label.

[0209] Any of a variety of different technologies and techniques can be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0210] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0211] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on a computer-readable medium or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software, hardware, firmware, hardwiring, or any combination of these. The features implementing the functions can also be physically located in various places, including being distributed such that portions of the functions are implemented at different physical locations. Additionally, as used herein (including in the claims), the "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Additionally, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, an exemplary step described as "based on condition A" can be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be understood in the same manner as the phrase "at least partially based on".

[0212] The description herein is provided to enable a person of ordinary skill in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those of ordinary skill in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for operating a memory device, comprising: Selecting a plate shared by a plurality of ferroelectric memory cells, each of the plurality of ferroelectric memory cells being coupled to a respective digit line among a plurality of digit lines corresponding to the plate, wherein selecting the plate includes activating the plate; Selecting at least two consecutive digit lines among the plurality of digit lines corresponding to the plate, at least partially based on activating the plate and during the same duration; Selecting a word line coupled to a subset of the plurality of ferroelectric memory cells while selecting the at least two digit lines corresponding to the plate; And Sensing a respective charge stored by each ferroelectric memory cell of the subset, at least partially based on selecting the word line.

2. The method according to claim 1, wherein selecting the plurality of digit lines corresponding to the plate includes: Selecting all of the plurality of digit lines corresponding to the plate simultaneously.

3. The method according to claim 1, wherein selecting the digit lines corresponding to the plate includes: Coupling the digit lines to a first input node of a sense amplifier; Biasing a second input node of the sense amplifier to a precharge voltage; And Precharging the digit lines to the precharge voltage, at least partially based on coupling an output node of the sense amplifier to the first input node of the sense amplifier.

4. The method according to claim 3, further comprising: Decoupling the output node of the sense amplifier from the first input node of the sense amplifier; And Coupling the output node of the sense amplifier to a reference voltage.

5. The method according to claim 4, wherein the first input node of the sense amplifier is coupled to a first node of a capacitor, the method further comprising: Coupling a second node of the capacitor to the reference voltage.

6. The method according to claim 1, wherein sensing the respective charge stored by the subset of ferroelectric memory cells includes: Applying a voltage to a capacitor when precharging the respective digit line, wherein the capacitor is coupled within an input node of the sense amplifier; And Coupling the ferroelectric memory cell to the input node of the sense amplifier at least partially based on selecting the word line after precharging the respective digit line, and transferring a portion of the respective charge between the ferroelectric memory cell and the capacitor at least partially based on the coupling.

7. The method according to claim 6, wherein sensing the respective charge stored by the subset of the ferroelectric memory cells further includes: Applying a second voltage to a second capacitor before coupling the ferroelectric memory cell to the input node of the sense amplifier, wherein the second capacitor is coupled within the input node of the sense amplifier, and transferring a second portion of the respective charge between the ferroelectric memory cell and the second capacitor at least partially based on the coupling.

8. A memory device, comprising: A plurality of sense amplifiers; And A memory array including a plurality of plates shared respectively for a corresponding plurality of ferroelectric memory cells, wherein: Each corresponding plurality of ferroelectric memory cells is coupled to a respective digital line among a plurality of digital lines corresponding to the plates in the plurality of plates; and The plurality of digital lines corresponding to the plates in the plurality of plates are configured to be coupled in parallel to respective sense amplifiers among the plurality of sense amplifiers, wherein the sense amplifiers among the plurality of sense amplifiers include: An amplifier including an input node configured to be coupled to a digital line among the plurality of digital lines; and A switch configured to couple an output node of the amplifier to a first plate of a capacitor and configured to couple the output node to a second plate of the capacitor, the first plate of the capacitor being coupled to the input node.

9. The memory device according to claim 8, wherein the plurality of plates include a plurality of plate groups, and wherein the plurality of sense amplifiers include respective groups of sense amplifiers for each of the plurality of plate groups, the memory device further including: A plate selection component configured to select a selected plate within each of the plurality of plate groups; And A plurality of multiplexing components, wherein for the selected plate within each of the plurality of plate groups, each multiplexing component among the plurality of multiplexing components is configured to couple all of the plurality of digital lines corresponding to the selected plate in parallel to the respective group of sense amplifiers of the plate group including the selected plate.

10. The memory device according to claim 9, wherein the respective groups of sense amplifiers of the plate groups are configured to sense, in parallel, respective amounts of charge stored by corresponding ferroelectric memory cells for each of the plurality of digital lines corresponding to the selected plate.

11. The memory device according to claim 8, wherein the amplifier includes a differential amplifier, wherein The output node of the differential amplifier is configured to be selectively coupled to the input node of the differential amplifier; and The differential amplifier is configured to pre-charge the digital line at least in part based on a voltage at a second input node of the differential amplifier when the output node of the differential amplifier is coupled to the input node.

12. The memory device according to claim 8, wherein the sense amplifiers among the plurality of sense amplifiers include: A second capacitor coupled to the input node of the amplifier, wherein during an access operation for a ferroelectric memory cell among the corresponding plurality of ferroelectric memory cells, both the capacitor and the second capacitor are configured to share charge with the ferroelectric memory cell.

13. The memory device according to claim 12, wherein the capacitor is configured to be coupled to the output node of the amplifier during a first part of the access operation.

14. The memory device according to claim 13, wherein a first plate of the second capacitor is configured to be set to a first voltage during the first part of the access operation and to a second voltage during a second part of the access operation.

15. The memory device according to claim 8, wherein all of the plurality of digit lines corresponding to the plate are below or above the plate.

16. The memory device according to claim 8, wherein each respective digit line of the plurality of digit lines corresponding to the plate is located between a pair of ground conductive lines configured to electrically isolate the respective digit line from every other digit line of the plurality of digit lines corresponding to the plate.

17. A method for operating a memory device, comprising: activating a plate coupled to a first ferroelectric memory cell and to a second ferroelectric memory cell; selecting a first digit line coupled to the first ferroelectric memory cell and a second digit line coupled to the second ferroelectric memory cell, at least in part based on activating the plate and during the same duration, wherein the first digit line is electrically isolated from the second digit line by a shield line; selecting a word line coupled to the first ferroelectric memory cell while the first digit line and the second digit line are selected; and performing an access operation on the first ferroelectric memory cell when the second digit line is selected.

18. The method according to claim 17, further comprising: selecting the first digit line and the second digit line simultaneously, wherein performing the access operation is at least in part based on selecting the first digit line and the second digit line simultaneously.

19. The method according to claim 17, wherein the plate is coupled to a plurality of ferroelectric memory cells, the method further comprising: selecting the digit lines of each of the plurality of ferroelectric memory cells during the access operation.

20. The method according to claim 17, wherein performing the access operation on the first ferroelectric memory cell comprises: transmitting a first signal along the first digit line; and transmitting a second signal along the second digit line, wherein the shield line includes ground conductive lines configured to isolate the first signal from the second signal.

21. A memory device, comprising: a first digit line coupled to a first ferroelectric memory cell; a second digit line coupled to a second ferroelectric memory cell; a plate common to the first ferroelectric memory cell and the second ferroelectric memory cell; a shield line positioned between the first digit line and the second digit line and configured to electrically isolate the first digit line from the second digit line during an access operation associated with the first ferroelectric memory cell, the second ferroelectric memory cell, or both; and a sense amplifier, comprising: an amplifier including an input node configured to be coupled to the first digit line; and A switch configured to couple an output node of the amplifier to a first plate of a capacitor and configured to couple the output node to a second plate of the capacitor, the first plate of the capacitor being coupled to the input node.

22. The memory device according to claim 21, further comprising: A plurality of digital lines including the first digital line and the second digital line; A plurality of ferroelectric memory cells including the first ferroelectric memory cell and the second ferroelectric memory cell, wherein each ferroelectric memory cell in the plurality of ferroelectric memory cells has a common plate, and wherein each digital line in the plurality of digital lines is coupled to a corresponding ferroelectric memory cell in the plurality of ferroelectric memory cells; And A plurality of shield lines including the shield line, wherein each shield line in the plurality of shield lines is positioned between a corresponding pair of digital lines in the plurality of digital lines and configured to electrically isolate the first digital line in the corresponding pair from the second digital line in the corresponding pair during the access operation.

23. The memory device according to claim 22, wherein each digital line in the plurality of digital lines is configured to be selected in parallel during the access operation.

24. The memory device according to claim 22, wherein each digital line in the plurality of digital lines is configured to transfer data to or from the corresponding ferroelectric memory cell during the access operation.

25. The memory device according to claim 21, wherein the shield line includes a ground conducting wire electrically isolated from each ferroelectric memory cell of the memory device.

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