An imaging device, a sensor, and an electronic device

Abstract

The application provides an imaging device, a sensor and an electronic device. The imaging device comprises a semiconductor substrate, a first well and a second well are arranged on two sides of the semiconductor substrate, a first insulating medium layer, a floating gate and a second insulating medium layer are sequentially arranged on the surface of the semiconductor substrate, the floating gate is arranged in a containing cavity formed between the first insulating medium layer and the second insulating medium layer, the first insulating medium layer is provided with at least one window, and the floating gate and the first well are connected through the window; the second well comprises a channel region, and along a direction away from the channel region, a surface of the channel region is sequentially provided with a first insulating medium layer, a floating gate and a second insulating medium layer. The first well and the floating gate are directly connected through the window, so that the electric charges are directly transferred into the floating gate through the window without the need of being transferred in a tunneling mode, the full well capacity of the imaging device is improved, and then the efficiency of the electric charge transfer and the quality of the obtained image are improved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more particularly to an imaging device, sensor, and electronic device. Background Technology

[0002] Image sensors are devices that convert photoelectrons into electrical signals. Existing technology provides a vertical charge transfer pixel sensor (VPS), which is discussed below. Figure 1 The diagram illustrates a partial structure of an imaging device used to compose a sensor, as provided by the prior art.

[0003] like Figure 1 As shown, the imaging device has a depletion region 101. When light shines on the depletion region 101, the depletion region 101 exhibits a photoelectric effect to generate photoelectrons. Under the action of voltage, the generated photoelectrons move to the interface between the depletion region 101 and the insulating layer 102. The photoelectrons located at the interface between the depletion region 101 and the insulating layer 102 will cause a change in the potential of the storage medium layer 104 through charge coupling. The composite dielectric gate 105 reads the number of photoelectrons by the change in the potential of the storage medium layer 104.

[0004] However, a problem with the existing technology is that if the voltage applied to the depletion region 101 is not large enough, some of the photoelectrons generated in the depletion region 101 will not cause a change in the potential of the storage medium layer 104, thereby reducing the imaging quality of the image sensor. If the photoelectrons generated in the depletion region 101 are to be fully used to change the potential of the storage medium layer 104, a sufficiently large voltage needs to be applied to the depletion region 101, thereby increasing the power consumption of the sensor. Summary of the Invention

[0005] This application provides an imaging device, sensor, and electronic device that can effectively improve charge transfer efficiency to enhance imaging quality.

[0006] A first aspect of this application provides an imaging device, including a semiconductor substrate. A first well and a second well are respectively disposed on both sides of the semiconductor substrate by ion implantation doping. The semiconductor substrate and the second well have a first doping type, and the first well has a second doping type. A first insulating dielectric layer, a floating gate, and a second insulating dielectric layer are sequentially disposed on the surface of the semiconductor substrate. The floating gate is located within a cavity formed between the first and second insulating dielectric layers. The first insulating dielectric layer has at least one opening, and the floating gate and the first well are connected through the opening. The second well includes a channel region. Along a direction away from the channel region, the surface of the channel region is sequentially disposed with the first insulating dielectric layer, the floating gate, and the second insulating dielectric layer. The threshold voltage of the channel region corresponds to the amount of charge stored in the floating gate.

[0007] It is understood that when incident light irradiates the semiconductor substrate and the first well, a photoelectric effect occurs to generate charge. This charge is transferred to the floating gate through the opening provided in the first insulating dielectric layer. The charge stored in the floating gate changes the potential of the floating gate. The floating gate with the changed potential changes the threshold voltage of the channel region accordingly. The amount of charge stored in the floating gate can be obtained by detecting the change in the threshold voltage. The corresponding image can be obtained based on the amount of charge stored in the floating gate.

[0008] The first well and the floating gate are directly connected via the window, so that the charge generated in the first well and the semiconductor substrate is directly transferred to the floating gate via the window. This allows the charge to be fully transferred to the floating gate without applying a high voltage to the first well and the semiconductor substrate, thereby reducing the voltage requirement during the charge transfer process, reducing the power consumption of the imaging device, and improving the charge transfer efficiency to effectively improve the imaging quality.

[0009] Because the charge in the first well is directly transferred to the floating grid through the window, the first insulating dielectric layer is not damaged during the charge transfer process, thereby reducing the requirement for the thickness of the first insulating dielectric layer. Since damage to the first insulating dielectric layer is effectively avoided, the accuracy of the number of charges read and the quality of the image are effectively improved. Moreover, during use, the service life of the imaging device is increased, thus improving the reliability of the imaging device.

[0010] The charge is transferred through a window, so the charge can be fully transferred without applying a sufficiently large voltage to the imaging device, thereby improving the light sensitivity of the imaging device and saving power consumption during the light sensing process.

[0011] Furthermore, since the channel region is located within the second well, the second well can effectively isolate the channel region from the semiconductor substrate. The second well can also effectively isolate the channel region from the first well, effectively preventing charges generated by the semiconductor substrate and the first well from entering the channel region and interfering with it. This effectively improves the accuracy of reading the number of charges, thereby improving the quality of the generated image.

[0012] The floating grid shown in this application covers the first well and the channel region, effectively improving the full well capacity (FWC) of the imaging device and significantly increasing the amount of charge that the imaging device can store.

[0013] Based on the first aspect of the present application, in an optional implementation of the first aspect of the present application, along a direction perpendicular to the imaging device, the window includes a first opening and a second opening disposed opposite to each other, the first opening being located on the surface of the first insulating dielectric layer facing the floating grating, the second opening being located on the surface of the first insulating dielectric layer facing the first well, and the first opening and the second opening being connected.

[0014] It is understood that the windowing enables a direct connection between the first well and the floating grid, increasing the full-well capacity of the imaging device, thereby improving the efficiency of charge transfer and the quality of the acquired image. The windowing also prevents damage to the first insulating dielectric layer during charge transfer, thus reducing the requirement for the thickness of the first insulating dielectric layer. Because damage to the first insulating dielectric layer is effectively avoided, the accuracy of the read charge quantity and the image quality are effectively improved. Furthermore, the lifespan of the imaging device is extended during use, resulting in improved reliability.

[0015] Based on the first aspect of the present application, in an optional implementation of the first aspect of the present application, an isolation medium layer is disposed between the first insulating medium layer and the first well, and the isolation medium layer is a high-density P-ion implantation medium.

[0016] It is understandable that because an isolation dielectric layer is provided between the first well and the first insulating dielectric layer, the first well and the first insulating dielectric layer are effectively isolated, the generation of dark current is reduced, the influence of dark current on the reading of the amount of charge stored in the floating gate is avoided, the accuracy of reading the amount of charge is improved, and thus the image quality is improved.

[0017] Based on the first aspect of the present application, in an optional implementation of the first aspect of the present application, the cross-sectional area of ​​the first well is larger than the cross-sectional area of ​​the second well along the lateral direction of the imaging device.

[0018] It is understandable that because the cross-sectional area of ​​the first well is larger than that of the second well, the photosensitive area used for photosensitive reaction to generate charge during the exposure period is effectively increased. It can be seen that when the photosensitive area of ​​the imaging device is increased, the photosensitive sensitivity of the imaging device is effectively increased.

[0019] Based on the first aspect of the present application, in an optional implementation of the first aspect of the present application, the source and drain are respectively disposed by ion implantation doping on both sides of the second well facing the end face of the first insulating dielectric layer, the source and drain having the second doping type, and the channel region is located between the source and the drain along the lateral direction of the imaging device.

[0020] Based on the first aspect of the present application, in an optional implementation of the first aspect of the present application, a control gate is provided on the surface of the second insulating dielectric layer away from the floating gate, the control gate, the source and the drain are respectively connected to a logic control circuit, and the logic control circuit is used to apply voltage to the control gate, the source and the drain.

[0021] Specifically, during the exposure period, the logic control circuit applies an exposure voltage to the control gate and applies a zero-bias or negative-bias voltage to the semiconductor substrate, causing the gate and source of the readout transistor to float, thus forming a depletion layer in the semiconductor substrate and the first well. When incident light irradiates the depletion layer, charge is generated. During the transfer period, the charge generated in the depletion layer is transferred towards the floating gate under the drive of the control gate voltage. When the charge reaches the interface of the first well, it enters the floating gate through the opening. As the charge is transferred into the floating gate, the potential of the floating gate begins to decrease due to the accumulation of charge, and the change in the potential of the floating gate is proportional to the number of photoelectrons accumulated. During the readout period, the storage of charge in the floating gate causes a change in the threshold voltage in the channel region. By measuring the threshold voltage before and after exposure, the logic control circuit can calculate the change in the floating gate potential, thereby calculating the amount of charge, and thus acquire the corresponding image. During the readout period, the logic control circuit applies a zero-bias voltage to the source and drain, so that the channel region does not affect the collection of charge by the semiconductor substrate and the first well.

[0022] Based on the first aspect of the present application, in an optional implementation of the first aspect of the present application, the floating gate extends along the guide of the window to the second opening via the first opening, and the floating gate located at the second opening is connected to the first sink.

[0023] It is understood that after the first insulating dielectric layer is set, a window can be set directly through the first insulating dielectric layer, and then a floating gate can be directly deposited on the surface of the first insulating dielectric layer by means such as chemical vapor deposition (CVD), so that the floating gate deposited in the window is directly connected to the first well.

[0024] Based on the first aspect of the present application, in an optional implementation of the first aspect of the present application, the first well extends along the guide of the window to the first opening via the second opening, and the floating gate located at the first opening is connected to the first well.

[0025] Based on the first aspect of the present application, in an optional implementation of the first aspect of the present application, the floating gate extends into the interior of the window via the first opening, the first sink extends into the interior of the window via the second opening, and the floating gate located inside the window and the first sink are connected.

[0026] Based on the first aspect of the embodiments of this application, in one optional implementation of the first aspect of the embodiments of this application, the first doping type is n-type impurity doping and the second doping type is p-type impurity doping; or, the first doping type is p-type impurity doping and the second doping type is n-type impurity doping.

[0027] A second aspect of this application provides an imaging device, including a semiconductor substrate. A first well and a second well are respectively disposed on both sides of the semiconductor substrate by ion implantation doping. The semiconductor substrate and the second well have a first doping type, and the first well has a second doping type. A first insulating dielectric layer, a floating gate, and a second insulating dielectric layer are sequentially disposed on the surface of the semiconductor substrate. The floating gate is located in a receiving cavity formed between the first insulating dielectric layer and the second insulating dielectric layer. The first insulating dielectric layer is provided with at least one opening, and the floating gate and the first well are connected through the opening.

[0028] For a detailed explanation of the beneficial effects shown in this aspect, please refer to the first aspect above; further details will not be elaborated upon here.

[0029] Based on the second aspect of the present application, in an optional implementation of the second aspect of the present application, the second well includes a channel region, and along a direction away from the channel region, the surface of the channel region is sequentially provided with the first insulating dielectric layer, the floating gate and the second insulating dielectric layer, and the magnitude of the threshold voltage of the channel region corresponds to the amount of charge stored in the floating gate.

[0030] Based on the second aspect of the present application, in an optional implementation of the second aspect of the present application, along a direction perpendicular to the imaging device, the window includes a first opening and a second opening disposed opposite to each other, the first opening being located on the surface of the first insulating dielectric layer facing the floating gate, the second opening being located on the surface of the first insulating dielectric layer facing the first well, and the first opening and the second opening being connected.

[0031] Based on the second aspect of the present application, in an optional implementation of the second aspect of the present application, an isolation medium layer is disposed between the first insulating medium layer and the first well, and the isolation medium layer is a high-density P-ion implantation medium.

[0032] Based on the second aspect of the present application, in an optional implementation of the second aspect of the present application, the cross-sectional area of ​​the first well is larger than the cross-sectional area of ​​the second well along the lateral direction of the imaging device.

[0033] Based on the second aspect of the present application, in an optional implementation of the second aspect of the present application, the source and drain are respectively disposed by ion implantation doping on both sides of the second well facing the end face of the first insulating dielectric layer, the source and drain having the second doping type, and the channel region is located between the source and the drain along the lateral direction of the imaging device.

[0034] Based on the second aspect of the present application, in an optional implementation of the second aspect of the present application, a control gate is provided on the surface of the second insulating dielectric layer away from the floating gate, the control gate, the source and the drain are respectively connected to a logic control circuit, and the logic control circuit is used to apply voltage to the control gate, the source and the drain.

[0035] Based on the second aspect of the present application, in an optional implementation of the second aspect of the present application, the floating gate extends along the guide of the window to the second opening via the first opening, and the floating gate located at the second opening is connected to the first sink.

[0036] Based on the second aspect of the present application, in an optional implementation of the second aspect of the present application, the first well extends along the guide of the window to the first opening via the second opening, and the floating gate located at the first opening is connected to the first well.

[0037] Based on the second aspect of the present application, in an optional implementation of the second aspect of the present application, the floating gate extends into the interior of the window via the first opening, the first sink extends into the interior of the window via the second opening, and the floating gate located inside the window and the first sink are connected.

[0038] Based on the second aspect of the embodiments of this application, in one optional implementation of the second aspect of the embodiments of this application, the first doping type is n-type impurity doping and the second doping type is p-type impurity doping; or, the first doping type is p-type impurity doping and the second doping type is n-type impurity doping.

[0039] A third aspect of this application provides an image sensor, which includes a pixel array and a logic control circuit. The pixel array includes at least one imaging device, which is electrically connected to the logic control circuit. The imaging device is as described in the first or second aspect above. The logic control circuit is used to generate a corresponding image based on the amount of charge stored in the floating grating.

[0040] A fourth aspect of this application provides an electronic device, the electronic device including a processor and an image sensor, the image sensor being as described in the third aspect above, and the processor being used to acquire the image from the image sensor. Attached Figure Description

[0041] Figure 1 Example diagram of the structure of an imaging device provided by the prior art;

[0042] Figure 2 An example structural diagram of an embodiment of the electronic device provided in this application;

[0043] Figure 3 This is an example diagram illustrating the structure of one embodiment of the pixel array provided in this application;

[0044] Figure 4 This is a side cross-sectional view of an embodiment of the photosensitive transistor provided in this application.

[0045] Figure 5 This is a side view cross-sectional structural example of an embodiment of the imaging device provided in this application;

[0046] Figure 6 This is an example side cross-sectional view of one embodiment of the readout transistor provided in this application;

[0047] Figure 7 This is an example of a side cross-sectional view of another embodiment of the imaging device provided in this application;

[0048] Figure 8 This is a transfer example diagram of one embodiment of the optoelectronics provided in this application. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] This application provides an imaging device. To better understand the imaging device provided in this application, the structure of an electronic device including the imaging device will be described by way of example below:

[0051] like Figure 2 As shown, electronic device 20 can be any electronic device equipped with a camera, including but not limited to smartphones, mobile computers, tablets, personal digital assistants (PDAs), etc. Figure 2 As shown, the electronic device 20 includes, but is not limited to, components such as an image sensor 200, a processor 210, a display 220, a communication unit 260, a storage unit 270, a radio frequency circuit 240, and a power supply 250.

[0052] Optionally, the processor 210 may be one or more of the following processors: central processing unit (CPU), image signal processor (ISP), graphics processing unit (GPU), and digital signal processor (DSP).

[0053] Image sensor 200 may include pixel array 201 and logic control circuit 202. Specifically, pixel array 201 may consist of individual imaging devices, each corresponding to one or more pixels in the image displayed on display 230. Each imaging device in pixel array 201 can be independent of the others. Specifically, when external light shines on pixel array 201, the imaging devices on pixel array 201 undergo photoelectric effect, generating a corresponding charge within each imaging device. Logic control circuit 202 acquires the image based on the corresponding charge generated within each imaging device. More specifically, logic control circuit 202 is used to control and exchange data with pixel array 201. For example, before the image sensor is exposed to light, logic control circuit sends a command to reset each imaging device included in the pixel array. Afterward, logic control circuit 202 exposes pixel array 201. After exposure, logic control circuit 202 reads and analyzes the charge quantity of each imaging device in pixel array 201 to obtain the image.

[0054] The logic control circuit 202 may include a processing device for controlling the pixel array to generate charges and generate corresponding images. The processing device may be one or more field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), system-on-chips (SoCs), central processors (CPUs), network processors (NPs), digital signal processors (DSPs), microcontrollers (MCUs), programmable logic devices (PLDs), or other integrated chips, or any combination of the above chips or processors.

[0055] The image sensor 200 can be controlled by the processor 210, which can output the image sensed and output by the image sensor 200 to the display 230. The display 230 can be a display panel configured as a liquid crystal display (LCD), an organic light-emitting diode (OLED), a field emission display (FED), or the like.

[0056] Storage unit 270 is used to store code and data, with the code being executed by processor 210. In this embodiment, storage unit 270 may include volatile memory or non-volatile memory.

[0057] Communication unit 260 is used to establish a communication channel, enabling electronic devices to connect to a remote server through the communication channel and download media data from the remote server. Communication unit 260 may include communication modules such as a wireless local area network (WLAN) module, a Bluetooth module, and a baseband module, as well as radio frequency (RF) circuits corresponding to the communication modules, for performing WLAN communication, Bluetooth communication, infrared communication, and / or cellular communication system communication.

[0058] Radio frequency (RF) circuit 240 is used to receive and transmit signals during information transmission or calls. For example, it receives downlink information from the base station and processes it with processor 210; additionally, it transmits uplink data to the base station. Typically, the RF circuit 240 includes known circuitry for performing these functions, including but not limited to antenna systems, RF transceivers, one or more amplifiers, tuners, one or more oscillators, digital signal processors, codec chipsets, subscriber identification modules (SIM) cards, memory, etc. Furthermore, the RF circuit 240 can also communicate wirelessly with networks and other devices.

[0059] Power supply 250 is used to supply power to various components of an electronic device to maintain its operation. Generally understood, power supply 250 can be a built-in battery, such as a common lithium-ion battery or nickel-metal hydride battery, or an external power source that directly supplies power to the electronic device, such as an alternating current (AC) adapter. In some embodiments of the invention, power supply 250 can also be defined more broadly, for example, including a power management system, a charging system, a power fault detection circuit, a power converter or inverter, a power status indicator (such as a light-emitting diode), and any other components associated with the generation, management, and distribution of electrical energy in the electronic device.

[0060] The following combination Figure 3 The following is an exemplary description of the specific structure of the pixel array provided in this application, wherein, Figure 3 This is a top view of an embodiment of the pixel array provided in this application.

[0061] like Figure 3As shown, the pixel array 300 includes multiple imaging devices 301, and further includes a word line set 310, a bit line set 320, and a source line set. The source line set includes multiple source lines, and any one of the source lines is perpendicular to the pixel array 300. Figure 3 The source lines are not shown. The word line set 310 includes multiple word lines, such as... Figure 3 The word lines 3101, 3102, 3103, and 310y shown are not limited in number (y) of the word lines in the word line set 310 in this embodiment, as long as y is a positive integer greater than 1; the bit line set 320 includes multiple bit lines, such as... Figure 3 The bit lines 3201, 3202, and 320x shown in the figure are not limited in number (x) of the bit line set 320 in this embodiment, as long as x is a positive integer greater than 1. Specifically, any one of the multiple source lines is connected to an imaging device included in the pixel array 300, any one of the word lines included in the word line set 310 is connected to an imaging device included in the pixel array 300, and any one of the bit lines in the bit line set 320 is connected to an imaging device included in the pixel array 300. Thus, any imaging device included in the pixel array 300 is connected to a bit line in the bit line set 302, a word line in the word line set 310, and any one of the source lines in the source line set. Any imaging device is coupled to a logic control circuit through the bit lines, word lines, and source lines. The logic control circuit can then control the exposure of any one or more imaging devices in the pixel array 300 to generate charge through the bit lines, word lines, and source lines. The logic control circuit can acquire the corresponding image by obtaining the corresponding amount of charge.

[0062] The following provides an exemplary description of the specific structure of the imaging device provided in this embodiment. Specifically, the imaging device shown in this embodiment includes a photosensitive transistor and a readout transistor connected together. When incident light shines on the photosensitive transistor, a photoelectric effect occurs to generate charge. The amount of charge stored in the photosensitive transistor causes a change in the threshold voltage of the readout transistor. The logic control circuit connected to the imaging device can calculate the amount of charge stored in the photosensitive transistor by the change in the threshold voltage generated by the readout transistor, and thus acquire the corresponding image.

[0063] For better understanding, the following will be combined with Figures 4 to 6 The specific structures of the photosensitive transistor and the readout transistor are illustrated by way of example, wherein, Figure 4 This is an example of a side cross-sectional view of the photosensitive transistor provided in this application. Figure 5 This is an example of a side-view cross-sectional structure of the imaging device provided in this application. Figure 6 This is an example of a side cross-sectional view of the readout transistor provided in this application.

[0064] The connection method between the photosensitive transistor and the readout transistor is first described by way of example:

[0065] The photosensitive transistor 400 and the readout transistor 500 shown in this embodiment both have the same semiconductor substrate 401, so that the photosensitive transistor 400 and the readout transistor 500 are connected through the same semiconductor substrate 401;

[0066] The semiconductor substrate 401 that enables the connection between the photosensitive transistor 400 and the readout transistor 500 is described below by way of example:

[0067] The semiconductor substrate 401 shown in this embodiment has a first doping type. Optionally, the first doping type is n-type impurity doping. Specifically, the semiconductor substrate 401 is made of pure silicon crystal, and a pentavalent element (such as phosphorus) is doped into the silicon crystal, so that the doped phosphorus replaces the positions of silicon atoms in the semiconductor substrate 401, thus forming an n-type semiconductor substrate. The free electron concentration of the n-type semiconductor substrate is much greater than that of the impurity semiconductor with a higher hole concentration. Moreover, the more impurities doped into the semiconductor substrate 401, the higher the free electron concentration of the semiconductor substrate 401, and the stronger the conductivity. Alternatively, the first doping type is p-type impurity doping. Specifically, the semiconductor substrate 401 is made of pure silicon crystal, and a trivalent element (such as boron) is doped into the silicon crystal, so that the doped boron replaces the positions of silicon atoms in the semiconductor substrate 401, thus forming a p-type semiconductor substrate. The hole concentration of the p-type semiconductor substrate is greater than that of the impurity semiconductor with a higher free electron concentration. Moreover, the more impurities doped into the semiconductor substrate 401, the higher the hole concentration of the semiconductor substrate 401, and the stronger the conductivity. This embodiment uses silicon as an example to illustrate the concept, but it is not limited to silicon. In other examples, the semiconductor substrate 401 may also be made of germanium. In this embodiment, p-type semiconductor substrate 401 is used as an example to illustrate the concept.

[0068] The process by which the photosensitive transistor 400 generates corresponding charges based on incident light is described below:

[0069] Optionally, the photosensitive transistor 400 shown in this embodiment includes a photodiode (PD). The photodiode included in the photosensitive transistor 400 is used to generate corresponding charges according to the incident light. More specifically, the photodiode for photosensing shown in this embodiment includes a first well 402 and the semiconductor substrate 401. Specifically, if the semiconductor substrate 401 is a p-type semiconductor substrate, the charge generated by the photodiode is photoelectrons; if the semiconductor substrate 401 is an n-type semiconductor substrate, the charge generated by the photodiode is holes. This embodiment uses the example of the charge generated by the photodiode being photoelectrons for illustrative purposes.

[0070] The first well 402 included in the photodiode is described below by way of example:

[0071] Specifically, in this embodiment, a first ion implantation doping is performed on the first side of the semiconductor substrate 401 to form the first well 402, so as to... Figure 4 Taking the left side of the semiconductor substrate 401 as an example, the first well 402 can be formed by first ion implantation doping on the left side of the semiconductor substrate 401.

[0072] Optionally, if the first ion is a trivalent element (such as boron), the formed first well 402 is a PWELL; if the first ion is a pentavalent element (such as phosphorus), the formed first well 402 is an NWELL. In this embodiment, to form the photodiode capable of photosensitive operation, if the first doping type of the semiconductor substrate 401 is p-type impurity doping, then the first ion is a boron ion; if the first doping type of the semiconductor substrate 401 is n-type impurity doping, then the first ion is a phosphorus ion. This embodiment uses a p-type substrate as an example for illustrative purposes.

[0073] The photosensitive transistor 400 shown in this embodiment needs to store the photoelectrons generated by the photodiode. The following is an exemplary description of how the photosensitive transistor specifically stores the photoelectrons generated by photosensitive light:

[0074] Specifically, in this embodiment, a first insulating dielectric layer 403, a floating gate 404 for storing photoelectrons, a second insulating dielectric layer 405, and a control gate 406 may be sequentially disposed above the first well 402.

[0075] The first insulating dielectric layer 403 shown in this embodiment has an insulating function. This embodiment does not limit the specific material of the first insulating dielectric layer 403, as long as it is a dielectric with a high dielectric constant. For example, the material of the first insulating dielectric layer 403 can be one or a combination of silicon oxide, silicon oxynitride (SiON), silicon nitride, and aluminum oxide. The material of the second insulating dielectric layer 405 can be the same as or different from the material of the first insulating dielectric layer 403, as long as the second insulating dielectric layer 405 is also a dielectric with a high dielectric constant.

[0076] In this embodiment, to improve the performance of the floating gate 404 in storing photoelectrons, a receiving cavity is formed between the first insulating dielectric layer 403 and the second insulating dielectric layer 405. The floating gate 404 is disposed inside the receiving cavity, so that the floating gate 404 is located between the first insulating dielectric layer 403 and the second insulating dielectric layer 405, so that the first insulating dielectric layer 403 and the second insulating dielectric layer 405 can effectively isolate the floating gate 404, so that the photoelectrons are confined within the floating gate 404 to realize the photoelectron storage function. The floating gate 404 shown in this embodiment can be a broadband semiconductor, such as polycrystalline silicon, silicon nitride (Si3N4), or other electronic conductors or semiconductors. The floating gate 404 shown in this embodiment effectively ensures that photoelectrons can enter the floating gate 404 and be stored within the floating gate 404.

[0077] The control gate 406 shown in this embodiment is used to interact with... Figure 3 The word lines shown are connected so that Figure 2 The logic control circuit shown can apply a voltage to the control gate 406 during the exposure time period through word lines. The control gate 406 shown in this embodiment can be made of polycrystalline silicon, metal, or other electrodes with conductive functions.

[0078] The following is an exemplary description of how the photoelectrons generated by the photodiode are transferred to the floating gate 404 for storage:

[0079] To enable the photoelectrons generated by the photodiode to be stored in the floating gate 404, a window 409 is provided through the first insulating layer 403 in a direction perpendicular to the imaging device. This embodiment does not limit the specific number of windows 409; that is, the number of windows 409 can be one or more. Figure 4As shown in the example, an imaging device includes a window 409. Specifically, along a direction perpendicular to the imaging device, the window 409 includes a first opening 4091 and a second opening 4092 disposed opposite to each other. The first opening 4091 is located on the surface of the first insulating dielectric layer 403 facing the floating gate 404, and the second opening 4092 is located on the surface of the first insulating dielectric layer 403 facing the first well 402, and the first opening 4091 and the second opening 4092 are connected.

[0080] In this embodiment, to enable the photoelectrons generated by the photodiode to be stored in the floating gate 404 via the window 409, the first well 402 can be connected to the floating gate 404 through the window 409. The specific connection method is illustrated below:

[0081] Method 1

[0082] The medium of the floating gate 404 extends through the first opening 4091 along the guide of the window 409 to the second opening 4092, and the connection between the floating gate 404 and the first sink 402 is realized at the second opening 4092.

[0083] Method 2

[0084] The medium of the first sink 402 extends through the second opening 4092 along the guide of the window 409 to the first opening 4091, and the connection between the floating gate 404 and the first sink 402 is realized at the first opening 4091.

[0085] Method 3

[0086] The medium of the floating grid 404 extends into the interior of the window 409 through the first opening 4091, and the medium of the first sink 402 extends into the interior of the window 409 through the second opening 4092, so that the floating grid 404 and the first sink 402 within the window 409 are connected. This method does not limit the thickness of the floating grid 404 and the first sink 402 within the window 409, as long as the floating grid 404 and the first sink 402 can be connected.

[0087] The above description provides an illustrative example of the specific structure of the photosensitive transistor 400 in the imaging device. The following description, in conjunction with... Figure 5 and Figure 6The specific structure of the read transistor 500 is illustrated by way of example. It should be noted that the description of the structure of the read transistor 500 in this embodiment is an optional example, as long as the read transistor 500 can read the number of photoelectrons stored in the floating gate 404. For example, the read transistor shown in this embodiment can be a metal-oxide-semiconductor field-effect transistor (MOSFET), a v-groove metal-oxide semiconductor (VMOS), a vertical double-diffused MOSFET (VDMOSFET), or a lateral double-diffused MOSFET (LDMOSFET).

[0088] As shown above, the photosensitive transistor 400 and the readout transistor 500 share the same semiconductor substrate 401. In this embodiment, a second ion implantation doping can be performed on the second side of the semiconductor substrate 401 to form a second well 502. In the example above where the first side is the left side of the semiconductor substrate 401, the second side shown in this example is the right side of the semiconductor substrate 401. Figure 5 and Figure 6 As shown in the example, a second ion implantation doping is performed on the right side of the semiconductor substrate 401 to form a second well 502.

[0089] Specifically, in this embodiment, the doping types of the first well 402 and the second well 502 are different. If the first ion is a trivalent element (such as boron), the first well 402 formed is PWELL; if the second ion is a pentavalent element (such as phosphorus), the second well 502 formed is NWELL. Similarly, if the first ion is phosphorus, the first well 402 formed is NWELL; if the second ion is boron, the second well 402 formed is PWELL. Since this embodiment takes the first well 402 as NWELL, the second well 502 in this example is PWELL. Because the doping types of the first well 402 and the second well 502 are different, the photoelectrons generated by the photodiode will not enter the second well 502, thus preventing photoelectrons from flowing into the second well 502 and affecting the accuracy of the number of photoelectrons read by the read transistor 500.

[0090] Optional, continue as follows Figure 5As shown in the figure, the second well 502 in this embodiment has a read electrode 503 disposed on the surface facing the first insulating dielectric layer 403. The following is in conjunction with Figure 6 The specific structure of the read electrode 503 is illustrated below:

[0091] Specifically, in this embodiment, a source 5031 and a drain 5032 can be formed by ion implantation doping on the surface of the second well 502 facing the first insulating dielectric layer 403. The source 5031 and the drain 5032 can be p-type or n-type. This embodiment does not limit the dielectric type of the source 5031 and the drain 5032, as long as the doping type of the source 5031 and the drain 5032 is different from the doping type of the second well 502. For example, if the doping type of the second well 502 is p-type, then the doping type of the source 5031 and the drain 5032 is n-type.

[0092] Specifically, the source electrode 5031 and Figure 3 The drain 5032 is connected to one of the source lines in the source line set shown. Figure 3 Connect one bit line from the set of bit lines shown so that Figure 2 The logic control circuit shown can apply voltage to the source 5031 via the source line and to the drain 5032 via the bit line.

[0093] As shown in this embodiment, a channel region 504 is formed between the source electrode 5031 and the drain electrode 5032 along the lateral direction of the imaging device. To achieve the purpose of reading the number of photoelectrons stored in the floating gate 404, in this embodiment, along the direction away from the channel region 504, the surface of the channel region 504 is sequentially provided with a first insulating dielectric layer 403, the floating gate 404, the second insulating dielectric layer 405, and the control gate 406. For a detailed description of the first insulating dielectric layer 403, the floating gate 404, the second insulating dielectric layer 405, and the control gate 406, please refer to the above description; further details are not repeated in this embodiment. It can be seen that the first insulating dielectric layer 403, the floating gate 404, the second insulating dielectric layer 405, and the control gate 406 shown in this embodiment are all disposed above the first well 402 and the second well 502.

[0094] Specifically, the surface of the channel region 504 is covered with the first insulating dielectric layer 403, and the surface of the first insulating dielectric layer 403 is covered with a floating grid 404, so that the floating grid 404 can cover the channel region 504 in a direction perpendicular to the imaging device.

[0095] As shown above, in order for the read transistor 500 to obtain the number of photoelectrons stored in the floating gate 404 of the photosensitive transistor 400, the photoelectrons stored in the floating gate 404 need to change the threshold voltage of the channel region 504 of the read transistor 500. Specifically, since the number of photoelectrons stored in the floating gate 404 will change the potential of the floating gate 404, that is, the change in the potential of the floating gate 404 is proportional to the number of photoelectrons stored in the floating gate 404, the channel region 504 obtains the change in the potential of the floating gate 404, thereby causing the threshold voltage of the channel region 504 to change. That is, the magnitude of the threshold voltage of the channel region 504 corresponds to the amount of charge stored in the floating gate 404. In order for the channel region 504 of the read transistor 500 to obtain the change in the potential of the floating gate 404, the floating gate 404 needs to be covered above the channel region 504.

[0096] The above example illustrates the situation by exemplifying that the channel region 504 is disposed within the second well 502. Because the channel region 504 is located within the second well 502, the second well 502 effectively isolates the channel region 504 from the photodiode, effectively preventing photoelectrons generated by the photodiode from entering the channel region 504 and interfering with it. This, in turn, improves the accuracy of reading the amount of charge generated by the photodiode, thereby enhancing the quality of the generated image. It should be noted that in other examples, the channel region 504 can also be disposed outside the second well 502, as long as the floating gate 404 covers and is disposed above the channel region 504, so that changes in the potential of the floating gate 404 can alter the threshold voltage of the channel region 504.

[0097] To prevent photoelectrons generated by the photodiode from entering the read transistor 500 and causing errors in the number of photoelectrons read by the read transistor 500, a shallow trench isolation (STI) 510 is provided between the photosensitive transistor 400 and the read transistor 500 in this embodiment. Specifically, STI 510 is formed by creating a shallow trench and filling it with oxide or nitride to isolate the photosensitive transistor 400 and the read transistor 500 from interfering with each other. This embodiment does not limit the location of the STI 510. For example, the STI 510 can be located within the first well 402 and facing the side of the second well 502; alternatively, the STI 510 can be located between the first well 402 and the second well 502; or alternatively, the STI 510 can be located within the second well 502 and facing the side of the first well 402. The specific arrangement is not limited in this embodiment, as long as the STI 510 ensures that photoelectrons do not enter the read transistor 500.

[0098] The following combination Figure 7 As shown, this embodiment provides an exemplary description of how the imaging device 500 effectively reduces the influence of dark current:

[0099] First see Figure 5 The following explains the dark current. In the photosensitive transistor 400, when there is no light illumination, the current flowing between the first well 402 and the first insulating dielectric layer 403 is the dark current. The dark current interferes with the number of photoelectrons read by the read transistor 500 and stored in the floating gate 404. To reduce the impact of the dark current on the number of photoelectrons read by the read transistor, the following is... Figure 7 As shown in this embodiment, an isolation dielectric layer 700 is provided between the first well 402 and the first insulating dielectric layer 403.

[0100] This embodiment does not limit the specific material of the isolation dielectric layer 700, as long as the isolation dielectric layer 700 can function to isolate the first well 402 and the first insulating dielectric layer 403. For example, the isolation dielectric layer 700 can be a high-density P ion implantation medium. The isolation dielectric layer 700 can effectively isolate the first well 402 and the first insulating dielectric layer 403, thereby effectively reducing the interference of the dark current between the first well 402 and the first insulating dielectric layer 403 on the read transistor 500.

[0101] Optionally, along the lateral direction of the imaging device, the cross-sectional area of ​​the photosensitive transistor 400 is larger than the cross-sectional area of ​​the readout transistor 500. Specifically, the cross-sectional area of ​​the first well 402 is larger than the cross-sectional area of ​​the second well 502, thereby effectively increasing the photosensitive area of ​​the imaging device shown in this embodiment, and thus effectively increasing the photosensitive sensitivity of the imaging device.

[0102] The electrical connection relationships of the pixel array shown in this embodiment are described below:

[0103] The following combination Figure 3 and Figure 5 The following explanation is provided:

[0104] In this embodiment, all read transistors 500 included in the pixel array 300 are interconnected using flash NOR, so that the logic control circuit shown in this embodiment can control the mutually perpendicular bit lines and word lines to perform XY addressing reads of all imaging devices included in the pixel array 300.

[0105] During the exposure period, the logic control circuit controls the source lines connected to all imaging devices included in the pixel array 300 to be grounded, which can effectively prevent the readout transistor 500 from interfering with the photosensitive transistor 400 during the exposure period.

[0106] In this embodiment, all photosensitive transistors included in the pixel array 300 are interconnected using NAND flash memory, so that the photosensitive transistors 400 of each imaging device are independent. This ensures that even if one photosensitive transistor 400 fails, it will not affect the normal operation of other photosensitive transistors 400 in the pixel array.

[0107] Optional, continue as follows Figure 5 As shown, isolation layers 511 are provided on both sides of the imaging device to achieve isolation from surrounding imaging devices. The isolation layers 511 can be formed by STI or by local oxidation of silicon (LOCOS) technology. In this embodiment, no specific limitation is made.

[0108] The photosensitive transistor 400 shown in this embodiment is used to realize the transfer and storage of photoelectrons. The following is in conjunction with... Figure 5 and Figure 8 The following is an exemplary illustration of the specific process:

[0109] First, the logic control circuit shown in this embodiment pre-sets an imaging cycle. One imaging cycle includes an exposure time period, a transfer time period, a readout time period, and a reset time period arranged sequentially. This embodiment does not limit the duration of each time period, which will be explained in detail below:

[0110] During the exposure period, the logic control circuit applies an exposure voltage to the control gate 406, which is a zero bias voltage or a very small positive bias voltage (such as between 0V and 1V), and applies a zero bias voltage or a negative bias voltage to the semiconductor substrate, causing the gate and source of the read transistor to float, so as to form a depletion layer 800 in the photodiode.

[0111] When incident light shines into the depletion layer 800, the photoelectric effect can occur in the depletion layer 800, that is, the photons of the incident light are absorbed to generate photoelectrons 801.

[0112] This embodiment does not limit the direction in which the incident light illuminates the pixel array; it is optional, such as... Figure 5 As indicated by arrow 507, the light sequentially passes through control gate 406, second insulating dielectric layer 405, floating gate 404, and first insulating dielectric layer 403 to illuminate the photodiode; optionally, it continues as follows... Figure 5 As indicated by arrow 508, the light directly illuminates the photodiode. The number of photoelectrons generated by the photodiode is positively correlated with the intensity of the incident light and / or the duration of illumination.

[0113] During the transfer period, the photoelectrons 801 generated in the depletion layer 800 are transferred in the direction toward the floating gate 404 under the drive of the voltage of the control gate 406. When the photoelectrons 801 move to the interface of the first well 402, they enter the floating gate 404 through the opening 409.

[0114] When photoelectrons 801 are transferred to the floating gate 404, the potential of the floating gate 404 begins to decrease slowly due to the accumulation of photoelectrons 801, and the change in the potential of the floating gate 404 is proportional to the number of photoelectrons accumulated.

[0115] During the reading period, after the floating gate 404 stores the photoelectron 801, it will cause the reading transistor 500 to generate a change in threshold voltage. The logic control circuit can calculate the change in potential of the floating gate 404 by measuring the threshold voltage before and after exposure, and thus calculate the number of photoelectrons.

[0116] Once the logic control circuit obtains the number of photoelectrons stored in the photosensitive transistor 400, it can acquire the corresponding image.

[0117] During the reading period, the logic control circuit applies zero bias to the source and drain of the read transistor 500, so that the read transistor 500 does not affect the photosensitive transistor 400's collection of photoelectrons.

[0118] During the reset period, the logic control circuit applies a negative bias voltage to the gate of the read transistor 500, and the semiconductor substrate 401 is positively biased. The source and the semiconductor substrate are both positively biased, thereby causing photoelectrons in the floating gate 404 to be swept out of the floating gate 404, or holes in the semiconductor substrate 401 to be swept into the floating gate 404 through the opening, so that the photoelectrons and holes stored in the floating gate 404 recombine and disappear.

[0119] The following describes the beneficial effects of the imaging device provided in this application:

[0120] The imaging device shown in this embodiment includes a phototransistor and a readout transistor. The photodiode in the phototransistor generates photoelectrons through the photoelectric effect. The photodiode in this embodiment includes a semiconductor substrate and a first well. A first insulating dielectric layer between the first well and the floating gate has a window, allowing the floating gate and the first well to connect through this window. The photoelectrons generated by the photodiode are transferred to the floating gate through the window in the first insulating dielectric layer. The photoelectrons stored in the floating gate change the potential of the floating gate, allowing the readout transistor to read the number of photoelectrons based on the changed potential. This window-based process of photoelectron flow to the floating gate allows for sufficient charge transfer to the floating gate without applying a high voltage to the photodiode. This reduces the voltage requirement during charge transfer, lowers the power consumption of the imaging device, and improves charge transfer efficiency, effectively improving image quality. This enhances the photosensitivity of the imaging device and saves power consumption during the photosensitivity process.

[0121] If photoelectron transfer is achieved through tunneling, a certain thickness of the insulating dielectric layer is required to allow the photoelectrons to tunnel into the photoelectron storage dielectric layer. In the imaging device of this application, photoelectrons flow into the floating gate through a window, thereby reducing the thickness of the insulating dielectric layer and improving the reliability of the imaging device. Furthermore, if photoelectrons change the potential of the storage dielectric layer through tunneling, high-energy photoelectrons can easily damage the underlying insulating dielectric layer, leading to errors in the number of photoelectrons read by the read transistor. However, the photoelectrons in this application do not need to tunnel through the first insulating dielectric layer; they can flow directly into the floating gate through the pre-set window. Therefore, even if the photoelectrons have high energy, they do not need to tunnel through the first insulating dielectric layer, thus avoiding damage to the first insulating dielectric layer and improving the accuracy of the number of photoelectrons read by the read transistor stored in the floating gate.

[0122] The floating grating shown in this application covers the entire area of ​​a single imaging device, effectively providing FWC and significantly increasing the number of photoelectrons that the photosensitive transistor can store.

[0123] In the imaging device shown in this application, an isolation dielectric layer can be provided between the first well and the first insulating dielectric layer, thereby effectively isolating the first well and the first insulating dielectric layer, reducing the generation of dark current, and avoiding the influence of dark current on the number of photoelectrons read by the readout transistor stored in the floating gate.

[0124] When the image sensor provided in this application is applied to a terminal, such as a smartphone, the imaging device can be made to be less than 0.7µm. The imaging device shown in this application can meet the requirements of full-well capacity while also meeting the requirements of miniaturization of the imaging device.

[0125] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0126] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection between apparatuses or units through some interfaces, and may be electrical, mechanical, or other forms.

[0127] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0129] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0130] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An imaging device, characterized in that, The semiconductor substrate includes a first well and a second well formed on both sides of the semiconductor substrate by ion implantation doping. The semiconductor substrate and the second well have a first doping type, and the first well has a second doping type. The surface of the semiconductor substrate is sequentially provided with a first insulating dielectric layer, a floating gate, and a second insulating dielectric layer. The floating gate is located in a receiving cavity formed between the first insulating dielectric layer and the second insulating dielectric layer. The first insulating dielectric layer is provided with at least one window, and the floating gate and the first well are connected through the window. The second well includes a channel region. Along a direction away from the channel region, the surface of the channel region is sequentially provided with the first insulating dielectric layer, the floating gate, and the second insulating dielectric layer. The magnitude of the threshold voltage of the channel region corresponds to the amount of charge stored in the floating gate. An isolation dielectric layer is disposed between the first insulating dielectric layer and the first well.

2. The imaging device according to claim 1, characterized in that, Along a direction perpendicular to the imaging device, the window includes a first opening and a second opening disposed opposite to each other. The first opening is located on the surface of the first insulating dielectric layer facing the floating grid, and the second opening is located on the surface of the first insulating dielectric layer facing the first well. The first opening and the second opening are connected to each other.

3. The imaging device according to claim 1 or 2, characterized in that, The isolation medium layer is a high-density P-ion implantation medium.

4. The imaging device according to any one of claims 1 to 3, characterized in that, Along the lateral direction of the imaging device, the cross-sectional area of ​​the first well is larger than that of the second well.

5. The imaging device according to any one of claims 1 to 4, characterized in that, The second well has a source and a drain on both sides facing the end face of the first insulating dielectric layer, respectively, by ion implantation doping. The source and drain have the second doping type. Along the lateral direction of the imaging device, the channel region is located between the source and the drain.

6. The imaging device according to claim 5, characterized in that, A control gate is disposed on the surface of the second insulating dielectric layer opposite to the floating gate. The control gate, the source, and the drain are respectively connected to a logic control circuit, which is used to apply voltage to the control gate, the source, and the drain.

7. The imaging device according to claim 2, characterized in that, The floating gate extends along the guide of the window through the first opening to the second opening, and the floating gate located at the second opening is connected to the first sink.

8. The imaging device according to claim 2, characterized in that, The first well extends through the second opening along the guide of the window to the first opening, and the floating gate located at the first opening is connected to the first well.

9. The imaging device according to claim 2, characterized in that, The floating grid extends into the window through the first opening, and the first sink extends into the window through the second opening. The floating grid and the first sink located inside the window are connected.

10. The imaging device according to any one of claims 1 to 9, characterized in that, The first doping type is n-type impurity doping, and the second doping type is p-type impurity doping; or, the first doping type is p-type impurity doping, and the second doping type is n-type impurity doping.

11. An image sensor, characterized in that, The image sensor includes a pixel array and a logic control circuit. The pixel array includes at least one imaging device, which is electrically connected to the logic control circuit. The imaging device is as described in any one of claims 1 to 10. The logic control circuit is used to generate a corresponding image based on the amount of charge stored in the floating grating.

12. An electronic device, characterized in that, The electronic device includes a processor and an image sensor, as described in claim 11, wherein the processor is configured to acquire the image from the image sensor.

Images