Method for manufacturing fin field effect transistor
By forming an isolation dielectric layer and compensating side wall on the semiconductor substrate, the problem of fin body loss during the removal of the pseudo-gate structure is solved, and the device performance and product yield are improved.
Patent Information
- Application Number
- CN202110924013.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-08-12
- Publication Date
- 2025-04-22
- Estimated Expiration
- 2041-08-12
AI Technical Summary
During the removal of the pseudo gate structure, the fin body is easily lost, resulting in a decrease in device performance and a decrease in product yield.
Fin body loss is prevented by forming an isolation dielectric layer on the semiconductor substrate and forming a compensating side wall on the side of the dummy gate structure, including a multi-layer first sub-side wall and a second sub-side wall.
It effectively prevents the loss of fins during the removal of the pseudo gate structure, and avoids degradation of device performance and product yield.
Smart Images
Figure CN114188223B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a method for manufacturing a fin field effect transistor (FinField Effect Transistor, FinFET). Background Art
[0002] With the development of semiconductor process technology, the gate width is constantly shrinking, and traditional planar CMOS devices can no longer meet the needs of devices, such as the control of short channel effects. For technology nodes below 20nm, the fin field effect transistor structure has better electrical performance.
[0003] Embedded epitaxial layers are also introduced into the source and drain regions of the fin field effect transistor to change the stress in the channel region, thereby improving the carrier mobility in the channel region and thus improving the performance of the device. Starting from the 90nm technology node, embedded SiGe epitaxial layers were introduced to improve the performance of PMOS; and starting from the 14nm technology node, embedded SiP epitaxial layers were introduced to improve the performance of NMOS.
[0004] At the same time, fin field effect transistors usually also use a metal gate structure. The metal gate structure is usually a high dielectric constant (HK) metal gate (MG), namely HKMG. The metal gate structure needs to be implemented through a metal gate replacement process. One metal gate replacement process is a gate-last process. In the gate-last process, a dummy gate structure needs to be used before the metal gate replacement process. The dummy gate structure is usually formed by superimposing a dummy gate dielectric layer such as an oxide layer and a polysilicon dummy gate. The formation area of the source and drain regions is self-aligned and defined by the dummy gate structure, including the formation area of the embedded epitaxial layer. Sidewalls are also formed on the side of the dummy gate structure, and the sidewalls include a compensation sidewall (offset spacer) and a second sidewall formed by a hard mask layer; the compensation sidewall is used to achieve self-alignment definition of the lightly doped drain region; the second sidewall is used for self-alignment definition of the formation area of the embedded epitaxial layer, and the second sidewall will serve as a hard mask layer during the etching process of the groove of the embedded epitaxial layer.
[0005] After the formation and planarization of the zero-th interlayer film is completed, the step of removing the dummy gate structure will be carried out. A gate trench will be formed in the removed area of the dummy gate structure, and then a metal gate structure will be formed in the gate trench.
[0006] However, when removing the pseudo-gate structure, the fins often disappear, which ultimately affects the performance of the device and the yield of the product. Summary of the invention
[0007] The technical problem to be solved by the present invention is to provide a method for manufacturing a fin field effect transistor, which can prevent fin body loss during the removal process of a pseudo gate structure.
[0008] In order to solve the above technical problems, the present invention provides a method for manufacturing a fin field effect transistor, comprising the following steps:
[0009] Step 1: providing a semiconductor substrate formed with fins, wherein there are spacing regions between the fins, the spacing regions are filled with an isolation dielectric layer, and the top surface of the isolation dielectric layer is lower than the top surface of the fins.
[0010] A dummy gate dielectric layer and a polysilicon dummy gate are formed in sequence and patterned to form a dummy gate structure formed by superimposing the patterned dummy gate dielectric layer and the polysilicon dummy gate; the dummy gate structure covers the top surface and side surfaces of the fin body located in the gate formation area, and the dummy gate structure also extends to the surface of the isolation dielectric layer in the spacing area.
[0011] Step 2: forming a compensation spacer on the side of the dummy gate structure for defining a self-alignment condition for lightly doped drain injection, wherein the steps of forming the compensation spacer include:
[0012] Step 21 , performing a first etching on the isolation dielectric layer with the dummy gate structure as a self-alignment condition so that the top surface of the isolation dielectric layer in the spacing region is lower than the bottom surface of the dummy gate dielectric layer.
[0013] Step 22: Use a deposition and etching process to self-align and form a first sub-spacer on the side of the dummy gate structure, wherein the bottom surface of the first sub-spacer is flush with the top surface of the isolation dielectric layer before the material layer of the first sub-spacer is deposited.
[0014] Step 23, performing a second etching on the isolation dielectric layer with the first sub-spacer as a self-alignment condition so that the top surface of the isolation dielectric layer in the spacing region is lower than the bottom surface of the first sub-spacer.
[0015] Repeat steps 22 and 23 to form multiple layers of the first sub-spacers on the side of the dummy gate structure until the stacking thickness of each layer of the first sub-spacers reaches a required value.
[0016] Step 24: Use a deposition process to self-align and form a second sub-sidewall on the side of the dummy gate structure. The second sub-sidewall also extends to the surface outside the dummy gate structure and the top surface of the dummy gate structure. The compensation sidewall is formed by stacking the first sub-sidewall and the second sub-sidewall in each layer.
[0017] Step three: forming an embedded epitaxial layer in the fins on both sides of the dummy gate structure by self-alignment.
[0018] Step 4: forming a zero-th interlayer film and performing planarization so that the top surface of the zero-th interlayer film is flush with the top surface of the polysilicon dummy gate.
[0019] Step 5: Perform a metal gate replacement process, including:
[0020] Step 51, using an etching process to remove the dummy gate structure and form a gate trench in the removal area of the dummy gate structure; when removing the dummy gate structure, the compensation sidewall on the fin body prevents the gate trench from being connected to the embedded epitaxial layer, and the compensation sidewall in the spacing area prevents the gate trench from being connected to the top area of the isolation dielectric layer outside the compensation sidewall, thereby preventing the generation of fin body loss.
[0021] Step 52: forming a metal gate structure in the gate trench formed by stacking a second gate dielectric layer and a second metal gate.
[0022] A further improvement is that the semiconductor substrate comprises a silicon substrate.
[0023] A further improvement is that the isolation dielectric layer adopts a shallow trench isolation oxide layer.
[0024] A further improvement is that the isolation dielectric layer is formed by FCVD process.
[0025] A further improvement is that in step one, a first hard mask layer is also formed on the top surface of the polysilicon pseudo gate. During patterning, the first hard mask layer is first etched, and then the polysilicon pseudo gate and the pseudo gate dielectric layer are etched in sequence using the first hard mask layer as a mask.
[0026] A further improvement is that, in step 21, the etching amount of the isolation dielectric layer by the first etching is 5 nm.
[0027] A further improvement is that in step 23, the etching amount of the isolation dielectric layer by the second etching is 2 nm.
[0028] A further improvement is that the material of the first sub-spacer includes oxide, nitride, oxynitride or low-K material.
[0029] A further improvement is that the material of the second sub-spacer includes oxide, nitride, oxynitride or low-K material.
[0030] A further improvement is that step three includes the following sub-steps:
[0031] Step 31 : forming a second sidewall spacer on the side of the compensation sidewall spacer of the dummy gate structure and the side of the fin body, wherein the second sidewall spacer is formed by depositing a second hard mask layer and performing full etching.
[0032] Step 32: Use the first hard mask layer on the top surface of the pseudo gate structure, the second side wall on the side of the pseudo gate structure, the second side wall on the side of the fin body, and the isolation dielectric layer in the isolation area as masks to self-align and etch the fin body on both sides of the pseudo gate structure to form grooves.
[0033] Step 33: Filling the groove with an epitaxial layer to form the embedded epitaxial layer.
[0034] A further improvement is that when the fin field effect transistor is NMOS, the embedded epitaxial layer includes SiP.
[0035] A further improvement is that when the fin field effect transistor is a PMOS, the embedded epitaxial layer includes SiGe.
[0036] A further improvement is that NMOS and PMOS are integrated on the semiconductor substrate at the same time, and step three is repeated twice, one time step three is used to form the embedded epitaxial layer of NMOS, and the other time step three is used to form the embedded epitaxial layer of PMOS.
[0037] A further improvement is that after step three is completed, the method further includes performing source and drain implantation using the second sidewalls on both sides of the dummy gate structure as a self-alignment condition to form source and drain regions in the embedded epitaxial layer.
[0038] A further improvement is that, in step 52, the second gate dielectric layer includes a high dielectric constant layer, and the second metal gate includes a metal work function layer and a metal conductive material layer.
[0039] A further improvement is that in step one, the fin bodies are formed by etching the semiconductor substrate, and in a top view, the fin bodies are in a strip structure parallel to each other.
[0040] A further improvement is that, in step one, the polysilicon pseudo gates on the same row are connected together to form a polysilicon row; in a top view, the polysilicon row and the fin body are perpendicular to each other.
[0041] The present invention makes a specific arrangement for the formation process of the compensation sidewall for defining the self-alignment condition of the lightly doped drain injection. The compensation sidewall is formed by stacking more than one layer of the first sub-sidewall formed by self-alignment through deposition and etching and a layer of the second sub-sidewall formed by deposition. Before the deposition of each layer of the sub-sidewall, the isolation dielectric layer in the spacing area is etched, that is, a certain thickness of the isolation dielectric layer is removed, so that the bottom surface of each sub-sidewall is lowered layer by layer. In this way, the compensation sidewall in the spacing area can form a good isolation between the pseudo gate structure and the isolation dielectric layer outside the pseudo gate structure, thereby preventing the formation of a connecting groove between the gate groove and the isolation dielectric layer outside the pseudo gate structure on both sides of the bottom of the pseudo gate structure when the pseudo gate structure is removed.
[0042] At the same time, the second sub-side wall is used for self-aligned etching. After the embedded epitaxial layer is formed on the fin body, the spacing area between the dummy gate structure and the embedded epitaxial layer can be lengthened, thereby preventing the formation of a connecting groove connected to the embedded epitaxial layer at the bottom of the dummy gate structure when the dummy gate structure is removed.
[0043] Therefore, the present invention can simultaneously prevent the gate trench and the isolation dielectric layer and the embedded epitaxial layer outside the pseudo gate structure from being connected, thereby finally avoiding the fin body loss during the removal of the pseudo gate structure and further avoiding the fin body disappearance defect. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0045] Figure 1 is a flow chart of a method for manufacturing a fin field effect transistor according to an embodiment of the present invention;
[0046] Figure 2 is a plan view of a fin field effect transistor formed by a method for manufacturing a fin field effect transistor according to an embodiment of the present invention;
[0047] Figure 3 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line AA in FIG.
[0048] Figure 4 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line BB in FIG.
[0049] Figure 5 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line CC in FIG.
[0050] Figure 6The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line CC in FIG.
[0051] Figure 7 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line BB in FIG.
[0052] Figure 8 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line CC in FIG.
[0053] Fig. 9 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line BB in FIG.
[0054] Fig.10 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line CC in FIG.
[0055] Fig.11 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line BB in FIG.
[0056] Fig.12 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line CC in FIG.
[0057] Fig.13 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line BB in FIG.
[0058] Fig.14 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line BB in FIG.
[0059] Fig.15 The method for manufacturing a fin field effect transistor according to an embodiment of the present invention is as follows: Figure 2 The cross-sectional structure diagram at the dotted line CC in FIG.
[0060] Fig.16 The existing method of manufacturing fin field effect transistors is to form an embedded epitaxial layer before Fig.12Cross-sectional structural diagram at the same position;
[0061] Fig.17 The existing method of manufacturing fin field effect transistors is to form an embedded epitaxial layer before Fig.13 Cross-sectional structural diagram at the same position;
[0062] Fig.18 The existing method for manufacturing fin field effect transistors is to remove the pseudo gate structure before Fig.14 Cross-sectional structural diagram at the same position;
[0063] Fig.19 The existing method for manufacturing fin field effect transistors is to remove the pseudo gate structure before Fig.15 Cross-sectional structural diagram at the same position;
[0064] Fig. 20 yes Fig.18 The corresponding simulation diagram;
[0065] Fig.21 yes Fig.19 The corresponding simulation diagram;
[0066] Fig. 22 It is a combination Fig. 20 and Fig.21 Simulation diagram of
[0067] Fig.23 The method of the embodiment of the present invention Fig.13 The corresponding simulation diagram;
[0068] Fig.24 The method of the embodiment of the present invention Fig.12 The corresponding simulation diagram. DETAILED DESCRIPTION
[0069] like Figure 1 is a flow chart of a method for manufacturing a fin field effect transistor according to an embodiment of the present invention; Figure 2 FIG. 1 is a plan view of a fin field effect transistor formed by a method for manufacturing a fin field effect transistor according to an embodiment of the present invention; the method for manufacturing a fin field effect transistor according to an embodiment of the present invention comprises the following steps:
[0070] Step 1: providing a semiconductor substrate 201 a formed with fin bodies 201 , wherein the fin bodies 201 have spacer regions between them, and the spacer regions are filled with an isolation dielectric layer 208 , wherein a top surface of the isolation dielectric layer 208 is lower than a top surface of the fin bodies 201 .
[0071] A dummy gate dielectric layer 210 and a polysilicon dummy gate 202 are sequentially formed and patterned to form a dummy gate structure formed by stacking the patterned dummy gate dielectric layer 210 and the polysilicon dummy gate 202; the dummy gate structure covers the top surface and side surfaces of the fin body 201 located in the gate formation area, and the dummy gate structure also extends to the surface of the isolation dielectric layer 208 in the spacing area.
[0072] Figure 3 It is along the Figure 2 It can be seen from the cross-sectional structure diagram at the dotted line AA in FIG. 2 that the polysilicon strip formed by the polysilicon pseudo gate 202 will cover the fin body 201 and the isolation dielectric layer 208 at the same time.
[0073] Figure 4 It is along the Figure 2 Cross-sectional structure diagram at the dotted line BB in .
[0074] Figure 5 It is along the Figure 2 Cross-sectional structure diagram at the dotted line CC in .
[0075] In the embodiment of the present invention, the semiconductor substrate 201a includes a silicon substrate.
[0076] The isolation dielectric layer 208 is a shallow trench isolation oxide layer.
[0077] The isolation dielectric layer 208 is formed by FCVD process.
[0078] A first hard mask layer 209 is also formed on the top surface of the polysilicon pseudo gate 202. During patterning, the first hard mask layer 209 is etched first, and then the polysilicon pseudo gate 202 and the pseudo gate dielectric layer 210 are etched in sequence using the first hard mask layer 209 as a mask.
[0079] Depend on Figure 2 As shown, the fin bodies 201 are formed by etching the semiconductor substrate 201 a , and in a top view, each of the fin bodies 201 is in a strip structure parallel to each other.
[0080] The polysilicon dummy gates 202 on the same row are connected together to form a polysilicon row; in a top view, the polysilicon row and the fin body 201 are perpendicular to each other.
[0081] Step 2: forming a compensation spacer 211 (offset spacer) on the side of the dummy gate structure for defining a self-alignment condition for lightly doped drain injection, the steps of forming the compensation spacer 211 include:
[0082] Step 21: Figure 6As shown, the isolation dielectric layer 208 is first etched with the pseudo gate structure as a self-aligned condition so that the top surface of the isolation dielectric layer 208 in the spacer region is lower than the bottom surface of the pseudo gate dielectric layer 210. In step 21, the isolation dielectric layer is not etched at the dotted lines AA and BB, so the cross-sectional structure at the dotted lines AA and BB remains Figure 3 and Figure 4 The structure shown.
[0083] Depend on Figure 6 As shown, the isolation dielectric layer 208 is etched to a certain thickness d1.
[0084] In the embodiment of the present invention, in step 21, the etching amount of the isolation dielectric layer 208 by the first etching is 5 nm; in other embodiments, the thickness d1 can also be adjusted as needed.
[0085] Step 22, using a deposition and etching process to self-align and form a first sub-spacer 211a on the side of the dummy gate structure, wherein the bottom surface of the first sub-spacer 211a is flush with the top surface of the isolation dielectric layer 208 before the material layer of the first sub-spacer 211a is deposited.
[0086] In the embodiment of the present invention, the material of the first sub-spacer 211 a includes oxide, nitride, oxynitride or low-K material.
[0087] like Figure 7 , which is a schematic structural diagram of the first sub-spacer 211a formed along the dotted line BB; Figure 8 is a schematic structural diagram of the first sub-sidewall 211a formed along the dotted line CC; Figure 8 The position of the bottom surface of the first sub-spacer 211a will drop, that is, be lower than the top surface of the isolation dielectric layer 208 at the bottom of the dummy gate structure, that is, the bottom surface of the dummy gate dielectric layer 210.
[0088] Step 23: performing a second etching on the isolation dielectric layer 208 under the self-alignment condition of the first sub-spacer 211 a so that the top surface of the isolation dielectric layer 208 in the spacing region is lower than the bottom surface of the first sub-spacer 211 a.
[0089] In the embodiment of the present invention, the etching amount of the isolation dielectric layer 208 by the second etching is 2 nm. In other embodiments, the thickness of the second etching can also be adjusted as needed.
[0090] Fig.10 It is shown that after the second etching, the top surface of the isolation dielectric layer 208 is further lowered.
[0091] Repeat steps 22 and 23 to form multiple layers of the first sub-spacer 211a on the side of the dummy gate structure until the stacking thickness of each layer of the first sub-spacer 211a reaches the required value. In the embodiment of the present invention, one layer of the first sub-spacer 211a can reach the required value, so there is no need to repeat the steps in a cycle. In other embodiments, steps 22 and 23 can be repeated as needed.
[0092] Step 24: Use a deposition process to self-align and form a second sub-spacer 211b on the side of the dummy gate structure, wherein the second sub-spacer 211b also extends to the surface outside the dummy gate structure and the top surface of the dummy gate structure, and the first sub-spacer 211a and the second sub-spacer 211b of each layer are superimposed to form the compensation spacer 211. A further improvement is that:
[0093] In the method of the embodiment of the present invention, the material of the second sub-spacer 211 b includes oxide, nitride, oxynitride or low-K material.
[0094] Fig. 9 The compensation spacer 211 along the dotted line BB, ie, the top of the fin 201 is shown.
[0095] Fig.10 The compensation sidewall 211 along the dotted line CC, ie, the spacing area, is shown.
[0096] Step three: forming an embedded epitaxial layer 214 in the fins 201 on both sides of the dummy gate structure by self-alignment.
[0097] In the embodiment of the present invention, step three includes the following sub-steps:
[0098] Step 31 : forming a second sidewall spacer 212 on the side surface of the compensation sidewall spacer 211 of the dummy gate structure and the side surface of the fin body 201 , wherein the second sidewall spacer 212 is formed by depositing a second hard mask layer and performing full etching.
[0099] Fig.11 The second sidewall 212 along the dotted line BB, ie, the top of the fin 201 is shown.
[0100] Fig.12 The second sidewall 212 along the dotted line CC, ie, the spacing area, is shown.
[0101] Step 32: Use the first hard mask layer 209 on the top surface of the pseudo gate structure, the second side wall 212 on the side of the pseudo gate structure, the second side wall 212 on the side of the fin body 201, and the isolation dielectric layer 208 in the isolation area as masks to self-align and etch the fin body 201 on both sides of the pseudo gate structure to form a groove 213.
[0102] The groove 213 is only Fig.11 In the display, Fig.12 The groove 213 is not formed therein.
[0103] Step 33 : Filling the groove 213 with an epitaxial layer to form the embedded epitaxial layer 214 .
[0104] Fig.13 The embedded epitaxial layer 214 is shown along the dashed line BB, ie, the top of the fin 201. The recess 213 and the embedded epitaxial layer 214 are not formed along the dashed line CC.
[0105] When the fin field effect transistor is an NMOS, the embedded epitaxial layer 214 includes SiP.
[0106] When the fin field effect transistor is a PMOS, the embedded epitaxial layer 214 includes SiGe.
[0107] Typically, NMOS and PMOS are integrated on the semiconductor substrate 201a at the same time, and step 3 is repeated twice, one time for forming the embedded epitaxial layer 214 of NMOS, and the other time for forming the embedded epitaxial layer 214 of PMOS. Figure 2 As shown, the dotted box 203 corresponds to a formation area of an NMOS, and the corresponding embedded epitaxial layer 214 formed by SiP is Figure 2 The dotted box 204 corresponds to a PMOS formation area, and the corresponding embedded epitaxial layer 214 formed of SiGe is Figure 2 In the figure, it is separately marked with a reference numeral 206.
[0108] After step 3 is completed, the step of performing source and drain implantation using the second sidewalls 212 on both sides of the dummy gate structure as a self-aligned condition to form source and drain regions in the embedded epitaxial layer 214 is also included. For NMOS, the source and drain implantation is N+ source and drain implantation; for PMOS, the source and drain implantation is P+ source and drain implantation.
[0109] Step 4: forming a zero-th interlayer film 302 and planarizing the film so that the top surface of the zero-th interlayer film 302 is flush with the top surface of the polysilicon dummy gate 202 .
[0110] The zeroth interlayer film 302 is also referred to Fig. 20 The simulation diagram in Fig.14 The description of the zero-th interlayer film 302 is omitted in the cross-sectional structure diagram. Generally, before forming the zero-th interlayer film 302, a step of forming a contact etch stop layer (CESL) 301 is also included. Fig. 20 shown.
[0111] Step 5: Perform a metal gate replacement process, including:
[0112] Step 51, using an etching process to remove the dummy gate structure and form a gate trench 215 in the removal area of the dummy gate structure; when removing the dummy gate structure, the compensation sidewall 211 on the fin body 201 prevents the gate trench 215 from being connected to the embedded epitaxial layer 214, and the compensation sidewall 211 in the spacing area prevents the gate trench 215 from being connected to the top area of the isolation dielectric layer 208 outside the compensation sidewall 211, thereby preventing the fin body 201 from being lost.
[0113] like Fig.15 As shown, the dotted line 207 corresponds to the bottom position structure of the compensation sidewall 211. It can be seen that the bottom structure at the dotted line 207 of the compensation sidewall 211 can form a good isolation between the gate trench 215 and the isolation dielectric layer 208 outside the pseudo gate structure.
[0114] Likewise, Fig.14 As shown, the dotted line 206 corresponds to the bottom position structure of the compensation sidewall 211 located on the fin body 201. The second sub-sidewall 211b in the compensation sidewall 211 has a larger lateral structure, thereby increasing the isolation between the gate trench 215 and the embedded epitaxial layer 214 and preventing the generation of connectivity defects between the two.
[0115] Depend on Figure 2 As shown, the dotted frame 207 corresponds to the area enclosed by the fin body 201 and the polysilicon pseudo gate 202, so the isolation dielectric layer 208 and the fin body 201 and the polysilicon pseudo gate 202 are adjacent to each other. If the bottom of the isolation dielectric layer 208 and the gate trench 215 are connected, it will inevitably affect the fin body 201 adjacent to the isolation dielectric layer 208, and eventually consume the fin body 201. After the embedded epitaxial layer 214 is formed, it will also serve as a part of the fin body 201. If the gate trench 215 and the embedded epitaxial layer 214 are connected, the fin body 201 will also be consumed. The embodiment of the present invention can well avoid the connection between the gate trench 215 and the isolation dielectric layer 208 and the embedded epitaxial layer 214, thereby avoiding the consumption of the fin body 201, and finally avoiding the disappearance of the fin body.
[0116] Step 52 : forming a metal gate structure in the gate trench 215 , which is formed by stacking a second gate dielectric layer and a second metal gate.
[0117] In the embodiment of the present invention, the second gate dielectric layer includes a high dielectric constant layer, and the second metal gate includes a metal work function layer and a metal conductive material layer.
[0118] The embodiment of the present invention makes specific settings for the formation process of the compensation sidewall 211 used to define the self-alignment condition of the lightly doped drain injection. The compensation sidewall 211 is composed of more than one layer of the first sub-sidewall 211a formed by self-alignment through deposition and etching and a layer of the second sub-sidewall 211b formed by deposition. Before the deposition of each layer of the sub-sidewall, the isolation dielectric layer 208 in the spacing area is etched, that is, a certain thickness of the isolation dielectric layer 208 is removed, so that the bottom surface of each sub-sidewall is lowered layer by layer. In this way, the compensation sidewall 211 in the spacing area can form a good isolation between the pseudo gate structure and the isolation dielectric layer 208 outside the pseudo gate structure, thereby preventing the formation of a connecting groove between the gate groove 215 and the isolation dielectric layer 208 outside the pseudo gate structure on both sides of the bottom of the pseudo gate structure when the pseudo gate structure is removed.
[0119] At the same time, the second sub-sidewall 211b is used for self-aligned etching. After the embedded epitaxial layer 214 is formed on the fin body 201, the spacing area between the dummy gate structure and the embedded epitaxial layer 214 can be lengthened, thereby preventing a connecting groove connected to the embedded epitaxial layer 214 from being formed at the bottom of the dummy gate structure when the dummy gate structure is removed.
[0120] Therefore, the embodiment of the present invention can prevent the gate trench 215 and the isolation dielectric layer 208 and the embedded epitaxial layer 214 from being connected to each other, thereby avoiding the loss of the fin 201 during the removal of the dummy gate structure and further avoiding the disappearance defect of the fin 201.
[0121] In order to make the effects of the embodiments of the present invention more clear, the corresponding defects of the existing methods are now described:
[0122] like Fig.16 As shown, the conventional method for manufacturing a fin field effect transistor is as follows: after forming an embedded epitaxial layer, Fig.12 The cross-sectional structure diagram at the same position; the compensation sidewall 211c of the existing method is directly formed by dielectric layer deposition and etching, and the isolation dielectric layer 208 is not etched step by step. The bottom surface of each compensation sidewall 211c is located above the top surface of the isolation dielectric layer 208.
[0123] like Fig.17 As shown, the conventional method for manufacturing a fin field effect transistor is as follows: after forming an embedded epitaxial layer, Fig.13 Cross-sectional structural diagram at the same position;
[0124] like Fig.18As shown, the conventional method for manufacturing a fin field effect transistor is performed after the pseudo gate structure is removed. Fig.14 Cross-sectional structure diagram at the same position; comparison Fig.14 and Fig.18 It can be seen that Fig.18 There is no second sub-sidewall 211b of a longer horizontal position in the embodiment of the present invention at the position corresponding to the dotted circle 216a in the figure, so the existing method is prone to produce a connecting groove defect at the dotted circle 216a.
[0125] like Fig.19 As shown, the conventional method for manufacturing a fin field effect transistor is performed after the pseudo gate structure is removed. Fig.15 Cross-sectional structure diagram at the same position; comparison Fig.15 and Fig.19 It can be seen that Fig.19 There is no bottom structure of the compensation side wall 211 of the embodiment of the present invention at the position corresponding to the dotted circle 217a in the figure, so the existing method is prone to produce a connecting groove defect at the dotted circle 217a.
[0126] In order to more vividly understand the difference between the device formed by the method of the embodiment of the present invention and the device formed by the prior art method, the device formed by the method of the embodiment of the present invention and the device formed by the prior art method are simulated respectively.
[0127] like Fig. 20 As shown, Fig.18 The corresponding simulation diagram; Fig. 20 It is actually a three-dimensional diagram, with section lines BB and CC at Fig. 20 It can be seen that there is a connecting groove defect at the bottom area 216a of the gate trench 215 corresponding to the dotted line BB.
[0128] like Fig.21 As shown, Fig.19 Corresponding simulation diagram; it can be seen that there is a connecting groove defect at the bottom area 217a of the gate trench 215 corresponding to the dotted line CC. Fig.21 The connecting groove defect corresponding to the bottom area 216a can also be seen.
[0129] Fig. 22 It is a combination Fig. 20 and Fig.21 Simulation diagram of Fig. 22 The area indicated by the mark 303 is the area where the fin body 201 is worn out and the fin body 201 completely disappears.
[0130] like Fig.23 As shown, it is an embodiment of the method of the present invention. Fig.13 The corresponding simulation diagram; Fig.23, an enlarged view of the dotted circle 216 is shown. It can be seen that the embodiment of the present invention will not produce a connecting groove defect at the dotted circle 216.
[0131] like Fig.24 As shown, it is an embodiment of the method of the present invention. Fig.12 The corresponding simulation diagram. Fig.24 , an enlarged view of the dotted circle 217 is shown. It can be seen that the embodiment of the present invention will not produce a connecting groove defect at the dotted circle 217.
[0132] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing a fin field effect transistor, characterized in that: The steps include: Step 1: providing a semiconductor substrate formed with fin bodies, wherein there are spacing regions between the fin bodies, and the spacing regions are filled with an isolation dielectric layer, and the top surface of the isolation dielectric layer is lower than the top surface of the fin bodies; A dummy gate dielectric layer and a polysilicon dummy gate are sequentially formed and patterned to form a dummy gate structure formed by stacking the patterned dummy gate dielectric layer and the polysilicon dummy gate; the dummy gate structure covers the top surface and side surfaces of the fin body located in the gate formation area, and the dummy gate structure also extends to the surface of the isolation dielectric layer in the spacing area; Step 2: forming a compensation sidewall on the side of the dummy gate structure for defining a self-alignment condition for lightly doped drain injection, wherein the step of forming the compensation sidewall comprises: Step 21, performing a first etching on the isolation dielectric layer with the pseudo gate structure as a self-alignment condition so that the top surface of the isolation dielectric layer in the spacing region is lower than the bottom surface of the pseudo gate dielectric layer; Step 22, using a deposition and etching process to self-align and form a first sub-spacer on the side of the dummy gate structure, wherein the bottom surface of the first sub-spacer is flush with the top surface of the isolation dielectric layer before the material layer of the first sub-spacer is deposited; Step 23, etching the isolation dielectric layer for a second time with the first sub-spacer as a self-alignment condition so that the top surface of the isolation dielectric layer in the spacing region is lower than the bottom surface of the first sub-spacer; Repeat steps 22 and 23 to form multiple layers of the first sub-spacers on the side of the dummy gate structure until the stacking thickness of each layer of the first sub-spacers reaches a required value; Step 24, forming a second sub-spacer on the side of the dummy gate structure in a self-aligned manner by a deposition process, wherein the second sub-spacer also extends to the surface outside the dummy gate structure and the top surface of the dummy gate structure, and the first sub-spacer and the second sub-spacer of each layer are stacked to form the compensation spacer; Step 3, forming an embedded epitaxial layer in the fins on both sides of the dummy gate structure by self-alignment; Step 4: forming a zero-th interlayer film and performing planarization so that the top surface of the zero-th interlayer film is flush with the top surface of the polysilicon dummy gate; Step 5: Perform a metal gate replacement process, including: Step 51, removing the dummy gate structure by etching process and forming a gate trench in the removal area of the dummy gate structure; when removing the dummy gate structure, the compensation sidewall on the fin body prevents the gate trench from being connected to the embedded epitaxial layer, and the compensation sidewall in the spacing area prevents the gate trench from being connected to the top area of the isolation dielectric layer outside the compensation sidewall, thereby preventing the generation of fin body loss; Step 52: forming a metal gate structure in the gate trench formed by stacking a second gate dielectric layer and a second metal gate.
2. The method for manufacturing a fin field effect transistor according to claim 1, wherein: The semiconductor substrate includes a silicon substrate.
3. The method for manufacturing a fin field effect transistor according to claim 1, wherein: The isolation dielectric layer adopts a shallow trench isolation oxide layer.
4. The method for manufacturing a fin field effect transistor according to claim 3, wherein: The isolation dielectric layer is formed by using the FCVD process.
5. The method for manufacturing a fin field effect transistor according to claim 2, wherein: In step one, a first hard mask layer is also formed on the top surface of the polysilicon dummy gate. During patterning, the first hard mask layer is first etched, and then the polysilicon dummy gate and the dummy gate dielectric layer are sequentially etched using the first hard mask layer as a mask.
6. The method for manufacturing a fin field effect transistor according to claim 1, wherein: In step 21, the etching amount of the isolation dielectric layer by the first etching is 5 nm.
7. The method for manufacturing a fin field effect transistor according to claim 1, wherein: In step 23, the etching amount of the isolation dielectric layer by the second etching is 2 nm.
8. The method for manufacturing a fin field effect transistor according to claim 1, wherein: The material of the first sub-spacer includes oxide, nitride, oxynitride or low-K material.
9. The method for manufacturing a fin field effect transistor according to claim 8, wherein: The material of the second sub-spacer includes oxide, nitride, oxynitride or low-K material.
10. The method for manufacturing a fin field effect transistor according to claim 5, wherein: Step 3 includes the following sub-steps: Step 31, forming a second sidewall spacer on the side of the compensation sidewall spacer of the dummy gate structure and the side of the fin body, wherein the second sidewall spacer is formed by depositing a second hard mask layer and fully etching; Step 32, using the first hard mask layer on the top surface of the dummy gate structure, the second sidewall spacer on the side of the dummy gate structure, the second sidewall spacer on the side of the fin body, and the isolation dielectric layer in the spacing area as masks to perform self-aligned etching on the fin body on both sides of the dummy gate structure to form grooves; Step 33: Filling the groove with an epitaxial layer to form the embedded epitaxial layer.
11. The method for manufacturing a fin field effect transistor according to claim 10, wherein: When the fin field effect transistor is NMOS, the embedded epitaxial layer includes SiP.
12. The method for manufacturing a fin field effect transistor according to claim 11, wherein: When the fin field effect transistor is a PMOS, the embedded epitaxial layer includes SiGe.
13. The method for manufacturing a fin field effect transistor according to claim 12, wherein: NMOS and PMOS are integrated on the semiconductor substrate at the same time, and step three is repeated twice, one time step three is used to form the embedded epitaxial layer of NMOS, and the other time step three is used to form the embedded epitaxial layer of PMOS.
14. The method for manufacturing a fin field effect transistor according to claim 10, wherein: After step three is completed, the method further includes performing source and drain implantation using the second sidewalls on both sides of the dummy gate structure as a self-alignment condition to form source and drain regions in the embedded epitaxial layer.
15. The method for manufacturing a fin field effect transistor according to claim 1, wherein: In step 52, the second gate dielectric layer includes a high dielectric constant layer, and the second metal gate includes a metal work function layer and a metal conductive material layer.
16. The method for manufacturing a fin field effect transistor according to claim 1, wherein: In step one, the fin bodies are formed by etching the semiconductor substrate, and in a top view, the fin bodies are in a strip-shaped structure parallel to each other.
17. The method for manufacturing a fin field effect transistor according to claim 16, wherein: In step 1, the polysilicon pseudo gates on the same row are connected together to form a polysilicon row; in a top view, the polysilicon row and the fin body are perpendicular to each other.
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