Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element having an inclined conductive layer and a method of manufacturing the same. The semiconductor element includes a substrate, a first insulating layer disposed on the substrate, a first inclined conductive layer disposed in the first insulating layer, and a top conductive layer disposed to cover the first inclined conductive layer.

Description

TECHNICAL FIELD

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 020,170, filed September 14, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor device and a method of fabricating the same. In particular, the present disclosure relates to a semiconductor device having a tilted conductive layer and a method of fabricating the same. BACKGROUND

[0003] Semiconductor devices are indispensible for many modern applications. For example, semiconductor devices are widely used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Furthermore, as electronic technology advances, semiconductor devices become smaller and smaller while providing better functionality and including larger numbers of integrated circuits. However, as semiconductor devices are scaled down, the spacing between adjacent conductive elements is gradually reduced, which can reduce the process window of an interconnect structure. Thus, it is increasingly difficult to fabricate an interconnect structure in a semiconductor device. There are continuing challenges in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The foregoing “background” description is for the purpose of generally presenting the context of the disclosure. The background description is not and should not be taken to be the applicant’s acknowledgement that any particular “background” information that has been made of the applicant’s invention, and are not to be taken as an admission that what the applicant’s “background” information and related disclosures are prior art with regard to the present disclosure, and no part of the “background” should be taken to be any part of the prior art of the present disclosure. SUMMARY

[0005] One embodiment of the present disclosure provides a semiconductor device, comprising: a substrate, a first insulating layer disposed on the substrate, a first tilted conductive layer disposed in the first insulating layer, and a top conductive layer disposed to cover the first tilted conductive layer.

[0006] In some embodiments, an acute angle between a bottom surface of the first tilted conductive layer and a sidewall of the first tilted conductive layer is in a range from about 10 degrees to about 85 degrees.

[0007] In some embodiments, the first tilted conductive layer is arranged in a grid dot pattern in a top view.

[0008] In some embodiments, the first tilted conductive layer is arranged in a diagonal dot pattern in a top view.

[0009] In some embodiments, the top conductive layer is a wire, and a fabrication technique of the top conductive layer includes copper, aluminum, titanium, tungsten, or a combination thereof.

[0010] In some embodiments, the semiconductor element includes a barrier layer disposed between the first insulating layer and the first sloped conductive layer, between the top conductive layer and the first insulating layer, and between the first sloped conductive layer and the substrate. The barrier layer is made of titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, silicon tantalum nitride, or a combination thereof.

[0011] In some embodiments, the barrier layer has a thickness in a range from about 10 angstroms to about 15 angstroms.

[0012] In some embodiments, the top conductive layer is a solder element, and is made of tin, silver, copper, gold, an alloy, or a combination thereof.

[0013] In some embodiments, the semiconductor element includes an under bump metallization layer disposed between the first insulating layer and the first sloped conductive layer, between the top conductive layer and the first insulating layer, and between the first sloped conductive layer and the substrate. The under bump metallization layer includes titanium, titanium-tungsten, chromium, aluminum, copper, nickel, chromium-copper, or nickel-vanadium.

[0014] In some embodiments, the semiconductor element includes a second sloped conductive layer disposed in the first insulating layer, wherein the top conductive layer is disposed to cover the first sloped conductive layer and the second sloped conductive layer.

[0015] In some embodiments, an acute angle between a bottom surface of the second sloped conductive layer and a sidewall of the second sloped conductive layer is in a range from about -10 degrees to about -85 degrees.

[0016] In some embodiments, the first sloped conductive layer extends along a first direction, the second sloped conductive layer extends along a second direction, and the second direction is different from the first direction.

[0017] In some embodiments, the first sloped conductive layer and the second sloped conductive layer are alternately arranged along a first axis and a second axis in a top view, and the first axis and the second axis are perpendicular to each other.

[0018] In some embodiments, the first sloped conductive layer is arranged along a first set of columns, the second sloped conductive layer is arranged along a second set of columns, and the first set of columns and the second set of columns are alternately arranged.

[0019] Another embodiment of the present disclosure provides a method of fabricating a semiconductor element, including providing a substrate, forming a first insulating layer on the substrate, forming a first sloped recess along the first insulating layer, and forming a first sloped conductive layer in the first sloped recess and a top conductive layer covering the first sloped conductive layer.

[0020] In some embodiments, forming the first inclined recess along the first insulating layer includes forming a first hard mask layer on the first insulating layer, forming a first hard mask opening along the first hard mask layer, performing a first inclined etching process on the first insulating layer to form the first inclined recess along the first insulating layer, and removing the first hard mask layer. The first inclined etching process uses the first hard mask layer as a pattern guide.

[0021] In some embodiments, an incident angle of the first inclined etching process is in a range of about 5 degrees to about 80 degrees.

[0022] In some embodiments, a fabrication technique of the first hard mask layer includes a material having etching selectivity to the first insulating layer.

[0023] In some embodiments, a fabrication technique of the first hard mask layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, boron nitride, boron silicon nitride, phosphorus boron nitride, boron carbon nitride silicon, or a carbon film.

[0024] In some embodiments, an etching rate ratio of the first hard mask layer to the first insulating layer of the first inclined etching process is in a range of about 1:10 to about 1:100.

[0025] Due to the design of the semiconductor element of the present disclosure, the first inclined conductive layer can provide more contact surface with the substrate. Therefore, the electrical characteristics of the semiconductor element can be improved. That is, the performance of the semiconductor element can be improved. In addition, the fabrication technique of the narrower first inclined recess can use the first hard mask layer having the wider first hard mask opening. In other words, the requirement of the lithography process for forming the narrower first inclined recess can be reduced. Therefore, the yield of the semiconductor element can be improved.

[0026] The foregoing has outlined rather broadly the technical features and advantages of the technology of the present disclosure so that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described below. The present disclosure is directed to all such technically practical applications of the enhancements identified hereinbelow. Those skilled in the art will appreciate the significance of the use of the concepts disclosed herein and of the specific embodiments disclosed herein as a basis of claims or as a design for the construction of other structures or processes that will achieve the same results achieved by the present disclosure. Those skilled in the art will also appreciate that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the claims appended hereto. BRIEF DESCRIPTION OF DRAWINGS

[0027] The disclosure will be more fully understood from the following detailed description taken in connection with the accompanying drawings, in which like reference numerals refer to like elements throughout the figures, and in which:

[0028] Figure 1A flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure is provided.

[0029] Figure 2 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0030] Figure 3 An embodiment of this disclosure is illustrated below. Figure 2 A cross-sectional view of line A-A' in the middle.

[0031] Figure 4 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0032] Figure 5 An embodiment of this disclosure is illustrated below. Figure 4 A cross-sectional view of line A-A' in the middle.

[0033] Figure 6 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0034] Figures 7 to 9 An embodiment of this disclosure is illustrated below. Figure 6 A cross-sectional view of line A-A' in the middle.

[0035] Figures 10 to 15 Examples of some embodiments of this disclosure are shown below. Figure 6 A cross-sectional view of line A-A' in the middle.

[0036] Figures 16 to 17 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0037] Figure 18 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0038] Figure 19 Another embodiment of this disclosure is illustrated along Figure 18 A cross-sectional view of line A-A' in the middle.

[0039] Figure 20 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0040] Figure 21 Another embodiment of this disclosure is illustrated along Figure 20 A cross-sectional view of line A-A' in the middle.

[0041] Figure 22 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure.

[0042] Figure 23 Another embodiment of this disclosure is illustrated along Figure 22Cross-sectional view along line A-A' of FIG. 1A.

[0043] Figure 24 Top view of an intermediate semiconductor element illustrating another embodiment of the present disclosure.

[0044] Figure 25 Cross-sectional view along line A-A' of FIG. 1A. Figure 24 Cross-sectional view along line A-A' of FIG. 1A.

[0045] Figure 26 Top view of an intermediate semiconductor element illustrating another embodiment of the present disclosure.

[0046] Figure 27 Cross-sectional view along line A-A' of FIG. 1A. Figure 26 Cross-sectional view along line B-B' of FIG. 1B.

[0047] Figure 28 Top view of an intermediate semiconductor element illustrating another embodiment of the present disclosure.

[0048] Figure 29 Cross-sectional view along line A-A' of FIG. 1A. Figure 28 Cross-sectional view along line C-C' of FIG. 1C.

[0049] Wherein, the reference numerals are explained as follows:

[0050] 1A: Semiconductor element

[0051] 1B: Semiconductor element

[0052] 1C: Semiconductor element

[0053] 1D: Semiconductor element

[0054] 1E: Semiconductor element

[0055] 1F: Semiconductor element

[0056] 1H: Semiconductor element

[0057] 10: Production method

[0058] 101: Substrate

[0059] 103: First insulating layer

[0060] 105: Second insulating layer

[0061] 201: First inclined conductive layer

[0062] 201BS: Bottom surface

[0063] 201SW: Side wall

[0064] 201TS: Top surface

[0065] 203: top conductive layer

[0066] 205: second inclined conductive layer

[0067] 205BS: bottom surface

[0068] 205SW: sidewall

[0069] 207: barrier layer

[0070] 209: under bump metallization layer

[0071] 301: first hard mask layer

[0072] 303: first hard mask opening

[0073] 305: first inclined recess

[0074] 305BS: bottom surface

[0075] 305SW: sidewall

[0076] 307: first conductive material

[0077] 309: second hard mask layer

[0078] 311: second hard mask opening

[0079] 313: second inclined recess

[0080] 313BS: bottom surface

[0081] 313SW: sidewall

[0082] 401: first inclined etching process

[0083] 403: second inclined etching process

[0084] AA': line

[0085] B-B': line

[0086] C-C': line

[0087] D1: distance

[0088] D2: distance

[0089] D3: distance

[0090] D4: distance

[0091] E1: first direction

[0092] E2: second direction

[0093] FS: first side

[0094] H1: height

[0095] H2: height

[0096] R1: column of the first group

[0097] R2: column of the second group

[0098] S11: step

[0099] S13: step

[0100] S15: step

[0101] S17: step

[0102] W1: width

[0103] W2: width

[0104] W3: width

[0105] W4: width

[0106] X: first axis

[0107] Y: second axis

[0108] Z: axis

[0109] a: angle of incidence

[0110] b: acute angle

[0111] g: acute angle

[0112] d: angle of incidence

[0113] e: acute angle

[0114] z: acute angle DETAILED DESCRIPTION

[0115] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0116] "one embodiment," "an embodiment," "exemplary embodiment," "other embodiments," "another embodiment," and the like mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure, and multiple implementations can exist that include the particular feature, structure, or characteristic. The repeated use of the phrase "in one embodiment" does not refer to the same embodiment; however, it can refer to a different embodiment.

[0117] ​To enable a full understanding of this disclosure, the following description provides detailed steps and structures. It is obvious that implementation of this disclosure does not limit the specific details known to those skilled in the art. Furthermore, known structures and steps are not detailed further to avoid unnecessarily limiting this disclosure. Preferred embodiments of this disclosure are detailed below. However, in addition to the detailed description, this disclosure can also be widely implemented in other embodiments. The scope of this disclosure is not limited to the detailed description, but is defined by the claims.

[0118] It should be understood that the following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or the desired properties of the apparatus. Furthermore, the description of a first feature being formed "on" or "on" a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby potentially preventing direct contact between the first and second features. For simplicity and clarity, various features may be drawn at different scales. In the drawings, some layers / features may be omitted for simplicity.

[0119] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0120] Figure 1 A flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure is provided. Figure 2 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 Example of an implementation of this disclosure Figure 2 A cross-sectional view of line A-A' in the middle.

[0121] refer to Figures 1 to 3 A substrate 101 can be provided, a first insulating layer 103 can be formed on the substrate 101, a first hard mask layer 301 can be formed on the first insulating layer 103, and a first hard mask opening 303 can be formed along the first hard mask layer 301. The corresponding steps are illustrated in...Figure 1 Step Sll in the method 10 shown.

[0122] Referring to Figure 2 and Figure 3 In some embodiments, the substrate 101 can comprise a semiconductor-on-insulator (SOI) structure including, from bottom to top, a handle substrate, an insulator layer, and a topmost semiconductor layer. The handle substrate and the topmost semiconductor layer can be fabricated from an elemental semiconductor, a compound semiconductor, or a combination thereof. The elemental semiconductor can be, for example, silicon or germanium. The compound semiconductor can be, for example, silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductor or II-VI compound semiconductor. The insulator layer can be a crystalline or amorphous dielectric material, such as an oxide and / or nitride. The insulator layer can have a thickness in a range of about 10 nm to 200 nm.

[0123] In some embodiments, the substrate 101 can include a dielectric, an insulator, or a conductive feature formed on the topmost semiconductor layer. The dielectric or the insulator can include, for example, a semiconductor oxide, a semiconductor nitride, a semiconductor oxynitride, a semiconductor carbide, tetraethyl orthosilicate oxide, phosphosilicate glass, borophosphosilicate glass, fluorinated quartz glass, carbon-doped silicon oxide, amorphous fluorinated carbon, or a combination thereof. The conductive feature can be a conductive line, a conductive via, a conductive contact, or the like. The dielectric or the insulator can serve as an insulator to support and electrically isolate the conductive feature.

[0124] In some embodiments, a device component (not shown) can be formed in the substrate 101. The device component can be, for example, a bipolar transistor, a metal oxide semiconductor field effect transistor, a diode, a system on a chip, a flash memory, a dynamic random access memory, a static random access memory, an electrically erasable programmable read-only memory, an image sensor, a microelectromechanical system, an active device, or a passive device. The device component can be electrically isolated from an adjacent device component by an insulating structure, such as a shallow trench isolation.

[0125] Referring to Figure 2 and Figure 3 In some embodiments, the first insulator layer 103 can be fabricated from, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon nitride oxide, flowable oxide, silicon aluminate, undoped quartz glass, borosilicate glass, phosphosilicate glass, borophosphosilicate glass, plasma-enhanced tetraethyl orthosilicate, fluorosilicate glass, carbon-doped silicon oxide, organosilicate glass, low-k dielectric material, or a combination thereof.

[0126] In some embodiments, the fabrication technique of the first insulating layer 103 can include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride nitride, polyimide, polybenzoxazole, phosphosilicate glass, undoped quartz glass, or fluorosilicate glass. The first insulating layer 103 can be referred to as a passivation layer.

[0127] In some embodiments, the first insulating layer 103 can include a bottom passivation layer (not shown for clarity) and a top passivation layer (not shown for clarity). The bottom passivation layer can be formed on the substrate 101. The top passivation layer can be formed on the bottom passivation layer. The fabrication technique of the bottom passivation layer can include, for example, silicon oxide or phosphosilicate glass. The fabrication technique of the top passivation layer can include, for example, silicon nitride, silicon oxynitride, or silicon oxynitride nitride. The bottom passivation layer can serve as a stress buffer to reduce the stress impact between the top passivation layer and the substrate 101. The top passivation layer can serve as a high vapor barrier to prevent moisture from entering from above.

[0128] In some embodiments, the fabrication technique of the first insulating layer 103 can include a different kind of material than the first hardmask layer 301. Specifically, the fabrication technique of the first insulating layer 103 can include a material that is etch-selective to the first hardmask layer 301.

[0129] Reference is made to Figure 2 and Figure 3 In some embodiments, the fabrication technique of the first hardmask layer 301 includes, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride nitride, the like, or a combination thereof. The fabrication technique of the first hardmask layer 301 can use a deposition process, such as a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, a low-pressure chemical vapor deposition process, or the like.

[0130] It should be understood that in the description of the present disclosure, silicon oxynitride refers to a material containing silicon, nitrogen, and oxygen, in which the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxynitride nitride refers to a material containing silicon, oxygen, nitrogen, and the proportion of nitrogen is greater than the proportion of oxygen.

[0131] Alternatively, in some embodiments, the fabrication technique of the first hardmask layer 301 can include, for example, a carbon film. The term "carbon film" is used herein to describe a material whose mass is predominantly carbon, whose structure is defined primarily by carbon atoms, or whose physical and chemical properties are determined by its carbon content. The term "carbon film" is intended to exclude materials that are simple mixtures or compounds including carbon, for example, dielectric materials such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polysilicon. These terms do include, for example, graphite, charcoal, and halocarbons.

[0132] In some embodiments, the carbon film fabrication technique can be deposited by a process that includes introducing a process gas mixture into a process chamber, where the process gas mixture includes one or more hydrocarbons. The hydrocarbons have a molecular formula of CxHy, where x has a range of 2 to 4, and y has a range of 2 to 10. The hydrocarbons can be, for example, propylene (C3H6), propyne (C3H4), propane (C3H8), butane (C4H10), butene (C4H8), butadiene (C4H6), or acetylene (C2H2), or combinations thereof. In some embodiments, partially or fully fluorinated derivatives of the hydrocarbons can be used. The doped derivatives include boron-containing derivatives of the hydrocarbons and fluorinated derivatives thereof.

[0133] In some embodiments, the carbon film fabrication technique can be deposited by the process gas mixture while maintaining a substrate temperature in a range of about 1000C to about 7000C. In particular, in a range of about 3500C to about 5500C. In some embodiments, the carbon film fabrication technique can be deposited by the process gas mixture while maintaining a chamber pressure in a range of about 1 Torr to about 20 Torr. In some embodiments, the carbon film fabrication technique can be deposited by the process gas mixture by introducing the hydrocarbon gas and any inert or reactive gas at a flow rate in a range of about 50 seem (standard cubic centimeters per minute) to about 2000 seem, respectively.

[0134] In some embodiments, the process gas mixture can also include an inert gas, such as argon. However, other inert gases, such as nitrogen or other noble gases, such as helium, can also be used. The inert gas can control the density and deposition rate of the carbon film. In addition, various gases can be added to the process gas mixture to alter the properties of the carbon film. The various gases can be a reactive gas, such as hydrogen, ammonia, a mixture of hydrogen and nitrogen, or combinations thereof. The addition of hydrogen or ammonia can control the hydrogen ratio of the carbon film to control layer properties, such as etch selectivity, chemical mechanical polishing resistance properties, and reflectivity. In some embodiments, a mixture of reactive and inert gases can be added to the process gas mixture to deposit the carbon film.

[0135] The carbon film can include carbon atoms and hydrogen atoms, which can be an adjustable carbon to hydrogen ratio in a range of about 10% hydrogen to about 60% hydrogen. Controlling the hydrogen ratio of the carbon film can adjust the corresponding etch selectivity and chemical mechanical polishing resistance properties. As the hydrogen content is decreased, the etch resistance and selectivity of the carbon film increases. The decreased removal rate of the carbon film can make the carbon film suitable as a mask layer when performing an etch process to transfer a desired pattern to an underlying layer.

[0136] In some embodiments, the fabrication technique of the first hard mask layer 301 can include, for example, boron nitride, boron nitride silicon, boron phosphorus nitride, or boron carbon nitride silicon. In some embodiments, the fabrication technique of the first hard mask layer 301 can include assistance of a process, such as a plasma process, an ultraviolet (UV) curing process, a thermal annealing process, or a combination thereof. A substrate temperature of the fabrication technique of the first hard mask layer 301 can be in a range from about 20 °C to about 1000 °C. A process pressure of the fabrication technique of the first hard mask layer 301 can be in a range from about 10 mTorr to about 760 Torr.

[0137] When the fabrication technique of the first hard mask layer 301 is assisted by the plasma process, the plasma of the plasma process can be provided by an RF power. In some embodiments, the RF power can be in a range from about 2 W (watt) to about 5000 W at a single low frequency in a range from about 100 kHz to about 1 MHz. In some embodiments, the RF power can be in a range from about 30 W to about 1000 W at a single high frequency greater than about 13.6 MHz.

[0138] When the fabrication technique of the first hard mask layer 301 is assisted by the UV curing process, the UV curing process can employ any UV light source, such as a mercury microwave arc lamp, a pulsed xenon flash lamp, or a high-efficiency UV light-emitting diode array. The UV light source can have a wavelength in a range from about 170 nm to about 400 nm. The UV light source can provide a photon energy in a range from about 0.5 eV to about 10 eV; specifically, in a range from about 1 eV to about 6 eV. The assistance of the UV curing process can remove hydrogen from the first hard mask layer 301. Since hydrogen can diffuse to other regions of the semiconductor element 1A and can degrade the reliability of the semiconductor element 1A, the removal of hydrogen by the assistance of the UV curing process can improve the reliability of the semiconductor element 1A. In addition, the UV curing process can increase the density of the first hard mask layer 301.

[0139] Reference Figure 2 and Figure 3The first hard mask openings 303 can be formed along the first hard mask layer 301. Portions of the first insulating layer 103 can be exposed through the first hard mask openings 303. In a top view, the first hard mask openings 303 can be arranged in a grid-like pattern. The first hard mask openings 303 can be equidistantly disposed along a first axis X and a second axis Y. The first axis X and the second axis Y are perpendicular to each other. Specifically, a distance Dl between a pair of adjacent first hard mask openings 303 along the first axis X can be equal to a distance D2 between a pair of adjacent first hard mask openings 303 along the second axis Y. In a cross-sectional view, a ratio of a width Wl of the first hard mask openings 303 to a height Hl of the first hard mask openings 303 can be in a range of about 5: 1 to about 1: 15, in a range of about 3: 1 to about 1: 13, in a range of about 1: 1 to about 1: 11, and in a range of about 5: 1 to about 1: 8.

[0140] Figure 4 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is illustrated. Figure 5 A cross-sectional view schematic diagram of the intermediate semiconductor element along line A-A' according to an embodiment of the present disclosure is illustrated. Figure 4 A cross-sectional view schematic diagram of the intermediate semiconductor element along line A-A' according to an embodiment of the present disclosure is illustrated.

[0141] Referring to FIG. 1, a method 10 for forming a semiconductor element is illustrated. Figure 1 and Figure 4 and Figure 5 A first oblique etching process 401 can be performed to form first oblique recesses 305 along the first insulating layer 103. The corresponding step is illustrated as step S13 in the method 10 as shown in FIG. 1. Figure 1

[0142] Referring to FIG. 1, a method 10 for forming a semiconductor element is illustrated. Figure 4 and Figure 5 The first oblique etching process 401 can use the first hard mask layer 301 as a pattern guide to remove portions of the first insulating layer 103 and simultaneously form the first oblique recesses 305 along the first insulating layer 103. In a cross-sectional view, the first oblique recesses 305 can be formed adjacent to the first side FS of the first hard mask layer 301.

[0143] In some embodiments, the incident angle a of the first oblique etching process 401 can be defined by a width Wl of the first hard mask openings 303 and a height Hl of the first hard mask openings 303.

[0144] In some embodiments, the incident angle a of the first oblique etching process 401 can be in a range of about 5 degrees to about 80 degrees. In some embodiments, the incident angle a of the first oblique etching process 401 can be in a range of about 20 degrees to about 60 degrees. In some embodiments, the incident angle a of the first oblique etching process 401 can be in a range of about 20 degrees to about 40 degrees.

[0145] ​In some embodiments, the first oblique etching process 401 can be a non-isotropic etching process, such as a reactive ion etching process. The reactive ion etching process can include an etching gas and a passivation gas, which can suppress isotropic effects to limit material removal in the horizontal direction. The etching gas can include chlorine and boron trichloride. The passivation gas can include fluoroform or other suitable halocarbon. In some embodiments, the first hard mask layer 301 is made of a carbon film, which can serve as a halocarbon source for the passivation gas of the reactive ion etching process.

[0146] In some embodiments, the first insulating layer 103 can have a faster etching rate than the first hard mask layer 301 during the first oblique etching process 401. For example, the etching rate ratio of the first insulating layer 103 to the first hard mask layer 301 during the first oblique etching process 401 can be in a range of about 100: 1 to about 1.05: 1, about 100: 1 to about 10: 1, about 50: 1 to about 10: 1, about 30: 1 to about 10: 1, about 20: 1 to about 10: 1, or about 15: 1 to about 10: 1.

[0147] Reference is made to Figure 4 and Figure 5 The width W2 of the first oblique recess 305 can be less than the width Wl of the first hard mask opening 303. The acute angle β is between the bottom surface 305BS of the first oblique recess 305 and the sidewall 305SW of the first oblique recess 305, which can be in a range of about 10 degrees to about 85 degrees, about 20 degrees to about 80 degrees, about 45 degrees to about 80 degrees, about 60 degrees to about 80 degrees, and about 70 degrees to about 80 degrees. In some embodiments, the first oblique recess 305 can extend in the first direction El. The first direction El can be oblique to the axis Z and the first axis X.

[0148] Figure 6 A top view schematic diagram of an intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figures 7 to 9 A cross-sectional view schematic diagram along line A-A' of the intermediate semiconductor element according to an embodiment of the present disclosure is shown. Figure 6 Some components are not shown in the cross-sectional view for the sake of clarity. Figure 6

[0149] Reference is made to Figure 1 and Figure 6 and Figure 7 The first hard mask layer 301 can be removed. The corresponding step is illustrated as step S15 in the method 10 as shown in FIG. 10. Figure 1

[0150] Reference is made to Figure 6 ​​and Figure 7 The first hard mask layer 301 can be removed by a hard mask etching process. The hard mask etching process can be a non-isotropic dry etching process or a wet etching process. In some embodiments, the etching rate of the first hard mask layer 301 by the hard mask etching process can be faster than the etching rate of the first insulating layer 103 by the hard mask etching process. For example, the etching rate ratio of the first insulating layer 103 to the first hard mask layer 301 during the hard mask etching process can be in a range of about 100: 1 to about 1.05: 1, in a range of about 100: 1 to about 10: 1, in a range of about 50: 1 to about 10: 1, in a range of about 30: 1 to about 10: 1, in a range of about 20: 1 to about 10: 1, or in a range of about 15: 1 to about 10: 1.

[0151] Referring to Figure 6 In a top view, the first inclined grooves 305 can be arranged in a grid point pattern. The first inclined grooves 305 can be equidistantly arranged along the first axis X and the second axis Y. Specifically, the distance D3 between a pair of adjacent first inclined grooves 305 along the first axis X can be equal to the distance D4 between a pair of adjacent first inclined grooves 305 along the second axis Y. Portions of the substrate 101 can be exposed by the first inclined grooves 305.

[0152] In some embodiments, after the first hard mask layer 301 is removed, a cleaning process and a passivation process can be performed on the first inclined grooves 305. The cleaning process can remove the oxide (from oxidation by oxygen in the air) on the top surface of the conductive features of the topmost semiconductor layer in the substrate 101 without damaging the conductive features of the topmost semiconductor layer in the substrate 101. The cleaning process can include applying a mixture of hydrogen and argon as a remote plasma source to the first inclined grooves 305. A process temperature of the cleaning process can be in a range of about 250 °C to about 350 °C. A process pressure of the cleaning process can be in a range of about 1 Torr to about 10 Torr. A bias energy can be applied to the apparatus performing the cleaning process. The bias energy can be in a range of about 0 W to 200 W.

[0153] The passivation process can include soaking the intermediate semiconductor element after the cleaning process with a precursor such as dimethylaminotrimethylsilane, tetramethylsilane, or the like at a process temperature in a range of about 200 °C to about 400 °C. An ultraviolet radiation can facilitate the passivation process. The passivation process can passivate the sidewalls of the first insulating layer 103 exposed by the first inclined grooves 305 by sealing the surfaces thereof. Poor sidewall growth (which can affect the electrical properties of the semiconductor element 1A) can be reduced by the passivation process. Thus, the performance and reliability of the semiconductor element 1A can be improved.

[0154] Referring to Figure 1 and Figure 8 and Figure 9 , a first sloped conductive layer 201 can be formed in the first sloped recess 305, and a top conductive layer 203 can be formed to cover the first sloped conductive layer 201. The corresponding steps are illustrated in step S17 of the method 10 as shown in Figure 1

[0155] Referring to Figure 8 , the fabrication technique of the first sloped conductive layer 201 can completely fill the first sloped recess 305 and cover the top surface of the first insulating layer 103. In some embodiments, the fabrication technique of the first sloped conductive layer 201 includes tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof. The fabrication technique of the first sloped conductive layer 201 can be through a deposition process, such as a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, or a sputtering process. A planarization process (e.g., a chemical mechanical polishing process) can be performed until the top surface of the first insulating layer 103 is exposed to remove excess material and provide a substantially planar surface for subsequent process steps.

[0156] Referring to Figure 8 , in a cross-sectional view, the shape of the first sloped conductive layer 201 can be defined by the first sloped recess 305. That is, an acute angle γ between the bottom surface 201BS of the first sloped conductive layer 201 and the sidewall 201SW of the first sloped conductive layer 201 can be in a range of about 10 degrees to about 85 degrees, in a range of about 20 degrees to about 80 degrees, in a range of about 45 degrees to about 80 degrees, in a range of about 60 degrees to about 80 degrees, and in a range of about 70 degrees to about 80 degrees. In some embodiments, the first sloped conductive layer 201 can extend in the first direction E1.

[0157] Referring to Figure 9 , a second insulating layer 105 can be formed on the first insulating layer 103. The fabrication technique of the second insulating layer 105 includes silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, the like, or a combination thereof. The low-k dielectric material can have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric material can have a dielectric constant less than 2.0. The fabrication technique of the second insulating layer 105 can be through, for example, a chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, an evaporation process, or a spin-on process.

[0158] Referring to Figure 9 ​The top conductive layer 203 can be formed in the second insulating layer 105 and cover the top surface 201TS of the first tilted conductive layer 201. In some embodiments, the fabrication technique of the top conductive layer 203 includes, for example, copper, aluminum, titanium, tungsten, the like, or combinations thereof. The fabrication technique of the top conductive layer 203 can be a damascene process. The first tilted conductive layer 201 can be referred to as a conductive via of the semiconductor device 1A, and the top conductive layer 203 can be referred to as a conductive wire of the semiconductor device 1A.

[0159] Figure 10 as well as Figure 11 Another embodiment of this disclosure is illustrated along Figure 6 A cross-sectional view of line A-A' in the middle.

[0160] refer to Figure 10 To fabricate semiconductor device 1B, the fabrication technique for an intermediate semiconductor device can be similar to... Figures 2 to 7 An illustrative process is described. A first conductive material 307 layer can completely fill the first inclined groove 305 and cover the top surface of the first insulating layer 103. The first conductive material 307 can be aluminum, copper, an aluminum-copper alloy, an aluminum alloy, or a copper alloy. The fabrication technique for the first conductive material 307 layer can be a deposition process, such as physical vapor deposition, chemical vapor deposition, or sputtering. A planarization process (e.g., chemical mechanical polishing) can be performed to provide a substantially flat surface for subsequent process steps. The first conductive material 307 layer fills a conductive via in the first inclined groove 305, which may be referred to as semiconductor element 1B.

[0161] refer to Figure 11 A lithography process can be performed to define a desired pattern for the first conductive material 307 layer. An etching process can then be performed to remove portions of the first conductive material 307 layer and simultaneously form a top conductive layer 203 having the desired pattern. The top conductive layer 203 may be referred to as a pad layer of the semiconductor device 1B.

[0162] Figure 12 as well as Figure 13 Another embodiment of this disclosure is illustrated along Figure 6 A cross-sectional view of line A-A' in the middle.

[0163] refer to Figure 12 To fabricate semiconductor device 1C, the fabrication technique of an intermediate semiconductor device can be similar to... Figures 2 to 7An illustrative process is described. The barrier layer 207 may be conformally formed in the first inclined groove 305. Fabrication techniques for the barrier layer 207 include, for example, titanium, titanium nitride, silicon titanium nitride, tantalum, tantalum nitride, silicon tantalum nitride, or combinations thereof. The barrier layer 207 may be fabricated using a deposition process, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or sputtering. In some embodiments, the barrier layer 207 may have a thickness ranging from approximately 10 angstroms to approximately 15 angstroms. In some embodiments, the barrier layer 207 may have a thickness ranging from approximately 11 angstroms to approximately 13 angstroms.

[0164] refer to Figure 13 The top conductive layer 203 can be similar to Figure 10 The process illustrated in 11 is formed on the barrier layer 207. The barrier layer 207 can serve as a bonding layer between the topmost conductor in the first inclined conductive layer 201 and the substrate 101. The barrier layer 207 can also prevent metal ions from the first inclined conductive layer 201 or the top conductive layer 203 from diffusing into the first insulating layer 103 or the substrate 101.

[0165] Figure 14 Another embodiment of this disclosure is illustrated along Figure 6 A cross-sectional view of line A-A' in the middle.

[0166] refer to Figure 14 To fabricate a semiconductor device 1D, the fabrication technique for an intermediate semiconductor device can be similar to... Figures 2 to 7 An illustrative process is described. The top conductive layer 203 can completely fill the first inclined groove 305 and cover a portion of the top surface of the first insulating layer 103. The fabrication techniques for the top conductive layer 203 include, for example, tin, silver, copper, gold, alloys, or combinations thereof. The top conductive layer 203 may be referred to as a solder unit of the semiconductor device 1D.

[0167] During a wiring process, a solder cell formation process, or a packaging process, stress may be applied to a semiconductor device, and this stress may cause delamination of the first insulating layer 103. To reduce the stress effects of the above processes, the first inclined groove 305 can serve as a buffer space to reduce the stress of the above processes, reduce warpage of the semiconductor device 1D, and prevent delamination of the layer beneath the first insulating layer 103.

[0168] Figure 15 Another embodiment of this disclosure is illustrated along Figure 6 A cross-sectional view of line A-A' in the middle.

[0169] refer to Figure 15 To fabricate semiconductor device 1E, the fabrication technique of an intermediate semiconductor device can be similar to... Figures 2 to 7The under bump metallization layer 209 can be conformally formed in the first inclined recess 305. The under bump metallization layer 209 can be a single layer structure or a multi-layer stack structure. For example, the under bump metallization layer 209 can include a first conductive layer, a second conductive layer, and a third conductive layer sequentially stacked. The first conductive layer can serve as a bonding layer to stably bond the top conductive layer 203 to the substrate 101 and the first insulating layer 103. For example, the first conductive layer can include at least one of titanium, titanium tungsten, chromium, and aluminum. The second conductive layer can serve as a barrier layer to prevent a conductive material contained in the under bump metallization layer 209 from diffusing into the substrate 101 or the first insulating layer 103. The second conductive layer can include at least one of copper, nickel, chromium copper, and nickel vanadium. The third conductive layer can serve as a sublayer to form the top conductive layer 203 or a wetting layer to improve the wetting properties of the top conductive layer 203. The third conductive layer can include at least one of nickel, copper, and aluminum. The fabrication technique of the top conductive layer 203 can use similar processes as the fabrication technique of the under bump metallization layer 209. Figure 14 An exemplary fabrication process.

[0170] Figures 16 to 17 An exemplary top view schematic diagram of an intermediate semiconductor element according to another embodiment of the present disclosure.

[0171] Reference Figure 16 To fabricate the semiconductor element 1F, a fabrication technique of an intermediate semiconductor element can use similar processes as the fabrication technique of the semiconductor element 1E. Figures 2 to 5 An exemplary fabrication process. The first hard mask openings 303 can be arranged in a diagonal point pattern. The first hard mask openings 303 can be classified into two groups. The first group of the first hard mask openings 303 can be disposed along a first group of columns R1. The second group of the first hard mask openings 303 can be disposed along a second group of columns R2. The first group of columns R1 and the second group of columns R2 can be parallel to the first axis X. The first group of columns R1 and the second group of columns R2 can be alternately arranged. As for the second axis Y, the first hard mask openings 303 disposed along the second group of columns R2 can be offset from the first hard mask openings 303 disposed along the first group of columns R1. Since the fabrication technique of the first inclined recess 305 can use the first hard mask layer 301 and the first hard mask openings 303 as a pattern guide, the arrangement of the first inclined recess 305 can be similar to the arrangement of the first hard mask openings 303.

[0172] Reference Figure 17 Similar to the fabrication technique of the semiconductor element 1E, the fabrication technique of the semiconductor element 1F can use the first hard mask layer 301 and the first hard mask openings 303 as a pattern guide. Figures 6 to 8 An exemplary fabrication process can be performed on the semiconductor element 1E. Figure 16The intermediate semiconductor element in the process. The arrangement of the first tilted conductive layer 201 can be defined by the arrangement of the first tilted groove 305. That is, the first tilted conductive layer 201 can also be arranged in a diagonal dot pattern. Specifically, the first tilted conductive layer 201 can also be classified into two groups. The first tilted conductive layer 201 of the first group can be disposed along column R1 of the first group. The first tilted conductive layer 201 of the second group can be disposed along column R2 of the second group. Column R1 of the first group and column R2 of the second group can be parallel to the first axis X. Column R1 of the first group and column R2 of the second group can be arranged alternately. As for the second axis Y, the first tilted conductive layer 201 disposed along column R2 of the second group can be offset from the first tilted conductive layer 201 disposed along column R1 of the first group.

[0173] The arrangement of the first tilted conductive layers 201 in a diagonal dot pattern maximizes the distance between any two adjacent first tilted conductive layers 201. Therefore, the parasitic capacitance between the first tilted conductive layers 201 can be minimized.

[0174] Figure 18 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 19 Another embodiment of this disclosure is illustrated along Figure 18 A cross-sectional view of line A-A' in the middle.

[0175] refer to Figures 18 to 19 To fabricate semiconductor device 1G, the fabrication technique of an intermediate semiconductor device can be similar to... Figures 2 to 5 An illustrative process. In a top view, the first hard mask opening 303 may be arranged in a diagonal dot pattern, and the first inclined groove 305 may be arranged in a similar pattern to the first hard mask opening 303. In a cross-sectional view, the first inclined groove 305 may have an acute angle β, which is similar to... Figure 5 An acute angle β is illustrated, and the first inclined groove 305 can extend in the first direction E1. After the first inclined groove 305 is formed, the first hard mask layer 301 can be removed.

[0176] Figure 20 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 21 Another embodiment of this disclosure is illustrated along Figure 20 A cross-sectional view of line A-A' in the middle.

[0177] refer to Figure 20 as well as Figure 21 The fabrication technique for forming the second hard mask layer 309 on the first insulating layer 103 can be similar to... Figure 2 as well as Figure 3Fabrication of the first hard mask layer 301. The second hard mask layer 309 can be fabricated using the same material as the first hard mask layer 301, but is not limited thereto. The second hard mask openings 311 can be formed in the second hard mask layer 309. In a top view, the second hard mask openings 311 can be arranged in a diagonal line pattern. The second hard mask openings 311 can be arranged vertically or horizontally between a pair of adjacent first inclined grooves 305. In other words, the first inclined grooves 305 and the second hard mask openings 311 can be alternately arranged along the first axis X and the second axis Y. That is, the first inclined grooves 305 and the second hard mask openings 311 can be staggered. In a cross-sectional view, the ratio of the width W3 of the second hard mask openings 311 to the height H2 of the second hard mask openings 311 can be in a range of about 5:1 to about 1:15, in a range of about 3:1 to about 1:13, in a range of about 1:1 to about 1:11, and in a range of about 5:1 to about 1:8.

[0178] Referring to Figure 20 and Figure 21 The second inclined etching process 403 can use the second hard mask layer 309 as a pattern guide to remove portions of the first insulating layer 103 and simultaneously form the second inclined grooves 313 in the first insulating layer 103. In some embodiments, the incident angle δ of the second inclined etching process 403 can have the same value as the incident angle α of the first inclined etching process 401, but the incident direction of the second inclined etching process 403 can be opposite to the incident direction of the first inclined etching process 401. In other words, the incident angle δ of the second inclined etching process 403 can be opposite to the incident angle α of the first inclined etching process 401.

[0179] In some embodiments, the second inclined etching process 403 can be a non-isotropic etching process, such as a reactive ion etching process. The process parameters of the second inclined etching process 403 can be the same as those of the first inclined etching process 401, except for the incident angle.

[0180] In some embodiments, the incident angle δ of the second inclined etching process 403 can be in a range of about -5 degrees to about -80 degrees, in a range of about -20 degrees to about -60 degrees, and in a range of about -20 degrees to about -40 degrees.

[0181] In some embodiments, the incident angle δ of the second inclined etching process 403 can be defined by the width W3 of the second hard mask layer 309 and the height H2 of the second hard mask openings 311.

[0182] In some embodiments, the etching rate of the first insulating layer 103 in the second oblique etching process 403 can be faster than the etching rate of the second hard mask layer 309 in the second oblique etching process 403. For example, the etching rate ratio of the first insulating layer 103 to the second hard mask layer 309 during the second oblique etching process 403 can be in a range from about 100: 1 to about 1.05: 1, in a range from about 100: 1 to about 10: 1, in a range from about 50: 1 to about 10: 1, in a range from about 30: 1 to about 10: 1, in a range from about 20: 1 to about 10: 1, or in a range from about 15: 1 to about 10: 1.

[0183] Referring to Figure 20 and Figure 21 , the width W4 of the second oblique recess 313 can be less than the width W3 of the second hard mask opening 313. In some embodiments, an acute angle ε between the bottom surface 313BS of the second oblique recess 313 and the sidewall 313SW of the second oblique recess 313 can be different from or opposite to the acute angle β between the bottom surface 305BS of the first oblique recess 305 and the sidewall 305SW of the first oblique recess 305. In some embodiments, the acute angle ε between the bottom surface 313BS of the second oblique recess 313 and the sidewall 313SW of the second oblique recess 313 can be in a range from about -10 degrees to about -85 degrees, in a range from about -20 degrees to about -80 degrees, in a range from about -45 degrees to about -80 degrees, in a range from about -60 degrees to about -80 degrees, and in a range from about -70 degrees to about -80 degrees.

[0184] In some embodiments, the second oblique recess 313 can extend in the first direction E1. In some embodiments, the second oblique recess 313 can extend in the second direction E2. The second direction E2 can be oblique with respect to the Z-axis and the first axis X, and with respect to the Z-axis, the second direction E2 can be opposite to the first direction E1.

[0185] Figure 22 A top view schematic diagram of an intermediate semiconductor element illustrating another embodiment of the present disclosure. Figure 23 A cross-sectional view schematic diagram along line A-A' of the intermediate semiconductor element illustrating another embodiment of the present disclosure. Figure 22 A cross-sectional view schematic diagram along line A-A' of the intermediate semiconductor element illustrating another embodiment of the present disclosure.

[0186] Referring to Figure 22 and Figure 23 , similar to Figure 6 and Figure 7 and Figure 8The exemplary process can be performed to remove the second hard mask layer 309 and form the first slanted conductive layer 201, the second slanted conductive layer 205, and the top conductive layer 203. The first slanted conductive layer 201 can be formed in the first slanted recess 305 and can have the same shape as the first slanted recess 305. The first slanted conductive layer 201 can be formed in the first slanted recess 305 by depositing a conductive material in the first slanted recess 305. The conductive material can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or other suitable deposition techniques. The conductive material can be a metal, a metal alloy, a conductive metal oxide, or other suitable conductive material. The conductive material can be deposited to a thickness of about 1000 angstroms to about 5000 angstroms, about 1500 angstroms to about 4500 angstroms, about 2000 angstroms to about 4000 angstroms, about 2500 angstroms to about 3500 angstroms, and about 3000 angstroms to about 3500 angstroms. The first slanted conductive layer 201 can be formed by depositing a conductive material in the first slanted recess 305 to a thickness of about 1000 angstroms to about 5000 angstroms, about 1500 angstroms to about 4500 angstroms, about 2000 angstroms to about 4000 angstroms, about 2500 angstroms to about 3500 angstroms, and about 3000 angstroms to about 3500 angstroms. Figure 8 Exemplary acute angle and extension direction.

[0187] The second slanted conductive layer 205 can be formed in the second slanted recess 313. In a cross-sectional view, the shape of the second slanted conductive layer 205 can be defined by the second slanted recess 313. That is, an acute angle ζ between the bottom surface 205BS of the second slanted conductive layer 205 and the sidewall 205SW of the second slanted conductive layer 205 can be in a range of about negative 10 degrees to about negative 85 degrees, about negative 20 degrees to about negative 80 degrees, about negative 45 degrees to about negative 80 degrees, about negative 60 degrees to about negative 80 degrees, and about negative 70 degrees to about negative 80 degrees. In some embodiments, one of the first slanted conductive layers 201 and one of the adjacent second slanted conductive layers 205 can extend in different directions. In some embodiments, the second slanted conductive layer 205 can extend in the second direction E2.

[0188] The top conductive layer 203 can be formed on the first insulating layer 103 and cover the first slanted conductive layer 201 and the second slanted conductive layer 205.

[0189] Figure 24 Exemplary top view schematic of an intermediate semiconductor element of another embodiment of the disclosure. Figure 25 Exemplary cross-sectional view schematic along line A-A' of another embodiment of the disclosure. Figure 24 Exemplary cross-sectional view schematic along line B-B' of another embodiment of the disclosure.

[0190] Reference is made to Figure 24 and Figure 25 To fabricate the semiconductor element 1H, the fabrication technique of the intermediate semiconductor element can be similar to the fabrication technique of the semiconductor element 1G. Figures 2 to 5 Exemplary process. In a top view, the first hard mask openings 303 can be arranged along a first set of columns R1. The first set of columns R1 can be parallel to the first axis X. The arrangement of the first slanted recesses 305 can be similar to the arrangement of the first hard mask openings 303. In a cross-sectional view, the first slanted recesses 305 can have a similar shape as the first hard mask openings 303. The first slanted recesses 305 can be formed by etching the first insulating layer 103 in the first slanted recesses 305. The first slanted recesses 305 can be formed by dry etching, wet etching, or other suitable etching techniques. The first slanted recesses 305 can be formed to a depth of about 1000 angstroms to about 5000 angstroms, about 1500 angstroms to about 4500 angstroms, about 2000 angstroms to about 4000 angstroms, about 2500 angstroms to about 3500 angstroms, and about 3000 angstroms to about 3500 angstroms. Figure 5 Exemplary acute angle and extension direction. After forming the first slanted recesses 305, the first hard mask layer 301 can be removed.

[0191] Figure 26 Exemplary top view schematic of an intermediate semiconductor element of another embodiment of the disclosure. Figure 27 Exemplary cross-sectional view schematic along line B-B' of another embodiment of the disclosure. Figure 26 Exemplary cross-sectional view schematic along line B-B' of another embodiment of the disclosure.

[0192] refer to Figure 26 as well as Figure 27 Similar to Figure 20 as well as Figure 21 The illustrated process can be performed. In a top view, the second hard mask opening 311 can be arranged along the column R2 of the second group. The column R2 of the second group can be parallel to the first axis X. The columns R1 of the first group and the columns R2 of the second group can be arranged alternately; in other words, the columns R1 of the first group and the columns R2 of the second group can be staggered. The arrangement of the second inclined grooves 313 can be similar to the arrangement of the second hard mask openings 311. In a cross-sectional view, the second inclined grooves 313 can have a similar shape to... Figure 21 Examples of acute angles and directions of extension.

[0193] Figure 28 A top view schematic diagram illustrating an intermediate semiconductor element according to another embodiment of the present disclosure. Figure 29 Another embodiment of this disclosure is illustrated along Figure 28 A cross-sectional view of the C-C' line.

[0194] refer to Figure 28 as well as Figure 29 Similar to Figure 22 as well as Figure 23 The illustrated process can be performed to remove the second hard mask layer 309 and form a first inclined conductive layer 201, a second inclined conductive layer 205, and a top conductive layer 203. In a cross-sectional view, the first inclined conductive layer 201 can be formed in the first inclined groove 305 and can have the same... Figure 23 The acute angle γ and the direction of extension are illustrated. The second inclined conductive layer 205 can be formed in the second inclined groove 313 and can have the same... Figure 23 The acute angle ζ and the direction of extension are illustrated. In a top view, the first tilted conductive layer 201 may be disposed along column R1 of the first group and the second tilted conductive layer 205 may be disposed along column R2 of the second group. Due to the different incident directions of the first tilted etching process 401 and the second tilted etching process 403, the second tilted conductive layer 205 may be offset from the first tilted conductive layer 201 relative to the second axis Y.

[0195] The top conductive layer 203 can be formed on the first insulating layer 103 and cover the first inclined conductive layer 201 and the second inclined conductive layer 205.

[0196] One embodiment of this disclosure provides a semiconductor device comprising: a substrate, a first insulating layer disposed on the substrate, a first inclined conductive layer disposed in the first insulating layer, and a top conductive layer disposed to cover the first inclined conductive layer.

[0197] Another embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate, forming a first insulating layer on the substrate, forming a first inclined groove along the first insulating layer, and forming a first inclined conductive layer in the first inclined groove and a top conductive layer covering the first inclined conductive layer.

[0198] Due to the design of the semiconductor device of the present disclosure, the first inclined conductive layer 201 can provide more contact surface with the substrate 201. Therefore, the electrical characteristics of the semiconductor device can be improved. That is, the performance of the semiconductor device can be improved. In addition, the manufacturing technique of the narrower first inclined groove 305 can use the first hard mask layer 301 with the wider first hard mask opening 303. In other words, the requirement of the lithography process for forming the narrower first inclined groove can be reduced. Therefore, the yield of the semiconductor device can be improved.

[0199] While the present disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes can be under taken in an alternative order, and / or the processes described can be modified or combined. Furthermore, where a description of a processes uses terms like "comprising", "having", "including", or "carrying", such processes are open-ended, and should be interpreted to mean that the processes include a particular element or step but not excluding others.

[0200] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure of one or more embodiments of the present application is intended to be illustrative, but not limiting, of the scope of the present application. Thus, it is intended that the scope of the present application should be determined by the appended claims and equivalents thereof.

Claims

1. A semiconductor device, comprising: a substrate; a first insulating layer disposed on the substrate; a first inclined recess disposed in the first insulating layer; a first inclined conductive layer disposed in the first inclined recess, the first inclined conductive layer having a first acute angle formed between a bottom surface of the first inclined conductive layer and a sidewall of the first inclined conductive layer; a second inclined recess disposed in the first insulating layer; a second inclined conductive layer disposed in the second inclined recess, the second inclined conductive layer having a second acute angle formed between a bottom surface of the second inclined conductive layer and a sidewall of the second inclined conductive layer, wherein the first inclined conductive layer extends in a first direction, the second inclined conductive layer extends in a second direction, and the second direction is opposite to the first direction; and a top conductive layer disposed to cover the first inclined conductive layer and the second inclined conductive layer.

2. The semiconductor device of claim 1, wherein the first acute angle is in a range of about 10 degrees to about 85 degrees.

3. The semiconductor device of claim 2, wherein the first inclined conductive layer is arranged in a grid dot pattern in a top view.

4. The semiconductor device of claim 2, wherein the first inclined conductive layer is arranged in a diagonal dot pattern in a top view.

5. The semiconductor device of claim 3, wherein the top conductive layer is a wire, and a fabrication technique of the top conductive layer includes copper, aluminum, titanium, tungsten, or a combination thereof.

6. The semiconductor device of claim 5, further comprising a barrier layer disposed between the first insulating layer and the first inclined conductive layer, between the top conductive layer and the first insulating layer, and between the first inclined conductive layer and the substrate, wherein a fabrication technique of the barrier layer includes titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, silicon tantalum nitride, or a combination thereof.

7. The semiconductor device of claim 6, wherein a thickness of the barrier layer is in a range of about 10 angstroms to about 15 angstroms.

8. The semiconductor device of claim 2, wherein the top conductive layer is a solder unit, and a fabrication technique thereof includes tin, silver, copper, gold, alloy, or a combination thereof.

9. The semiconductor device of claim 8, further comprising an under bump metallization layer disposed between the first insulating layer and the first inclined conductive layer, between the top conductive layer and the first insulating layer, and between the first inclined conductive layer and the substrate, wherein the under bump metallization layer includes titanium, titanium-tungsten, chromium, aluminum, copper, nickel, chromium-copper, or nickel-vanadium.

10. The semiconductor device of claim 1, wherein the second acute angle is in a range of about -10 degrees to about -85 degrees.

11. The semiconductor device of claim 1, wherein the first inclined conductive layer and the second inclined conductive layer are alternately arranged along a first axis and a second axis in a top view, and the first axis and the second axis are perpendicular to each other. ​ ​ ​ ​ ​ ​ ​ 12. The semiconductor device of claim 11, wherein the first sloped conductive layers are arranged along a first set of columns, the second sloped conductive layers are arranged along a second set of columns, and the first set of columns are arranged alternately with the second set of columns.

13. A method for fabricating a semiconductor device, comprising: providing a substrate; forming a first insulating layer on the substrate; forming a first sloped recess along the first insulating layer; forming a first sloped conductive layer in the first sloped recess, the first sloped conductive layer having a first acute angle formed between a bottom surface of the first sloped conductive layer and a sidewall of the first sloped conductive layer; forming a second sloped recess along the first insulating layer; forming a second sloped conductive layer in the second sloped recess, the second sloped conductive layer having a second acute angle formed between a bottom surface of the second sloped conductive layer and a sidewall of the second sloped conductive layer, wherein the first sloped conductive layer extends in a first direction, the second sloped conductive layer extends in a second direction, and the second direction is opposite to the first direction; and forming a top conductive layer covering the first sloped conductive layer and the second sloped conductive layer.

14. The method of claim 13, wherein forming the first sloped recess along the first insulating layer comprises: forming a first hardmask layer on the first insulating layer; forming a first hardmask opening along the first hardmask layer; performing a first sloped etch process on the first insulating layer to form the first sloped recess along the first insulating layer; and wherein the first sloped etch process uses the first hardmask layer as a pattern guide.

15. The method of claim 14, wherein an incident angle of the first sloped etch process is in a range of about 5 degrees to about 80 degrees.

16. The method of claim 15, wherein the first hardmask layer is made of a material that is etch selective to the first insulating layer.

17. The method of claim 15, wherein the first hardmask layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, boron nitride, boron silicon nitride, phosphorous boron nitride, silicon boron carbon nitride, or carbon film.

18. The method of claim 15, wherein an etch rate ratio of the first hardmask layer to the first insulating layer of the first sloped etch process is in a range of about 1:10 to about 1:

100. ​ ​

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