Semiconductor structure

Abstract

A semiconductor structure includes a interposer substrate including an upper surface and a lower surface opposite the upper surface. A guard ring is formed in the interposer substrate and surrounds a device region of the interposer substrate. At least one through-silicon via is formed in the interposer substrate, wherein an end of the guard ring adjacent the upper surface and an end of the through-silicon via adjacent the upper surface are coplanar with each other.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor structure, and in particular, to a semiconductor structure including an interposer substrate with electronic elements and a guard ring. BACKGROUND

[0002] In advanced semiconductor technology, heterogeneous integration technology uses an interposer to carry and electrically connect different chips, which can achieve higher speed, higher bandwidth and lower power consumption. With the increasing complexity of chips and the requirement of smaller package size, how to further improve the integration density and reduce the signal interference between electronic elements in the package is an important issue in the field. SUMMARY

[0003] The purpose of the present invention is to provide an improved semiconductor structure that can improve integration density and reduce electronic signal interference.

[0004] According to an embodiment of the present invention, a semiconductor structure includes an interposer substrate including an upper surface and a lower surface opposite to the upper surface. A guard ring is formed in the interposer substrate and surrounds an element region of the interposer substrate. At least one through silicon via is formed in the interposer substrate, wherein an end of the guard ring adjacent to the upper surface and an end of the through silicon via adjacent to the upper surface are flush with each other. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 FIG. 1 is a cross-sectional view of a partial region of a semiconductor structure according to an embodiment of the present invention;

[0006] Figure 2 FIG. 2 is a top view of a partial region of an interposer substrate of a semiconductor structure according to an embodiment of the present invention;

[0007] Figures 3 to 6 FIG. 3 is a cross-sectional view of a step of a manufacturing method of a semiconductor structure according to an embodiment of the present invention;

[0008] Figures 7 to 9 FIG. 4 is a cross-sectional view of a step of a manufacturing method of a semiconductor structure according to an embodiment of the present invention;

[0009] Figure 10 FIG. 5 is a cross-sectional view of a partial region of a semiconductor structure according to an embodiment of the present invention;

[0010] Figure 11 FIG. 6 is a top view of a partial region of an interposer substrate of a semiconductor structure according to an embodiment of the present invention.

[0011] MAIN ELEMENT SYMBOL EXPLANATION

[0012] 100 interposer substrate

[0013] 102 upper surface

[0014] 104 lower surface

[0015] 110 element region

[0016] 112 electronic element

[0017] 120 through silicon via

[0018] 130 guard ring

[0019] 132 auxiliary guard ring

[0020] 134 auxiliary guard ring

[0021] 136 auxiliary guard ring

[0022] 140 first redistribution layer

[0023] 141 dielectric layer

[0024] 142 conductive layer

[0025] 143 first shielding layer

[0026] 150 second redistribution layer

[0027] 151 dielectric layer

[0028] 152 conductive layer

[0029] 153 second shielding layer

[0030] 160 bump

[0031] 300 chip

[0032] 302 micro bump

[0033] 100a front side

[0034] 100b back side

[0035] 112' trench

[0036] 120' hole

[0037] 130' trench

[0038] 120a end

[0039] 120b end

[0040] 130a end

[0041] 130b end

[0042] X direction

[0043] Y direction

[0044] Z direction DETAILED DESCRIPTION

[0045] The following detailed description and recited description, with reference to the accompanying drawings, are used to explain embodiments that can be implemented according to the present application. These embodiments have been provided with sufficient details to allow those skilled in the art to fully understand and implement the present application. Modifications in structure, logic, and electrical properties can be made without departing from the scope of the present application, and can be applied to other embodiments.

[0046] For the convenience of explanation and for the skilled in the art to more easily understand the present application, the drawings of the present application are only schematic, and the detailed proportions can be adjusted according to the design requirements. In the description, the relative positions of the devices in the drawings are described, and those skilled in the art should understand that the relative positions of the objects can be reversed to present the same components, and therefore, should all belong to the scope disclosed in the present specification, which is described herein.

[0047] In the present specification, "wafer", "substrate" or "substrate" means any structure containing an exposed surface on which material can be deposited according to the embodiments shown in the present application to form an integrated circuit structure, such as a wiring layer. It should be understood that "substrate" includes semiconductor wafers, but is not limited thereto. "Substrate" also means a semiconductor structure containing material layers formed thereon during the manufacturing process.

[0048] It should be readily understood that the terms used in the present specification, such as "on", "above", "over", "below", "under", "underneath", and the like, should be interpreted in the broadest manner, so that these terms mean not only "directly on" or "directly under", but also "indirectly on" or "indirectly under" with intermediate features or layers.

[0049] In addition, the above spatially relative terms are used for the purpose of describing the relationship of one element or feature to another (or multiple) element(s) or feature(s) as shown in the drawings. In addition to the orientation shown in the drawings, the spatially relative terms are intended to encompass different orientations of the elements in use or operation. The elements can be oriented in other ways (e.g., rotated 90 degrees or at other orientations) and are likewise described herein with spatially relative terms.

[0050] Figure 1 A schematic cross-sectional view of a partial region of a semiconductor structure according to an embodiment of the present application. As shown in FIG. 1, the semiconductor structure 100 includes a substrate 110, a first dielectric layer 120, a first conductive layer 130, a second dielectric layer 140, and a second conductive layer 150. Figure 1As shown, the semiconductor structure includes an interposer substrate 100 having a front side 100a with an upper surface 102 and a back side 100b with a lower surface 104. The upper surface 102 and the lower surface 104 are oppositely disposed and each extends substantially along the X direction and the Y direction. The interposer substrate 100 can include a silicon substrate or other suitable semiconductor substrate, but is not limited thereto. The interposer substrate 100 defines at least one device region 110 in which at least one electronic device 112 can be formed by a semiconductor fabrication process. The electronic device 112 can include a passive device, such as at least one of a capacitor, a resistor, or an inductor, but is not limited thereto. In some embodiments, the electronic device 112 does not include an active device, such as a transistor. At least one guard ring 130 is formed in the interposer substrate 110 and surrounds the device region 110.

[0051] The semiconductor structure further includes at least one through silicon via (TSV) 120 (or through substrate via) formed in the interposer substrate 100. In some embodiments, an end 130a of the guard ring 130 and an end 120a of the through silicon via 120 can be coplanar with each other and exposed from the upper surface 102 of the interposer substrate 100. In some embodiments, an end 130b of the guard ring 130 and an end 120b of the through silicon via 120 can be coplanar with each other and exposed from the lower surface 104 of the interposer substrate 100.

[0052] In some embodiments, the semiconductor structure can include a first redistribution layer 140 formed on the upper surface 102 of the interposer substrate 100 and a second redistribution layer 150 formed on the lower surface 104 of the interposer substrate 100. The first redistribution layer 140 and the second redistribution layer 150 each include at least one dielectric layer (e.g., dielectric layers 141, 151) and at least one conductive layer (e.g., conductive layers 142, 152). The conductive layers can include conductive lines for horizontal (e.g., in the XY plane) electrical connections and conductive vias for vertical (e.g., Z direction) electrical connections. The conductive layers can also include bump pads for bumping. The dielectric layers of the first redistribution layer 140 and the second redistribution layer 150 can include inorganic dielectric materials such as silicon oxide, silicon nitride, or organic dielectric materials such as polyimide (PI), but are not limited thereto. The conductive layers can include metals such as aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or the like, but are not limited thereto. The first redistribution layer 140 can include conductive lines (not shown) electrically connected to the electronic device 112.

[0053] One end portion 120a of the through silicon via 120 can be electrically connected with the conductive layer 142 of the first redistribution layer 140, and the other end portion 120b can be electrically connected with the conductive layer 152 of the second redistribution layer 150, so as to realize the electrical connection between the first redistribution layer 140 and the second redistribution layer 150.

[0054] In some embodiments, the end portion 120a of the guard ring 130 can be electrically connected with the second redistribution layer 150. The guard ring 130 can be electrically connected to a ground voltage (or a reference voltage) through the second redistribution layer 150, so as to provide electronic shielding for the electronic elements 112 in the element region 110 and reduce signal interference.

[0055] In some embodiments, the semiconductor structure can include at least one chip (or die) 300 arranged on the front side 100a of the interposer substrate 100 in a manner facing the upper surface 102 of the interposer substrate 100. That is, the chip 300 is arranged above the interposer substrate 100 along the Z direction, wherein the Z direction is a direction perpendicular to the plane defined by the X direction and the Y direction. The chip 300 can be electrically connected with the conductive layer 142 of the first redistribution layer 140 through the micro bump 302. The chip 300 can be an active integrated circuit chip with specific functions, such as a graphics processing unit (GPU), a central processing unit (CPU), a memory chip, etc., but is not limited thereto.

[0056] In some embodiments, the semiconductor structure can include a circuit board (or package substrate) 200 arranged on the back side 100b of the interposer substrate 100 in a manner facing the lower surface 104 of the interposer substrate 100, and electrically connected with the conductive layer 152 of the second redistribution layer 150 through the bump 160.

[0057] It should be noted that, Figure 1 The arrangement of the chip 300, the interposer substrate 100, and the circuit board 200 of the semiconductor structure shown is only an example, and in other embodiments, the die (or chip) can be arranged on the back side 100b of the interposer substrate 100 in a manner facing the lower surface 104 of the interposer substrate 100, or the circuit board can be arranged on the front side 100a of the interposer substrate 100 in a manner facing the upper surface 102 of the interposer substrate 100.

[0058] Figure 2This is a top view of a portion of an interposer substrate 100 of a semiconductor structure according to an embodiment of the present invention. Facing the upper surface 102, the interposer substrate 100 may include multiple component regions 110, each continuously surrounded by a closed annular guard ring 130. The shape of the guard ring 130 can be adjusted according to the shape of the component region 110; for example, when the component region 110 is a rectangular area, the guard ring 130 may be approximately rectangular. In other embodiments, the guard ring 130 may be designed as a circular ring, an elliptical ring, a polygonal ring, etc., depending on application requirements, but is not limited thereto.

[0059] Figures 3 to 6 This is a cross-sectional schematic diagram of the steps of a method for fabricating a semiconductor structure according to an embodiment of the present invention. In this embodiment, the through-silicon via 120 and the guard ring 130 can be formed simultaneously by the same fabrication process and include the same material and the same height.

[0060] Please refer to Figure 3 First, an interposer substrate 100 is provided, having a front side 100a with an upper surface 102 and a back side 100b with a lower surface 104. The interposer substrate 100 defines at least one element region 110.

[0061] Please refer to Figure 4 Then, at least one electronic component 112 is formed in the component region 110 from the front side 100a of the interposer substrate 100. The electronic component 112 may include passive components, such as capacitors, resistors, or inductors, but is not limited thereto. The electronic component 112 can be fabricated using existing semiconductor fabrication processes, such as photolithography, etching, thin film deposition, chemical mechanical polishing, but is not limited thereto. For the sake of simplicity, these will not be elaborated further here.

[0062] Please refer to Figure 5A pad layer (not shown) can then be selectively formed on the upper surface 102 to protect the electronic component 112 or as a stop layer for subsequent grinding fabrication processes, and then a guard ring 130 and a through-silicon via 120 are formed in the interposer substrate 100 from the front side 100a of the interposer substrate 100. For example, a hole 120' for the through-silicon via 120 and a trench 130' for the guard ring 130 can be formed in the interposer substrate 100 to a predetermined depth from the upper surface 102 by a photolithography and etching fabrication process, laser drilling or other suitable methods, and then a conductive material (e.g. aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride or other metals or similar materials) is formed to fill the hole 120' and the trench 130', and then a grinding fabrication process is performed from the front side 100a of the interposer substrate 100 to remove the excess conductive material outside the hole 120' and the trench 130'. In this embodiment, the end 120a of the through-silicon via 120 adjacent to the upper surface 102 and the end 130a of the guard ring 130 adjacent to the upper surface 102 can be substantially at the same level and flush with each other. If a pad layer (not shown) is provided on the upper surface 102, the end 120a of the through-silicon via 120 and the end 130a of the guard ring 130 can pass through and expose from the pad layer.

[0063] Please continue to refer to Figure 5 After the guard ring 130 and the through-silicon via 120 are formed, a first redistribution layer 140 is then formed on the upper surface 102 of the interposer substrate 100. The first redistribution layer 140 includes at least one dielectric layer 141 and at least one conductive layer 142 formed in the dielectric layer 141. The end 120a of the through-silicon via 120 is electrically connected to the conductive layer 142. If a pad layer (not shown) is provided between the upper surface 102 and the first redistribution layer 140, the pad layer can include a conductive hole to electrically connect the electronic component 112 to the first redistribution layer 140.

[0064] Please refer to Figure 6 A grinding fabrication process is then performed on the lower surface 104 from the back side 100b of the interposer substrate 100 to thin the interposer substrate 100 to expose the end 120b of the through-silicon via 120 adjacent to the lower surface 104 and the end 130b of the guard ring 130 adjacent to the lower surface 102, and then a second redistribution layer 150 is formed on the lower surface 104. The second redistribution layer 150 includes at least one dielectric layer 151 and at least one conductive layer 152 formed in the dielectric layer 151. In this embodiment, the end 120b of the through-silicon via 120 and the end 130b of the guard ring 130 can be substantially at the same level and flush with each other, and are respectively electrically connected to the conductive layer 152. Subsequently, a plurality of bumps 160 can be formed on the second redistribution layer 150 for bonding the interposer substrate 100 to a circuit board (or a package substrate).

[0065] Figures 7 to 9This is a cross-sectional schematic diagram of the steps of a method for fabricating a semiconductor structure according to another embodiment of the present invention. In this embodiment, the guard ring 130 can be formed simultaneously with the electronic component 112 using the same fabrication process, including the same material and extending to the same depth as the interposer substrate 100.

[0066] Please refer to Figure 7 First, an interposer substrate 100 is provided, having a front side 100a with an upper surface 102 and a back side 100b with a lower surface 104, and defining at least one component region 110. Next, an electronic component 112 and a guard ring 130 surrounding the component region 110 are formed from the front side 100a of the interposer substrate 100 within the component region 110. In this embodiment, the electronic component 112 may include a deep trench capacitor (DTC). The steps for forming the electronic component 112 and the guard ring 130 include, for example, forming trenches 112' of the electronic component 112 and trenches 130' of the guard ring 130 at a predetermined depth from the upper surface 102 in the interposer substrate 100 using photolithography and etching processes, laser drilling, or other suitable methods; then depositing a conductive-dielectric-conductive material stack to fill the trenches 112' and 130'; and then removing excess conductive-dielectric-conductive material stacks using a patterning process (e.g., photolithography and etching processes). The conductive material of the electronic component 112 and the guard ring 130 may include polysilicon, or may include metals such as aluminum, copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride, or the like, but is not limited thereto. The dielectric material of the electronic component 112 and the guard ring 130 may include silicon oxide, silicon nitride, or a high-k dielectric constant material, but is not limited thereto. In this embodiment, the end 112a of the electronic component 112 adjacent to the upper surface 102 and the end 130a of the guard ring 130 adjacent to the upper surface 102 can be located at approximately the same horizontal level and are flush with each other.

[0067] Please refer to Figure 8 After forming the electronic component 112 and the guard ring 130, a pad layer (not shown) may be selectively formed on the upper surface 102 to protect the electronic component 112 and the guard ring 130 or as a stop layer for subsequent polishing processes. Then, a through-silicon via 120 is formed in the interposer substrate 100 from the front side 100a. The steps for forming the through-silicon via 120 are as described above and will not be repeated here. Subsequently, a first redistribution layer 140 is formed on the upper surface 102 of the interposer substrate 100. If a pad layer (not shown) is provided between the upper surface 102 and the first redistribution layer 140, the pad layer may include conductive vias to electrically connect the electronic component 112 and the guard ring 130 to the first redistribution layer 140.

[0068] Please refer to Figure 9, a grinding fabrication process is performed on the bottom surface 104 from the back side 100b of the interposer substrate 100 to thin the interposer substrate 100 to expose the end portion 120b of the through silicon via 120 adjacent to the bottom surface 104, and then a second redistribution layer 150 is formed on the bottom surface 104 and the end portion 120b of the through silicon via 102 is electrically connected to the conductive layer 152 of the second redistribution layer 150. Subsequently, a plurality of bumps 160 can be formed on the second redistribution layer 150 for bonding the interposer substrate 100 to a circuit board (or a package substrate). In some embodiments, as shown in Figure 9 the end portion 130a of the guard ring 130 can be electrically connected to the end portion 120a of a through silicon via 120 through the conductive layer 142 of the first redistribution layer 140, and then electrically connected to a ground voltage or a reference voltage through the through silicon via 120 and the second redistribution layer 150.

[0069] Figure 10 is a cross-sectional view of a partial region of a semiconductor structure according to an embodiment of the present application. To further improve the electronic shielding effect on the electronic element 112, the semiconductor structure of the present application can further include a first shielding layer 143 and a second shielding layer 153 disposed in the first redistribution layer 140 and the second redistribution layer 150, respectively, and corresponding to the electronic element 112. The first shielding layer 143 can be formed in the dielectric layer 141 through the same fabrication process as the conductive layer 142, including the same material as the conductive layer 142. The second shielding layer 153 can be formed in the dielectric layer 151 through the same fabrication process as the conductive layer 152, including the same material as the conductive layer 152. In some embodiments, the first shielding layer 143 and the second shielding layer 153 can be electrically connected to the end portion 130a and the end portion 130b of the guard ring 130, respectively, and both electrically connected to a ground voltage or a reference voltage to provide electronic shielding in both horizontal and vertical directions of the electronic element 112. In some embodiments, the first shielding layer 143 and / or the second shielding layer 153 can also be electrically floating. It should be understood that in other embodiments, a shielding layer can be disposed in only one of the first redistribution layer 140 or the second redistribution layer 150.

[0070] Figure 11 is a top view of a partial region of the interposer substrate 100 of a semiconductor structure according to an embodiment of the present application. To further improve the electronic shielding effect on the electronic element 112, the semiconductor structure of the present application can further include at least one or more auxiliary guard rings disposed in the interposer substrate 100 and surrounding the guard ring 130. As shown in Figure 11As shown, the interposer substrate 100 can be provided with an auxiliary guard ring 132, an auxiliary guard ring 134, and an auxiliary guard ring 136, which together with the guard ring 130 form a multi-layer concentric ring structure around the component region 110. In some embodiments, the auxiliary guard ring 132, the auxiliary guard ring 134, and the auxiliary guard ring 136 can be discontinuous rings, respectively.

[0071] The auxiliary guard ring 132, the auxiliary guard ring 134, and the auxiliary guard ring 136 can be formed simultaneously with the guard ring 130 by the same manufacturing process and comprise the same material as the guard ring 130. The auxiliary guard ring 132, the auxiliary guard ring 134, and the auxiliary guard ring 136 can be electrically connected to the first redistribution layer 140 and / or the second redistribution layer 150, respectively, and connected to a ground voltage or a reference voltage. In some cases, the guard ring 130, the auxiliary guard ring 132, the auxiliary guard ring 134, and the auxiliary guard ring 136 can also be connected to different voltages or electrically floating. In addition, the present application can achieve the effect of buffering the stress around the component region 110 by adjusting the shape and configuration of the auxiliary guard ring.

[0072] In summary, the present application plans a component region in the interposer substrate for setting electronic components such as capacitors, resistors, or inductors, which can improve the integrated density of the semiconductor structure. The guard ring formed around the component region in the interposer substrate can provide electronic shielding for the electronic components and reduce signal interference between the electronic components.

[0073] The above description is only the preferred embodiments of the present application, and any equivalent changes and modifications made according to the claims of the present application shall be within the scope of the present application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: an interposer substrate including an upper surface and a lower surface opposite to the upper surface; a guard ring formed in the interposer substrate and surrounding a device region of the interposer substrate; at least one through-silicon via formed in the interposer substrate, wherein an end of the guard ring adjacent to the upper surface and an end of the through-silicon via adjacent to the upper surface are flush with each other; and an electronic device formed in the device region of the interposer substrate, wherein the guard ring and the electronic device are simultaneously formed by a same fabrication process.

2. The semiconductor structure of claim 1, wherein the electronic device comprises at least one of a capacitor, a resistor, or an inductor.

3. The semiconductor structure of claim 1, wherein the electronic device comprises a deep trench capacitor, and the guard ring and the deep trench capacitor are composed of a same material.

4. The semiconductor structure of claim 1, wherein the guard ring and the through-silicon via are composed of a same material.

5. The semiconductor structure of claim 4, wherein another end of the guard ring and another end of the through-silicon via are flush with each other.

6. The semiconductor structure of claim 1, further comprising a first redistribution layer disposed on the upper surface of the interposer substrate, wherein the electronic device, the through-silicon via, and the guard ring are respectively electrically connected to the first redistribution layer.

7. The semiconductor structure of claim 6, further comprising a first shielding layer disposed in the first redistribution layer and electrically connected to the guard ring.

8. The semiconductor structure of claim 1, further comprising a second redistribution layer disposed on the lower surface of the interposer substrate, wherein the through-silicon via and the guard ring are respectively electrically connected to the second redistribution layer.

9. The semiconductor structure of claim 8, further comprising a second shielding layer disposed in the second redistribution layer and electrically connected to the guard ring.

10. The semiconductor structure of claim 8, further comprising a plurality of bumps disposed on the second redistribution layer.

11. The semiconductor structure of claim 1, wherein the guard ring is electrically connected to a ground voltage.

12. The semiconductor structure of claim 1, wherein the guard ring is a closed ring.

13. The semiconductor structure of claim 1, further comprising at least one auxiliary guard ring surrounding the guard ring, and the guard ring and the at least one auxiliary guard ring form a multi-layer concentric ring structure surrounding the device region.

14. The semiconductor structure of claim 13, wherein the at least one auxiliary guard ring is a discontinuous ring.

Images