Semiconductor device and control method thereof

Abstract

Embodiments relate to semiconductor devices and control methods thereof. The semiconductor device comprises a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type disposed on the first semiconductor layer, a third semiconductor layer of the first conductivity type selectively disposed on the second semiconductor layer, a fourth semiconductor layer of the second conductivity type selectively disposed on the second semiconductor layer and arranged side by side with the third semiconductor layer, and a fifth semiconductor layer of the second conductivity type. The first semiconductor layer is located between the second semiconductor layer and the fifth semiconductor layer. The fourth semiconductor layer is in a plane parallel to the upper surface of the second semiconductor layer, and the area of ​​the fourth semiconductor layer has an area larger than that of the third semiconductor layer. The semiconductor device further comprises: a control electrode disposed inside a trench from the upper surface of the third semiconductor layer to a depth in the first semiconductor layer; a first electrode electrically connected to the third semiconductor layer; and a second electrode electrically connected to the fourth semiconductor layer.

Description

[0001] This application includes all the contents of the basic application by reference to the basic application. This application enjoys priority from Japanese Patent Application No. 2020-157529 (filing date: September 18, 2020) as a basic application. This application includes all the contents of the basic application by reference to the basic application. Technical Field

[0002] Embodiments relate to a semiconductor device and a control method thereof. Background Art

[0003] Semiconductor devices constituting power converters such as inverters are required to have improved breakdown resistance against short-circuit currents and the like. Summary of the invention

[0004] The embodiment provides a semiconductor device having improved breakdown resistance and a control method thereof.

[0005] A semiconductor device according to an embodiment includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type, arranged on the first semiconductor layer; a third semiconductor layer of the first conductivity type, selectively arranged on the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, selectively arranged on the second semiconductor layer and arranged in parallel with the third semiconductor layer; and a fifth semiconductor layer of the second conductivity type. The first semiconductor layer is located between the second semiconductor layer and the fifth semiconductor layer. The fourth semiconductor layer has an area larger than that of the third semiconductor layer in a plane parallel to the upper surface of the second semiconductor layer. The semiconductor device further includes: a control electrode, arranged inside a channel, the depth of the channel being from the upper surface of the third semiconductor layer to the first semiconductor layer; a first electrode, electrically connected to the third semiconductor layer; a second electrode, electrically connected to the fourth semiconductor layer; a third electrode, electrically connected to the fifth semiconductor layer; and a control terminal, electrically connected to the control electrode. The control electrode is electrically insulated from the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer by a first insulating film. The second semiconductor layer faces the control electrode via the first insulating film, and the third semiconductor layer is in contact with the first insulating film.

[0006] In the control method of the semiconductor device according to the embodiment, the potential connected to the fourth semiconductor layer via the second electrode is lower than the potential connected to the third semiconductor layer via the first electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment.

[0008] Figure 2 (a) to (d) are schematic plan views showing semiconductor devices according to the embodiments.

[0009] Figure 3 is a graph showing characteristics of the semiconductor device according to the embodiment.

[0010] Figure 4 It is a timing chart showing the control method of the semiconductor device according to the embodiment.

[0011] Figure 5 It is a timing chart showing a method of controlling a semiconductor device according to a modification of the embodiment.

[0012] Figure 6 (a) and (b) are schematic diagrams showing a power converter according to a comparative example. DETAILED DESCRIPTION

[0013] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The same parts in the drawings are given the same numbers and their detailed descriptions are appropriately omitted, and different parts are described. Among them, the accompanying drawings are schematic diagrams or conceptual diagrams, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as the actual ones. In addition, even when representing the same parts, there are cases where the mutual sizes and ratios are represented differently according to the drawings.

[0014] Furthermore, the configuration and structure of each part are described using the X-axis, Y-axis, and Z-axis shown in each figure. The X-axis, Y-axis, and Z-axis are orthogonal to each other and represent the X direction, Y direction, and Z direction, respectively. In addition, there is a case where the Z direction is regarded as the upper direction and the opposite direction is regarded as the lower direction for description.

[0015] Figure 1 1 is a schematic cross-sectional view showing a semiconductor device 1 according to an embodiment. The semiconductor device 1 is, for example, an IGBT (Insulated Gate Bipolar Transistor).

[0016] like Figure 1 As shown, the semiconductor device 1 includes a first semiconductor layer 11 of a first conductivity type, a second semiconductor layer 13 of a second conductivity type, a third semiconductor layer 15 of a first conductivity type, a fourth semiconductor layer 17 of a second conductivity type, a fifth semiconductor layer 19 of a second conductivity type, a first control electrode 20, and a second control electrode 30. In the following description, the first conductivity type is set to an n-type and the second conductivity type is set to a p-type.

[0017] The first to fifth semiconductor layers are, for example, silicon. The first semiconductor layer 11 is, for example, an n-type base layer. The second semiconductor layer 13 is, for example, a p-type base layer. The second semiconductor layer 13 is provided on the first semiconductor layer 11 .

[0018] The third semiconductor layer 15 is, for example, an n-type emitter layer and is selectively provided on the second semiconductor layer 13. The third semiconductor layer 15 contains, for example, first conductivity type impurities at a higher concentration than the first conductivity type impurities in the first semiconductor layer 11.

[0019] The fourth semiconductor layer 17 is, for example, a p-type emitter layer. The fourth semiconductor layer 17 is selectively disposed on the second semiconductor layer 13. The fourth semiconductor layer 17, for example, contains second conductivity type impurities having a higher concentration than the second conductivity type impurities of the second semiconductor layer 13. The third semiconductor layer 15 and the fourth semiconductor layer 17 are arranged side by side on the second semiconductor layer 13.

[0020] The fifth semiconductor layer 19 is, for example, a p-type collector layer. The first semiconductor layer 11 is provided between the second semiconductor layer 13 and the fifth semiconductor layer 19 .

[0021] The first control electrode 20 is, for example, a gate electrode. The first control electrode 20 is, for example, conductive polysilicon, and is disposed inside the trench GT1. The trench GT1 extends, for example, in the Z direction, and has a depth from the upper surface of the third semiconductor layer 15 to the first semiconductor layer 11. In addition, the trench GT1 also extends, for example, in the Y direction. The first control electrode 20 extends inside the trench GT1, for example, in the X direction and the Y direction, and is electrically insulated from the first semiconductor layer 11, the second semiconductor layer 13, and the third semiconductor layer 15 by the first insulating film 23. The first insulating film 23 is, for example, a gate insulating film. The first insulating film 23 is, for example, a silicon oxide film.

[0022] The first control electrode 20 has a portion extending into the first semiconductor layer 11. The first semiconductor layer 11 faces the first control electrode 20 via the first insulating film 23. The second semiconductor layer 13 faces the first control electrode 20 via the first insulating film 23. The third semiconductor layer 15 is in contact with the first insulating film 23.

[0023] The second control electrode 30 is, for example, a field plate. The second control electrode 30 is, for example, conductive polysilicon, and is disposed inside the trench GT2. The trench GT2 extends, for example, in the Z direction, and has a depth from the upper surface of the fourth semiconductor layer 17 to the first semiconductor layer 11. In addition, the trench GT2 also extends, for example, in the Y direction. The second control electrode 30 extends inside the trench GT2, for example, in the X direction and the Y direction, and is electrically insulated from the first semiconductor layer 11, the second semiconductor layer 13, and the fourth semiconductor layer 17 by the second insulating film 33. The second insulating film 33 is, for example, a silicon oxide film.

[0024] The second control electrode 30 has a portion extending into the first semiconductor layer 11. The first semiconductor layer 11 faces the second control electrode 30 via the second insulating film 33. The second semiconductor layer 13 faces the second control electrode 30 via the second insulating film 33. The fourth semiconductor layer 17 is in contact with the second insulating film 33, for example.

[0025] The semiconductor device 1 further includes, for example, a first electrode ET1 , a second electrode ET2 , a third electrode CT, and a control terminal GTE.

[0026] The first electrode ET1 is electrically connected to the third semiconductor layer 15 , the second electrode ET2 is electrically connected to the fourth semiconductor layer 17 , and the third electrode CT is electrically connected to the fifth semiconductor layer 19 .

[0027] The control terminal GTE is electrically connected to the first control electrode 20. The control terminal GTE is electrically connected to the first control electrode 20 via, for example, a contact hole provided in an insulating film 25 covering the upper end of the first control electrode 20. The insulating film 25 is, for example, a silicon oxide film.

[0028] Furthermore, the first control electrode 20 has a contact portion (not shown) extending to the outside of the trench GT1 at an end in the Y direction, for example, and the control terminal GTE is electrically connected to the contact portion of the first control electrode 20 .

[0029] The second control electrode 30 is controlled independently of the first control electrode 20. The second control electrode 30 is controlled to have the same potential as the first electrode ET1, for example. The second control electrode 30 is electrically connected to the first electrode ET1, for example, via a contact hole (not shown) provided in an insulating film 35 covering the upper end thereof. The insulating film 35 is, for example, a silicon oxide film.

[0030] In addition, the second control electrode 30 may be controlled to have a potential different from that of the first electrode ET1 and the first control electrode 20 .

[0031] Figure 2 (a) to (d) are schematic plan views showing the semiconductor device 1 according to the embodiment. Figure 2(a) to (d) are schematic diagrams showing the arrangement of the third semiconductor layer 15 and the fourth semiconductor layer 17. CH1 and CH2 shown in each figure represent contact holes provided in an interlayer insulating film (not shown).

[0032] like Figure 2 As shown in (a) to (d), the third semiconductor layer 15 and the fourth semiconductor layer 17 are arranged side by side in the XY plane. In the XY plane, the area of ​​the fourth semiconductor layer 17 is set larger than the area of ​​the third semiconductor layer 15.

[0033] The first electrode ET1 is electrically connected to the third semiconductor layer 15 via the contact hole CH1. The second electrode ET2 is electrically connected to the fourth semiconductor layer 17 via the contact hole CH2.

[0034] Figure 3 : is a graph showing the characteristics of the semiconductor device 1 according to the embodiment. The horizontal axis shows the collector voltage Vce applied between the first electrode ET1 and the third electrode CT. The vertical axis shows the collector current Ic flowing between the first electrode ET1 and the third electrode CT.

[0035] In this example, the potential Ve1 of the first electrode ET1 is 0 V, the gate voltage Vg1 applied between the first control electrode 20 and the first electrode ET1 is 15 V, and the voltage applied between the second control electrode 30 and the first electrode ET1 is 0 V. In this case, the threshold voltage of the first control electrode 20 is lower than 15V.

[0036] Figure 3 The collector current Ic when the potential Ve2 of the second electrode ET2 is changed relative to the potential Ve1 of the first electrode ET1 is shown. For example, when the potential Ve2 of the second electrode ET2 is set to 0 V, Figure 3 The collector current Ic shown shows the characteristics of a general IGBT having an emitter electrode electrically connected to both the third semiconductor layer 15 and the fourth semiconductor layer 17 .

[0037] like Figure 3 As shown, the collector current Ic decreases as the potential Vc2 of the second electrode ET2 decreases by -0.5V, -2V, and -4V relative to the potential Vc1 (=0V) of the first electrode ET1. When the potential Vc2 of the second electrode ET2 is set to 0.5V, the collector current Ic increases.

[0038] Figure 4 It is a timing chart showing a control method of the semiconductor device 1 according to the embodiment. Figure 4 The graph shows time changes of the collector voltage Vce, the collector current Ic, the gate voltage Vg1 , the potential Ve1 of the first electrode ET1 , and the potential Ve2 of the second electrode ET2 .

[0039] Here, the collector voltage Vce is a voltage applied between the first electrode ET1 and the third electrode CT. The collector current Ic is a current flowing between the first electrode ET1 and the third electrode CT. In addition, the gate voltage Vg1 is a voltage applied between the first electrode ET1 and the first control electrode 20.

[0040] For example, at time t1, in a state where a predetermined collector voltage Vce is applied between the first electrode ET1 and the third electrode CT, the gate voltage Vg1 between the first electrode ET1 and the first control electrode 20 is changed from a negative voltage to +15 V higher than the threshold voltage. At this time, the potential Ve1 of the first electrode ET1 and the potential Ve2 of the second electrode ET2 are both 0V.

[0041] The potential of the first control electrode 20 induces an inversion layer of the first conductivity type at the interface between the first insulating film 23 and the second semiconductor layer 13 , and the collector current Ic increases to a predetermined on-current level.

[0042] Next, at time t2 later than time t1, for example, if a short circuit fault (see Figure 6 ) causes the collector voltage Vce to rise, and the potential Ve2 of the second electrode ET2 is reduced to a level lower than the potential Ve1 of the first electrode ET1, for example, to -4V. As a result, the collector current Ic is reduced (see Figure 3 ). For example, a short-circuit fault is detected when the collector voltage Vce exceeds a specified threshold.

[0043] Figure 6 (a) and (b) are schematic diagrams showing a power converter 2 according to a comparative example. Figure 6 (a) is a circuit diagram of the power converter 2. Figure 6 (b) is a timing chart illustrating the operation of the power converter 2 when a failure occurs.

[0044] like Figure 6 As shown in (a), the power converter 2 is, for example, a single-phase inverter. The power converter 2 includes semiconductor devices 1A to 1D. The semiconductor devices 1A to 1D are, for example, ordinary IGBTs in which an emitter electrode is electrically connected to both an n-type emitter layer and a p-type emitter layer.

[0045] Figure 6 (b) shows the time changes of the collector voltage Vce, the collector current Ic, and the gate voltage Vg of the semiconductor device 1B.

[0046] The power converter 2 is controlled, for example, so that the semiconductor device 1B and the semiconductor device 1C are turned on and the semiconductor device 1A and the semiconductor device 1D are turned off at time t1. The gate voltage Vg of the semiconductor device 1B rises from the off level to the on level, for example, to 15 V. Along with this, the collector current Ic rises to the on current level, and the collector voltage drops to the on voltage level.

[0047] For example, if a short-circuit failure occurs in the semiconductor device 1A at time t2, the collector voltage Vce rises to, for example, the level of the power supply voltage Vcc. Along with this, the collector current Ic also rises, and the device suddenly enters a state of so-called thermal runaway. As a result, the semiconductor device 1B is also destroyed, and there is a case where the power converter 2 is explosively destroyed.

[0048] On the other hand, if the semiconductor device 1 according to the embodiment is used as the semiconductor devices 1A to 1D, for example, when a short-circuit fault is detected in the semiconductor device 1A, the potential Ve2 of the second electrode ET2 is reduced to a level lower than the potential Ve1 of the first electrode ET1 in the semiconductor device 1B. This can suppress the increase of the collector current Ic and prevent thermal runaway.

[0049] In addition, in the above-mentioned embodiment, an example of reducing the potential Ve2 of the second electrode ET2 in the on-state of the semiconductor device 1 is illustrated, but it is not limited to this. For example, when the semiconductor device 1 is in the off-state, the rise of the collector voltage Vce may be detected to reduce the potential Ve2 of the second electrode ET2. In this way, the level of the collector current Ic when the semiconductor device 1 is in the on-state can be suppressed to avoid thermal runaway. In addition, the detection of the timing to reduce the potential Ve2 of the second electrode ET2 is not limited to the rise of the collector voltage Vce. For example, the change of other parameters in the power converter 2 may be detected to reduce the potential Ve2 of the second electrode ET2.

[0050] Figure 5 It is a timing chart showing a control method of the semiconductor device 1 according to a modification of the embodiment. Figure 5 The graph shows time changes of the collector voltage Vce, the collector current Ic, the gate voltage Vg1 , the potential Ve1 of the first electrode ET1 , and the potential Ve2 of the second electrode ET2 .

[0051] In this example, the potential Ve2 of the second electrode ET2 is always maintained at a level lower than the potential Ve1 of the first electrode ET1, for example, maintained at -4 V. Therefore, at time t1, even if the gate voltage Vg1 is increased from a negative voltage to 15 V higher than the threshold voltage, an inversion layer of the first conductivity type is induced at the interface between the second semiconductor layer 13 and the first insulating film 23, and the collector current Ic does not rise to the original on-current level. That is, by controlling the potential Ve2 of the second electrode ET2, the on-current can be stably suppressed.

[0052] According to such a control method, for example, when the original on-current level of the semiconductor device 1 is too high, it can be suppressed to a desired level. In addition, there is a case where the gate voltage Vg1 vibrates due to the increase of the on-current (see Figure 6 (b)). Such vibration is not limited to thermal runaway, but can also occur when the level of the on-current is too high during normal operation. Figure 5 The control method shown can also suppress the vibration of the gate voltage Vg1.

[0053] Several embodiments of the present invention have been described, but these embodiments are only illustrative and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the invention described in the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: have: a first semiconductor layer of a first conductivity type; A second semiconductor layer of a second conductivity type, disposed on the first semiconductor layer; The third semiconductor layer of the first conductivity type is selectively disposed on the second semiconductor layer; The fourth semiconductor layer of the second conductivity type is selectively disposed on the second semiconductor layer and arranged side by side with the third semiconductor layer, and in a plane parallel to the upper surface of the second semiconductor layer, the area of ​​the fourth semiconductor layer is larger than that of the third semiconductor layer; A fifth semiconductor layer of the second conductivity type, wherein the first semiconductor layer is located between the second semiconductor layer and the fifth semiconductor layer; a first control electrode, disposed inside the first channel, the first channel extending from the upper surface of the third semiconductor layer into the first semiconductor layer, the first control electrode being electrically insulated from the first semiconductor layer, the second semiconductor layer and the third semiconductor layer by a first insulating film, the second semiconductor layer being opposite to the first control electrode via the first insulating film, and the third semiconductor layer being in contact with the first insulating film; a first electrode, electrically connected to the third semiconductor layer; a second electrode, electrically connected to the fourth semiconductor layer; a third electrode, electrically connected to the fifth semiconductor layer; as well as A control terminal is electrically connected to the control electrode.

2. The semiconductor device according to claim 1, wherein: A second control electrode is provided inside a second channel, wherein the second channel extends from the upper surface of the fourth semiconductor layer into the first semiconductor layer, the second control electrode is electrically insulated from the first semiconductor layer, the second semiconductor layer and the fourth semiconductor layer by a second insulating film, the second semiconductor layer is opposite to the second control electrode via the second insulating film, and the fourth semiconductor layer is connected to the second insulating film.

3. The semiconductor device according to claim 2, wherein: The second control electrode is disposed at a position adjacent to the first control electrode.

4. The semiconductor device according to claim 1, wherein: The third semiconductor layer includes a first conductivity type impurity at a higher concentration than that of the first conductivity type impurity in the first semiconductor layer. The fourth semiconductor layer includes the second conductivity type impurity at a higher concentration than the second conductivity type impurity of the second semiconductor layer.

5. A control method for a semiconductor device, characterized in that: The semiconductor device comprises: a first semiconductor layer of a first conductivity type; A second semiconductor layer of a second conductivity type, disposed on the first semiconductor layer; The third semiconductor layer of the first conductivity type is selectively disposed on the second semiconductor layer; The fourth semiconductor layer of the second conductivity type is selectively disposed on the second semiconductor layer and arranged side by side with the third semiconductor layer; A fifth semiconductor layer of the second conductivity type, wherein the first semiconductor layer is located between the second semiconductor layer and the fifth semiconductor layer; a first control electrode, disposed inside the first channel, the first channel extending from the upper surface of the third semiconductor layer into the first semiconductor layer, the first control electrode being electrically insulated from the first semiconductor layer, the second semiconductor layer and the third semiconductor layer by a first insulating film, the second semiconductor layer being opposite to the first control electrode via the first insulating film, and the third semiconductor layer being in contact with the first insulating film; a first electrode, electrically connected to the third semiconductor layer; a second electrode, electrically connected to the fourth semiconductor layer; a third electrode, electrically connected to the fifth semiconductor layer; as well as a control terminal electrically connected to the control electrode, The control method makes a potential connected to the fourth semiconductor layer via the second electrode lower than a potential connected to the third semiconductor layer via the first electrode.

6. A method for controlling a semiconductor device, characterized in that: The semiconductor device comprises: a first semiconductor layer of a first conductivity type; A second semiconductor layer of a second conductivity type, disposed on the first semiconductor layer; The third semiconductor layer of the first conductivity type is selectively disposed on the second semiconductor layer; The fourth semiconductor layer of the second conductivity type is selectively disposed on the second semiconductor layer and arranged side by side with the third semiconductor layer; A fifth semiconductor layer of the second conductivity type, wherein the first semiconductor layer is located between the second semiconductor layer and the fifth semiconductor layer; a first control electrode, disposed inside the first channel, the first channel extending from the upper surface of the third semiconductor layer into the first semiconductor layer, the first control electrode being electrically insulated from the first semiconductor layer, the second semiconductor layer and the third semiconductor layer by a first insulating film, the second semiconductor layer being opposite to the first control electrode via the first insulating film, and the third semiconductor layer being in contact with the first insulating film; a first electrode, electrically connected to the third semiconductor layer; a second electrode, electrically connected to the fourth semiconductor layer; a third electrode, electrically connected to the fifth semiconductor layer; as well as a control terminal electrically connected to the control electrode, The control method makes the potential connected to the fourth semiconductor layer via the second electrode lower than the potential connected to the third semiconductor layer via the first electrode when the voltage between the first electrode and the third electrode exceeds a predetermined value.

7. The control method of a semiconductor device according to claim 6, characterized in that: While a voltage higher than a threshold voltage of the control electrode is applied between the control terminal and the first electrode, a potential connected to the fourth semiconductor layer is made lower than a potential connected to the third semiconductor layer via the first electrode.

8. The control method of a semiconductor device according to claim 6, characterized in that: Before the potential connected to the fourth semiconductor layer via the second electrode is made lower than the potential connected to the third semiconductor layer via the first electrode, the same potential as that of the third semiconductor layer is supplied to the fourth semiconductor layer via the second electrode.

9. The control method of a semiconductor device according to claim 6, characterized in that: The semiconductor device further includes a second control electrode adjacent to the first control electrode, the second control electrode being arranged inside a second channel, the second channel extending from the upper surface of the fourth semiconductor layer into the first semiconductor layer, the second control electrode being electrically insulated from the first semiconductor layer, the second semiconductor layer, and the fourth semiconductor layer by a second insulating film, and the second semiconductor layer being opposite to the second control electrode via the second insulating film. The control method performs control in such a manner that the potential of the second control electrode becomes the same as the potential of the first electrode.

10. The control method of a semiconductor device according to claim 6, characterized in that: The semiconductor device further includes a second control electrode adjacent to the first control electrode, the second control electrode being arranged inside a second channel, the second channel extending from the upper surface of the fourth semiconductor layer into the first semiconductor layer, the second control electrode being electrically insulated from the first semiconductor layer, the second semiconductor layer, and the fourth semiconductor layer by a second insulating film, and the second semiconductor layer being opposite to the second control electrode via the second insulating film. The control method performs control so that the potential of the second control electrode is different from the potential of the first electrode and the potential of the first control electrode.

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