A method of manufacturing a trench
By using the method of step-by-step deposition and etching of the dielectric layer, the difficulty in preparing high aspect ratio trench structures was solved, high-precision and high-yield trench preparation was achieved, the process flow was simplified, and the risk of defects was reduced.
Patent Information
- Application Number
- CN202111326597.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-11-10
- Publication Date
- 2025-10-24
- Estimated Expiration
- 2041-11-10
AI Technical Summary
The existing technology has high process difficulty, low processing precision and poor product yield when preparing high aspect ratio trench structures. It is difficult to control the shape and size of the bottom of the trench, which easily leads to defects.
A method of step-by-step deposition and step-by-step etching of dielectric layers is adopted. First, a first dielectric layer is formed on a semiconductor substrate and a first trench is etched. Then a sacrificial layer is filled. Then a second dielectric layer is formed and a second trench is etched. Finally, the sacrificial layer is removed to form a through trench with a high aspect ratio.
The preparation of high aspect ratio grooves is achieved with simple process and low operation difficulty, which improves processing accuracy, reduces the risk of product defects and improves product yield.
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Figure CN114220766B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of semiconductor manufacturing, and relates to a trench preparation method. BACKGROUND
[0002] Etching is a very important step in semiconductor manufacturing process, and is a main process of pattern processing associated with photolithography. Etching, in a narrow sense, is actually photolithography etching. First, a photoresist is exposed to light through photolithography, and then the part to be removed is removed through etching.
[0003] With the improvement of device performance requirements, reducing chip area is the common goal in the current chip research and development field. In order to improve the performance indicators of the chip, a trench needs to be prepared on the substrate. However, with the continuous reduction of chip area, the size of the trench prepared accordingly is also reduced. In the process of semiconductor chip production and preparation, the situation of etching high aspect ratio trench structure is encountered. When etching high aspect ratio trench structure, the processing capacity of the machine is greatly challenged, and the processing precision is difficult to control well. The shape and size of the position near the bottom of the trench deviate from the pattern defined by the mask, such as defects or open circuits, so that the existing trench preparation process is difficult to improve the product yield, and the risk of product defects is high.
[0004] Therefore, it is necessary to provide a trench preparation method. SUMMARY
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a trench preparation method for solving the problems of large process difficulty, poor processing precision and poor product yield in the preparation of high aspect ratio trench structure in the prior art.
[0006] To achieve the above-mentioned purpose and other related purposes, the present application provides a trench preparation method, comprising the following steps:
[0007] providing a semiconductor substrate;
[0008] forming a first dielectric layer on the semiconductor substrate;
[0009] forming a patterned first photoresist layer on the first dielectric layer;
[0010] etching the first dielectric layer to form a first trench penetrating through the first dielectric layer, the first trench having a first width;
[0011] removing the first photoresist layer to expose the surface of the first dielectric layer;
[0012] forming a sacrificial layer covering the surface of the first dielectric layer and filling the first trench;
[0013] removing part of the sacrificial layer to expose the surface of the first dielectric layer;
[0014] forming a second dielectric layer covering the surface of the first dielectric layer and the surface of the sacrificial layer;
[0015] forming a patterned second photoresist layer on the second dielectric layer;
[0016] etching the second dielectric layer to form a second trench penetrating the second dielectric layer, the second trench having a second width, and the second trench exposing the sacrificial layer;
[0017] removing the second photoresist layer and the sacrificial layer to form a trench exposing the semiconductor substrate.
[0018] Optionally, the second width of the second trench is greater than the first width of the first trench.
[0019] Optionally, the first trench and the second trench are both axisymmetric patterns, and the symmetry axes of the first trench and the second trench are the same perpendicular line.
[0020] Optionally, between removing the second photoresist layer and removing the sacrificial layer, further comprising repeating the steps of forming a sacrificial layer and a dielectric layer for M times, where M is a positive integer greater than or equal to 1.
[0021] Optionally, the first dielectric layer and the second dielectric layer are layers of the same material.
[0022] Optionally, the aspect ratio of the first trench ranges from 1:1 to 100:1, and the aspect ratio of the second trench ranges from 1:1 to 100:1.
[0023] Optionally, the first trench comprises a deep hole trench or a deep trench, and the second trench comprises a deep hole trench or a deep trench.
[0024] Optionally, the cross-sectional shape of the first trench comprises one of a rectangle, an inverted trapezoid, a "V" shape, and a "U" shape, and the cross-sectional shape of the second trench comprises one of a rectangle, an inverted trapezoid, a "V" shape, and a "U" shape.
[0025] Optionally, the first dielectric layer comprises one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer, and the second dielectric layer comprises one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.
[0026] Optionally, the sacrificial layer comprises a BARC layer.
[0027] As described above, the trench preparation method of the present application, first forms a first dielectric layer on a semiconductor substrate, and etches the first dielectric layer to form a first trench, then forms a sacrificial layer to fill the first trench, and then forms a second dielectric layer, and etches the second dielectric layer to form a second trench exposing the sacrificial layer, and then removes the sacrificial layer to form a trench through the first trench and the second trench. Thus, by the method of depositing and etching the dielectric layer in steps, the present application can prepare a trench with high aspect ratio, and the preparation process is simple, the operation difficulty is low, and the process precision is high, and it can also effectively reduce the risk of product defects and improve product yield. BRIEF DESCRIPTION OF DRAWINGS
[0028] Figure 1 A process flow chart for preparing a trench in an embodiment of the present application is shown.
[0029] Figure 2 A structure schematic diagram after forming a patterned first photoresist layer in an embodiment of the present application is shown.
[0030] Figure 3 A structure schematic diagram after forming a first trench in an embodiment of the present application is shown.
[0031] Figure 4 A structure schematic diagram after forming a sacrificial layer in an embodiment of the present application is shown.
[0032] Figure 5 A structure schematic diagram after removing part of the sacrificial layer in an embodiment of the present application is shown.
[0033] Figure 6 A structure schematic diagram after forming a patterned second photoresist layer in an embodiment of the present application is shown.
[0034] Figure 7 A structure schematic diagram after forming a second trench in an embodiment of the present application is shown.
[0035] Figure 8 A structure schematic diagram after removing the second photoresist layer and the sacrificial layer in an embodiment of the present application is shown.
[0036] ELEMENT NUMBER EXPLANATION
[0037] 100 semiconductor substrate
[0038] 210 first dielectric layer
[0039] 211 first trench
[0040] 220 second dielectric layer
[0041] 221 second trench
[0042] 310 first photoresist layer
[0043] 320 second photoresist layer
[0044] 400 sacrificial layer
[0045] S1-S11 steps DETAILED DESCRIPTION
[0046] Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure and the appended claims with the benefit of the present disclosure being taken into account. The present application can be implemented or carried out in ways other than those specifically described herein without departing from the spirit of the present application.
[0047] In describing the embodiments of the application, specific terminology is employed for the sake of clarity. The description is not intended to be limited to the details of the specific illustrated embodiments. Rather, the description is intended to be illustrative of the general inventive concept of the application. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. However, it will be apparent to those skilled in the art that the techniques described herein can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, for the sake of clarity.
[0048] For the sake of convenience, the terms "lower," "beneath," "below," "bottom," "upper," "above," and "top" can be used herein with reference to the figures to describe one element or feature's relationship to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Likewise, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present. The term "between" as used herein is intended to encompass both endpoints of the range.
[0049] In the context of this application, a structure described as having a first feature "on" a second feature can encompass embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features can not be in direct contact.
[0050] It should be noted that the drawings provided in the embodiments are only schematic and are intended to provide the basic understanding of the application. In reality, the shape, size, and number of components shown in the drawings can be varied significantly depending on the needs and preferences of the particular application. The layout of components in the drawings can also be more complex than what is shown.
[0051] Referring to Figure 1 The embodiment provides a trench preparation method, comprising the following steps:
[0052] S1: providing a semiconductor substrate;
[0053] S2: forming a first dielectric layer on the semiconductor substrate;
[0054] S3: forming a patterned first photoresist layer on the first dielectric layer;
[0055] S4: etching the first dielectric layer to form a first trench penetrating the first dielectric layer, the first trench having a first width;
[0056] S5: removing the first photoresist layer to expose the surface of the first dielectric layer;
[0057] S6: forming a sacrificial layer covering the surface of the first dielectric layer and filling the first trench;
[0058] S7: removing part of the sacrificial layer to expose the surface of the first dielectric layer;
[0059] S8: forming a second dielectric layer covering the surface of the first dielectric layer and the surface of the sacrificial layer;
[0060] S9: forming a patterned second photoresist layer on the second dielectric layer;
[0061] S10: etching the second dielectric layer to form a second trench penetrating the second dielectric layer, the second trench having a second width, and the second trench exposing the sacrificial layer;
[0062] S11: removing the second photoresist layer and the sacrificial layer to form a trench exposing the semiconductor substrate.
[0063] In the embodiment, the first dielectric layer is first formed on the semiconductor substrate, and then the first dielectric layer is etched to form the first trench. Then, the sacrificial layer is filled in the first trench. Then, the second dielectric layer is formed, and the second dielectric layer is etched to form the second trench exposing the sacrificial layer. Then, the sacrificial layer is removed to form the trench penetrating the first trench and the second trench. Thus, the trench with high aspect ratio can be prepared by the method of depositing and etching the dielectric layer step by step, and the preparation process is simple, the operation difficulty is low, the process precision is high, the product defect risk can be effectively reduced, and the product yield can be improved.
[0064] Specifically, the following will be described in combination with the accompanying drawings. Figures 2-8 The preparation process of the trench will be further introduced.
[0065] Firstly, step S1 is performed to provide the semiconductor substrate 100.
[0066] Specifically, referring to Figure 2 The semiconductor substrate 100 in the embodiment is a silicon substrate, but is not limited thereto. For example, the semiconductor substrate 100 can also be a silicon-on-insulator substrate, a silicon germanium substrate, a silicon carbide substrate, a germanium-on-insulator substrate, or a III-V compound substrate. The semiconductor substrate 100 can also include a doped region, and the like. The specific structure and material of the semiconductor substrate 100 are not limited herein.
[0067] Next, step S2 is performed to form a first dielectric layer 210 on the semiconductor substrate 100.
[0068] For example, the first dielectric layer 210 can include one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In the embodiment, the first dielectric layer 210 is a silicon oxide layer, but is not limited thereto. Other insulating dielectric layers can also be provided as needed. The method for forming the silicon oxide layer can be a CVD deposition method. The specific method and the thickness of the first dielectric layer 210 deposited can be set as needed.
[0069] Next, step S3 is performed to form a patterned first photoresist layer 310 on the first dielectric layer 210.
[0070] Specifically, referring to Figure 2 The step of forming the first photoresist layer 310 on the first dielectric layer 210 can include the steps of coating, exposing, developing, and heating. The method for forming the first photoresist layer 310 is not limited herein.
[0071] Next, step S4 is performed to etch the first dielectric layer 210 to form a first trench 211 that penetrates the first dielectric layer 210. The first trench 211 has a first width.
[0072] Specifically, referring to Figure 3 The first trench 211 is formed in the first dielectric layer 210 using the patterned first photoresist layer 310 as a mask and using an etching process. The first trench 211 exposes the semiconductor substrate 100 to form the first trench 211. The width and depth of the first trench 211 can be set as needed. Preferably, the aspect ratio of the first trench 211 is in the range of 1:1 to 100:1, such as 1:1, 10:1, 50:1, 100:1, and the like. The specific aspect ratio can be set as needed.
[0073] As an example, the first groove 211 may include a deep hole groove or a deep trench groove. The shape of the first groove 211 can be set as needed. For example, the cross-sectional shape of the first groove 211 may include a rectangle, an inverted trapezoid, a "V" shape, and a "U" shape. In this embodiment, the first groove 211 adopts a rectangular shape, but is not limited to this.
[0074] Next, step S5 is performed to remove the first photoresist layer 310 to expose the surface of the first dielectric layer 210 .
[0075] Next, step S6 is performed to form a sacrificial layer 400 . The sacrificial layer 400 covers the surface of the first dielectric layer 210 and fills the first trench 211 .
[0076] Specifically, such as Figure 4 The sacrificial layer 400 covers the first dielectric layer 210, wherein the material of the sacrificial layer 400 can be a BARC layer, but is not limited thereto. The material of the sacrificial layer 400 needs to be a material with a high selective etching ratio with the first dielectric layer 210, so as to avoid damage to the first dielectric layer 210 when removing the sacrificial layer 400. Therefore, the selection of the sacrificial layer 400 is related to the first dielectric layer 210 and is not overly restricted here.
[0077] Next, step S7 is performed to remove a portion of the sacrificial layer 400 to expose the surface of the first dielectric layer 210 .
[0078] Specifically, such as Figure 5 The BARC layer can be etched back through an etch-back process to expose the surface of the first dielectric layer 210 to facilitate subsequent processes, thereby completing the first deposition and etching steps and forming the sacrificial layer 400 with a transitional filling having a preset morphology in the first dielectric layer 210.
[0079] Next, step S8 is performed to form a second dielectric layer 220 . The second dielectric layer 220 covers the surface of the first dielectric layer 210 and the surface of the sacrificial layer 400 .
[0080] Specifically, such as Figure 6 The material of the second dielectric layer 220 may include a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. In this embodiment, the second dielectric layer 220 is made of the same material as the first dielectric layer 210, namely, a silicon oxide layer, but is not limited thereto. Other insulating dielectric layers may also be provided as needed. The silicon oxide layer may be formed by CVD deposition. The specific method and thickness of the deposited second dielectric layer 220 may be adjusted as needed.
[0081] Then, step S9 is performed to form a patterned second photoresist layer 320 on the second dielectric layer 220.
[0082] Specifically, as shown in FIG. 4, the step of forming the second photoresist layer 320 on the second dielectric layer 220 can include the steps of coating, exposing, developing and heating, and the method of forming the second photoresist layer 320 is not limited here. Figure 6 The second photoresist layer 320 can be made of the same material as the first photoresist layer 310, or can be made of different material.
[0083] Then, step S10 is performed to etch the second dielectric layer 220 to form a second trench 221 penetrating through the second dielectric layer 220, the second trench 221 has a second width, and the second trench 221 exposes the sacrificial layer 400.
[0084] Specifically, as shown in FIG. 5, the second trench 221 is formed in the second dielectric layer 220 by using the patterned second photoresist layer 320 as a mask and using an etching process, and the second trench 221 exposes the sacrificial layer 400. Figure 7 The width and depth of the second trench 221 can be set as required, and preferably, the aspect ratio of the second trench 221 is in the range of 1:1 to 100:1, such as 1:1, 10:1, 50:1, 100:1, etc., which can be set as required.
[0085] As an example, the second trench 221 can include a deep hole trench or a deep groove trench. The topography of the second trench 221 can be set as required, such as the cross-sectional shape of the second trench 221 can include one of a rectangle, an inverse trapezoid, a "V" shape and a "U" shape, and in the embodiment, the second trench 221 has a rectangular topography, but is not limited thereto.
[0086] As an example, preferably, the second width of the second trench 221 is greater than the first width of the first trench 211, so that the sacrificial layer 400 filled in the first trench 211 can be effectively removed through the second trench 221, so that the second trench 221 penetrates through the first trench 211.
[0087] As an example, preferably, the first trench 211 and the second trench 221 are both axisymmetric patterns, and the symmetry axes of the first trench 211 and the second trench 221 are the same perpendicular line, so that the removal of the sacrificial layer 400 in the first trench 211 can be further facilitated, and the formation of the axisymmetric trench can facilitate the subsequent filling of the material, so as to improve the quality of the product prepared.
[0088] Then, step S11 is performed to remove the second photoresist layer 320 and the sacrificial layer 400, so as to form a trench exposing the semiconductor substrate 100.
[0089] Specifically, after the sacrificial layer 400 is removed, the first trench 211 and the second trench 221 are connected, so that the trench with high aspect ratio can be prepared by the method of step-by-step deposition and step-by-step etching of the dielectric layer, and the preparation process is simple, the operation difficulty is low, the process precision is high, the product defect risk can be effectively reduced, and the product yield is improved.
[0090] As an example, between the removal of the second photoresist layer 320 and the removal of the sacrificial layer 400, a cycle step of forming a sacrificial layer and a dielectric layer can be further included M times, wherein M is a positive integer greater than or equal to 1.
[0091] Specifically, after the second photoresist layer 320 is removed and before the sacrificial layer 400 is removed, the steps S6-S10 can be repeated to ensure that the trench with the target depth is finally obtained. The value of M can include 1, 2, 3, etc., and can be selected as needed, which is not described here.
[0092] In summary, the preparation method of the trench of the present application first forms a first dielectric layer on a semiconductor substrate, etches the first dielectric layer to form a first trench, then forms a sacrificial layer filling the first trench, then forms a second dielectric layer, etches the second dielectric layer to form a second trench exposing the sacrificial layer, and then removes the sacrificial layer to form a trench in which the first trench and the second trench are connected. Therefore, by the method of step-by-step deposition and step-by-step etching of the dielectric layer, the trench with high aspect ratio can be prepared, and the preparation process is simple, the operation difficulty is low, the process precision is high, the product defect risk can be effectively reduced, and the product yield is improved. Therefore, the present application effectively overcomes the shortcomings of the prior art and has high industrial utilization value.
[0093] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. A method of manufacturing a trench, characterized by, The method comprises the following steps: S1: providing a semiconductor substrate; S2: forming a first dielectric layer on the semiconductor substrate; S3: forming a patterned first photoresist layer on the first dielectric layer; S4: etching the first dielectric layer to form a first trench penetrating the first dielectric layer, the first trench having a first width, and the depth-width ratio of the first trench ranging from 1:1 to 100:1; S5: removing the first photoresist layer to expose the surface of the first dielectric layer; S6: forming a sacrificial layer covering the surface of the first dielectric layer and filling the first trench, the sacrificial layer comprising a BARC layer; S7: performing a back etching on the BARC layer to remove part of the sacrificial layer and expose the surface of the first dielectric layer; S8: forming a second dielectric layer covering the surface of the first dielectric layer and the surface of the sacrificial layer; S9: forming a patterned second photoresist layer on the second dielectric layer; S10: etching the second dielectric layer to form a second trench penetrating the second dielectric layer, the second trench having a second width, and the second trench exposing the sacrificial layer, the depth-width ratio of the second trench ranging from 1:1 to 100:1, the second width of the second trench being greater than the first width of the first trench; the first trench and the second trench are both axisymmetric patterns, and the symmetry axes of the first trench and the second trench are the same perpendicular line; S11: removing the second photoresist layer; S12: performing the cycle steps of forming a sacrificial layer and a dielectric layer for M times again, wherein M is a positive integer greater than or equal to 1; S13: removing the sacrificial layer to form a trench exposing the semiconductor substrate.
2. The method of claim 1, wherein: The first dielectric layer and the second dielectric layer are layers of the same material.
3. The method of claim 1, wherein: The first trench comprises a deep hole trench or a deep groove trench; and the second trench comprises a deep hole trench or a deep groove trench.
4. The method of claim 1, wherein: The cross-sectional shape of the first trench comprises one of a rectangle, an inverted trapezoid, a "V" shape and a "U" shape; and the cross-sectional shape of the second trench comprises one of a rectangle, an inverted trapezoid, a "V" shape and a "U" shape.
5. The method of claim 1, wherein: The first dielectric layer comprises one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer; and the second dielectric layer comprises one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.
Citation Information
Patent Citations
Method of forming via and trench in copper dual damascene process
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