Junction termination of power transistor

Abstract

The present invention discloses a junction terminal of a power transistor, comprising a dielectric layer, a plurality of field limiting ring groups, and a plurality of field plates corresponding to the field limiting ring groups; the projected area of ​​the field plates on the dielectric layer is larger than the projected area of ​​the field limiting ring groups on the dielectric layer; wherein the field limiting ring groups comprise a main field limiting ring and a plurality of auxiliary field limiting rings; the main field limiting ring is connected to the corresponding field plate through a contact hole of the dielectric layer, and the auxiliary field limiting ring is isolated from the corresponding field plate through the dielectric layer. In this way, a field plate, a main field limiting ring, and a plurality of auxiliary field limiting rings form a composite structure, and under the constraint of the same blocking voltage, the number of field plates is smaller, the number of gaps between the field plates is also smaller, and the terminal exposure area is reduced accordingly. In the subsequent chip process, packaging process, and external environment, the charge entering the dielectric layer through these gaps is reduced as much as possible, so as to avoid the destruction of the electric field distribution of the junction terminal due to excessive accumulation of charge, and prevent the voltage resistance of the power transistor from being reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor power transistors, and in particular relates to a junction terminal of a power transistor. Background Art

[0002] Breakdown voltage is one of the most important parameters of power transistors. It determines the rated power of power transistors together with the maximum current capacity. Among them, the breakdown voltage of insulated gate bipolar transistor (IGBT) chips, metal-oxide-semiconductor field-effect transistor (MOSFET) chips, and fast recovery diode (FRD) chips are all borne by a large area of ​​PN junction. In the chip process, there is inevitably an edge PN junction surface bending effect. The main factors affecting the device breakdown voltage are the electric field concentration caused by the junction surface bending in the PN junction diffusion window area and the surface electric field concentration caused by the interface charge. Because these factors make the actual breakdown voltage of the device only 10-40% of the ideal situation. Therefore, in order to protect the power transistor to work normally under high voltage, it is usually necessary to use junction terminal protection technology at the chip boundary to eliminate the influence of the junction surface bending effect, reduce the surface electric field strength, and increase the breakdown voltage of the power transistor.

[0003] At present, the junction termination technology mainly has the following basic structures: field plate termination technology, field limiting ring termination technology, junction termination extension technology, lateral variable doping technology, semi-insulating polysilicon, etc. Due to the compatibility with the power transistor process, the field limiting ring and field plate technology in the planar junction termination technology are the most commonly used termination technologies for power transistors. Among them, the field plate technology can effectively suppress the breakdown caused by the surface charge and shield the influence of the charge in the passivation layer; the field limiting ring technology has a significant effect on the voltage division of the main junction, and is also very significant in alleviating the PN junction breakdown caused by the curvature effect of the planar junction.

[0004] The field limiting ring-field plate composite terminal technology combines the advantages of the two technologies, using the field limiting ring to achieve voltage division of the main junction and improve the withstand voltage of the device. The field plate is connected to the field limiting ring through the contact hole, and its potential is the same as the silicon in contact with its bottom, which can partially shield the charge in the oxide layer and reduce the electric field on the silicon surface. However, there are large gaps between the metal field plates that meet the terminal structure, which will cause the charges introduced by the subsequent chip process, packaging process and external environment to enter the dielectric layer through these gaps. When the accumulated charge is too much, it will destroy the electric field distribution of the terminal, resulting in a decrease in the withstand voltage of the power transistor. Summary of the invention

[0005] The main purpose of the present invention is to provide a junction terminal of a power transistor to solve the problem in the prior art that due to the presence of large gaps between metal field plates, charges introduced in subsequent chip processes, packaging processes and the external environment will enter the dielectric layer through these gaps. When too much charge is accumulated, the electric field distribution of the terminal will be destroyed, resulting in a decrease in the withstand voltage of the device.

[0006] In view of the above problems, the present invention provides a junction terminal of a power transistor, comprising a dielectric layer, a plurality of field limiting ring groups and a plurality of field plates corresponding to the field limiting ring groups;

[0007] The projected area of ​​the field plate on the dielectric layer is greater than the projected area of ​​the field limiting ring group on the dielectric layer;

[0008] Wherein, the field limiting ring group includes a main field limiting ring and a plurality of auxiliary field limiting rings;

[0009] The main field limiting ring is connected to the corresponding field plate through the contact hole of the dielectric layer, and the auxiliary field limiting ring is isolated from the corresponding field plate through the dielectric layer.

[0010] Furthermore, in the junction terminal of the power transistor described above, a projected area of ​​the main field limiting ring on the dielectric layer is larger than a projected area of ​​each of the auxiliary field limiting rings on the dielectric layer.

[0011] Further, in the junction terminal of the power transistor described above, the number of the plurality of auxiliary field limiting rings is 2N+1; N is an integer greater than or equal to 1;

[0012] The distance between the main field limiting ring and each of the auxiliary field limiting rings is equal.

[0013] Further, in the junction terminal of the power transistor described above, the number of the plurality of auxiliary field limiting rings is 2N; N is an integer greater than or equal to 1;

[0014] Any two auxiliary field limiting rings form an auxiliary field limiting ring pair;

[0015] The auxiliary field limiting ring pairs are symmetrically distributed around the main field limiting ring.

[0016] Furthermore, in the junction terminal of the power transistor described above, the distance between the two auxiliary field limiting rings in each auxiliary field limiting ring pair is equal or unequal.

[0017] Furthermore, the junction terminal of the power transistor described above further includes a field stop ring and a field stop plate;

[0018] The field stop ring and the field stop plate are both located at the edge of the dielectric layer;

[0019] And the field stop ring is connected to the field stop plate.

[0020] Furthermore, in the junction terminal of the power transistor described above, in a direction extending away from the dielectric layer, the length of the field stop ring is greater than the length of the main field limiting ring and the length of the auxiliary field limiting ring.

[0021] Furthermore, in the junction terminal of the power transistor described above, the dielectric layer includes an oxide layer, a silicon nitride layer or an oxide combination layer; wherein the oxide combination layer is formed by a semi-insulating polysilicon layer and an oxide layer.

[0022] Furthermore, in the junction terminal of the power transistor described above, the field plate is a conductive field plate.

[0023] Furthermore, in the junction terminal of the power transistor described above, the conductive field plate includes an aluminum field plate, an aluminum alloy field plate or a polysilicon field plate.

[0024] Compared with the prior art, one or more embodiments of the above scheme may have the following advantages or beneficial effects:

[0025] The junction terminal of the power transistor of the present invention forms a composite structure with a field plate, a main field limiting ring and a plurality of auxiliary field limiting rings, and only uses the main field limiting ring to connect with the corresponding field plate through a contact hole, so that the field plate potential is the same as the silicon contacted at the bottom, which can partially shield the charge in the oxide layer and reduce the electric field on the silicon surface. At the same time, multiple auxiliary field limiting rings and the main field limiting ring are used to realize the voltage division of the main junction and improve the withstand voltage of the device. In this way, the size of the field plate can be made larger. Under the constraint of the same blocking voltage, it is equivalent to a composite mode of one field plate corresponding to one field limiting ring. The number of field plates is smaller, the number of gaps between the field plates is also smaller, and the terminal exposure area is reduced accordingly. In the subsequent chip process, packaging process and external environment, the charge is reduced as much as possible to enter the dielectric layer through these gaps, so as to avoid the electric field distribution of the junction terminal being destroyed due to excessive accumulation of charge, and to prevent the withstand voltage of the power transistor from being reduced.

[0026] Other features and advantages of the present invention will be described in the following description, and part of the description will become apparent, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0028] Figure 1A schematic diagram of the structure of a junction terminal of a power transistor in the related art;

[0029] Figure 2 It is a schematic structural diagram of a junction terminal embodiment of a power transistor of the present invention. DETAILED DESCRIPTION

[0030] The following will describe the implementation methods of the present invention in detail with reference to the accompanying drawings and embodiments, so that the implementation process of how the present invention applies technical means to solve technical problems and achieve technical effects can be fully understood and implemented accordingly. It should be noted that as long as there is no conflict, the various embodiments of the present invention and the various features in the embodiments can be combined with each other, and the technical solutions formed are all within the protection scope of the present invention.

[0031] Figure 1 FIG. 1 is a schematic diagram of a junction terminal of a power transistor in the related art. Figure 1 As shown, the junction terminal of the power transistor in the related art may include a collector 11, a base region 12 (i.e., a substrate), a plurality of field limiting rings 13, a dielectric layer 14 arranged between the field limiting rings 13 and the field plates 15, and the field plates 15, wherein the field limiting rings 13 include two doped regions with the same conductivity type but different doping concentrations, and the conductivity type is a P+ type.

[0032] However, Figure 1 In the junction terminal of the power transistor shown, there are large gaps between the field plates, and the number of field plates is large, and there are also many gaps between the field plates, which will cause the charges introduced in the subsequent chip process, packaging process and external environment to enter the dielectric layer through these gaps. When the accumulated charges are too much, the electric field distribution of the terminal will be destroyed, resulting in a decrease in the device's withstand voltage. In addition, this type of junction terminal will introduce hot carriers into the dielectric layer due to the surface electric field effect during the reverse bias process. Since the direction of the electric field at the edge interface of the field plate points from silicon to silicon dioxide, the holes generated by the avalanche will jump to the dielectric layer, and the increase in the charge in the dielectric layer will cause the device's withstand voltage to decrease.

[0033] Therefore, in order to solve the above-mentioned technical problems existing in the related art, the embodiments of the present invention provide the following technical solutions.

[0034] Figure 2 FIG. 1 is a schematic diagram of a structure of a junction terminal embodiment of a power transistor of the present invention, as shown in FIG. Figure 2As shown, the junction terminal of the power transistor of this embodiment may include a dielectric layer 14, a plurality of field limiting ring groups 16, and a plurality of field plates 15 corresponding to the field limiting ring groups 16; the projection area of ​​the field plates 15 on the dielectric layer 14 is larger than the projection area of ​​the field limiting ring group 16 on the dielectric layer 14. The field limiting ring group 16 includes a main field limiting ring 161 and a plurality of auxiliary field limiting rings 162. The main field limiting ring 161 is connected to the corresponding field plate 15 through the contact hole of the dielectric layer 14, and the auxiliary field limiting ring 162 is isolated from the corresponding field plate 15 through the dielectric layer 14.

[0035] In the junction terminal of the power transistor of this embodiment, a field plate 15 forms a composite structure with a main field limiting ring 161 and a plurality of auxiliary field limiting rings 162, and only the main field limiting ring 161 is connected to the corresponding field plate 15 through a contact hole, so that the electric potential of the field plate 15 is the same as the silicon in contact with its bottom, which can partially shield the charge in the oxide layer and reduce the electric field on the silicon surface. At the same time, multiple auxiliary field limiting rings 162 and the main field limiting ring 161 are used to realize the voltage division of the main junction and improve the withstand voltage of the device. In this way, the size of the field plate 15 can be made larger. Under the constraint of the same blocking voltage, it is equivalent to a composite mode in which one field plate 15 corresponds to one field limiting ring. The number of field plates 15 is smaller, the number of gaps between the field plates 15 is also smaller, and the terminal exposure area is reduced accordingly. In the subsequent chip process, packaging process and external environment, the charge is reduced as much as possible to enter the dielectric layer 14 through these gaps, so as to avoid the electric field distribution of the junction terminal being destroyed due to excessive accumulation of charge, and to prevent the withstand voltage of the power transistor from being reduced.

[0036] In a specific implementation process, the projection area of ​​the main field limiting ring 161 on the dielectric layer 14 is larger than the projection area of ​​each auxiliary field limiting ring 162 on the dielectric layer 14. In other words, the ring diameter of the main field limiting ring 161 is larger than the ring diameter of each auxiliary field limiting ring 162.

[0037] In a specific implementation process, by carefully designing the length of the field plate 15 and reasonably arranging the auxiliary field limiting ring 162 and the main field limiting ring 161, a balance between avalanche hot electrons and holes under reverse bias can be achieved, thereby reducing the impact on the terminal electric field, improving the high-temperature reverse bias test capability of the terminal, and improving the long-term reliability of the device.

[0038] Specifically, if the number of the plurality of auxiliary field limiting rings 162 is 2N+1, N is an integer greater than or equal to 1, and the distance between the main field limiting ring 161 and each of the auxiliary field limiting rings 162 is equal. In other words, if the number of the auxiliary field limiting rings 162 is an odd number, the auxiliary field limiting rings 162 can be distributed according to the principle that the distance between the main field limiting ring 161 and each of the auxiliary field limiting rings 162 is equal. For example, the plurality of auxiliary field limiting rings 162 can be distributed on a circle with the main field limiting ring 161 as the center.

[0039] In a specific implementation process, the number of the plurality of auxiliary field limiting rings 162 is 2N; N is an integer greater than or equal to 1; any two auxiliary field limiting rings 162 form an auxiliary field limiting ring 162 pair; the auxiliary field limiting ring 162 pair is symmetrically distributed around the main field limiting ring 161. The distance between the two auxiliary field limiting rings 162 in each pair of auxiliary field limiting rings 162 is equal or unequal.

[0040] For example, multiple auxiliary field limiting rings 162 can be distributed on both sides of the main field limiting ring 161 to form a straight line distribution, or can be distributed on multiple sides of the main field limiting ring 161 to form a circular distribution or a polygonal distribution, etc. This embodiment does not make any specific limitations.

[0041] In a specific implementation process, the distribution method between the auxiliary field limiting ring 162 and the main field limiting ring 161 can ensure that Figure 2 The number of hot electrons generated in region A is equivalent to the number of hot holes generated in region B, which can achieve a balance between avalanche hot electrons and holes under reverse bias conditions, reduce the impact on the terminal electric field, improve the high-temperature reverse bias test capability of the terminal, and improve the long-term reliability of the device.

[0042] In a specific implementation process, Figure 2 As shown, the junction terminal of the power transistor may further include a field stop ring 17 and a field stop plate 18. The field stop ring 17 and the field stop plate 18 are both arranged at the edge of the dielectric layer 14; and the field stop ring 17 is connected to the field stop plate 18. In other words, the field stop ring 17 is arranged at the periphery of the main field limiting ring 161 and the plurality of auxiliary field limiting rings 162, and the field stop plate 18 is arranged at the periphery of the plurality of field plates 15.

[0043] In a specific implementation process, in a direction extending away from the dielectric layer 14 , the length of the field stop ring 17 is greater than the length of the main field limiting ring 161 and the length of the auxiliary field limiting ring 162 .

[0044] In a specific implementation process, the dielectric layer 14 includes an oxide layer, a silicon nitride layer or an oxide combination layer; wherein the oxide combination layer is formed by a semi-insulating polysilicon layer and an oxide layer. The field plate 15 is a conductive field plate 15. The conductive field plate 15 includes an aluminum field plate 15, an aluminum alloy field plate 15 or a polysilicon field plate 15.

[0045] In a specific implementation process, the junction terminal of the power transistor may also include a collector and a base region. The main field limiting ring 161 and the plurality of auxiliary field limiting rings 162 are both located in the base region; the collector is located on a side of the base region away from the field limiting ring group 16 .

[0046] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0047] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0048] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0049] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted for facilitating the understanding of the present invention and are not intended to limit the present invention. Any technician in the technical field to which the present invention belongs can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in the present invention, but the protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A junction terminal of a power transistor, characterized in that: It includes a base region, a dielectric layer, a plurality of field limiting ring groups and a plurality of field plates corresponding to the field limiting ring groups; The projected area of ​​the field plate on the dielectric layer is greater than the projected area of ​​the field limiting ring group on the dielectric layer; The field limiting ring group includes a main field limiting ring and a plurality of auxiliary field limiting rings; the main field limiting ring and the auxiliary field limiting rings are both located on the surface of the base region; the plurality of auxiliary field limiting rings are located on two or more sides of the main field limiting ring and are spaced apart from the main field limiting ring; The main field limiting ring is connected to the corresponding field plate through the contact hole of the dielectric layer, and the auxiliary field limiting ring is isolated from the corresponding field plate through the dielectric layer; The projection area of ​​the main field limiting ring on the dielectric layer is greater than the projection area of ​​each of the auxiliary field limiting rings on the dielectric layer.

2. The junction terminal of a power transistor according to claim 1, characterized in that The number of the plurality of auxiliary field limiting rings is 2N+1; N is an integer greater than or equal to 1; The distance between the main field limiting ring and each of the auxiliary field limiting rings is equal.

3. The junction terminal of the power transistor according to claim 1, characterized in that The number of the plurality of auxiliary field limiting rings is 2N; N is an integer greater than or equal to 1; Any two auxiliary field limiting rings form an auxiliary field limiting ring pair; The auxiliary field limiting ring pairs are symmetrically distributed around the main field limiting ring.

4. The junction terminal of the power transistor according to claim 3, characterized in that The distance between the two auxiliary field limiting rings in each auxiliary field limiting ring pair is equal or unequal.

5. The junction termination of a power transistor according to claim 1, characterized in that Also included are a field cutoff ring and a field cutoff plate; The field stop ring and the field stop plate are both located at the edge of the dielectric layer; And the field stop ring is connected to the field stop plate.

6. The junction termination of a power transistor according to claim 5, characterized in that In a direction extending away from the dielectric layer, the length of the field stop ring is greater than the length of the main field limiting ring and the length of the auxiliary field limiting ring.

7. The junction termination of a power transistor according to claim 1, characterized in that The dielectric layer includes an oxide layer, a silicon nitride layer or an oxide combination layer; wherein the oxide combination layer is formed by a semi-insulating polysilicon layer and an oxide layer.

8. The junction termination of a power transistor according to claim 1, characterized in that The field plate is a conductive field plate.

9. The junction termination of a power transistor according to claim 8, characterized in that The conductive field plate includes an aluminum field plate, an aluminum alloy field plate or a polysilicon field plate.

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