Matrix array detector with multiple sets of driver modules and method of implementing the detector

Abstract

The invention provides a matrix array detector having multiple groups of driver modules and a method of implementing the detector. The matrix array detector comprises: a pixel array, the pixel array being sensitive to a physical effect and arranged in a matrix along rows and columns, each pixel generating a signal according to the physical effect; line conductors (L), each line conductor allowing to drive a row of pixels; a first group (A) of driver modules (SR_A), each driver module (SR_A) delivering a selection signal (Out_A) to one line conductor (L) of the first group of line conductors; a second group (B) of driver modules (SR_B), each driver module (SR_B) delivering a selection signal (Out_B) to one line conductor (L) of the first group of line conductors; the first group of line conductors and the second group of line conductors being interleaved.

Description

Technical Field

[0001] This invention relates to matrix array detectors and methods for implementing such detectors. The invention can be used to generate visible images, but is not limited to this field. For example, it can generate two-dimensional representations of pressure or temperature maps or chemical or electrical potentials. These maps or representations form images of physical quantities. The invention is particularly applicable to active matrix array detectors in imaging devices employing ionizing radiation (e.g., X-rays), such as those used for detection purposes, for example, as TFT panels, where TFT stands for "thin-film transistor". Background Technology

[0002] In a matrix array detector, pixels represent the basic sensitive elements of the detector. Each pixel converts the physical effects it experiences into electrical signals. These electrical signals from the individual pixels are collected at the matrix array readout stage and then digitized so that they can be processed and stored to form an image. For example, a pixel is formed by a region that is sensitive to physical effects and carries a charge current. The physical effect can be electromagnetic radiation that carries a photon flux, and therefore the invention will be interpreted according to this type of radiation, and the charge current depends on the photon flux received by the sensitive region. Generalization to any matrix array detector is straightforward.

[0003] A matrix array image detector includes row conductors, each connecting pixels in the same row; and column conductors, each connecting pixels in the same column. The column conductors are connected to converter circuitry, which is typically located at the edge of the matrix array; this edge may be referred to as the "foot of the column."

[0004] Each pixel typically includes a photosensitive element or photodetector, which may be, for example, a photodiode, a photoresistor, or a phototransistor. There are large-scale photosensitive matrix arrays, which may contain millions of pixels arranged in rows and columns. Each pixel also includes electronic circuitry, which includes, for example, switches, capacitors, and resistors, with an actuator located downstream of the electronic circuitry. The assembly including the photosensitive element and electronic circuitry allows for the generation and collection of charge. This electronic circuitry typically allows for the reset of the charge collected in each pixel after a charge transfer. The actuator's role is to transfer or copy the charge collected by the electronic circuitry into the column conductor. The actuator executes the transfer when it receives a command to perform the transfer from the row conductor. The output of the actuator corresponds to the output of the pixel. The terms "row conductor" and "column conductor" are entirely arbitrary. These terms can certainly be used interchangeably.

[0005] In this type of detector, the pixel operates in two phases: an image capture phase in which the pixel's electronic circuitry accumulates the charge generated by the photosensitive element, and a readout phase in which the collected charge is transferred or copied into the column conductor by an actuator.

[0006] During the reading phase, the row conductors send reading commands to all actuators in the same row of the matrix array. Each pixel in that row is read by sending its electrical information, such as charge, voltage, current, frequency, etc., to the column conductor associated with that pixel.

[0007] For an image frame, pixel rows can be sequentially selected in the direction of scanning the rows of the matrix array during a row selection time corresponding to a portion of the frame duration, thereby allowing an appropriate signal (e.g., voltage) to be applied to the pixels of the relevant row. Therefore, selecting a row corresponds to applying a high-level signal during the corresponding row selection time, which controls the on-state of the switching device of the corresponding pixel row. Outside of this row selection time, the switching device is held off by applying an appropriate low-level signal. For example, when the switching device is a transistor and the applied signal is a voltage, it is common practice to use VGon to represent the voltage corresponding to the high level and thus the on-state of the switching transistor, and VGoff to represent the voltage corresponding to the low level and the off-state of the switching transistor.

[0008] Rows can be controlled by control circuitry comprising one or more shift registers connected in series, each shift register comprising multiple cascaded stages, each stage adapted to switch high and low levels of signals applied to the actuators of the pixels for the corresponding rows of the matrix array according to the order of row selection operations (e.g., vertical scan). The control circuitry can be implemented in an integrated circuit, the same integrated circuit being capable of having multiple control circuits for multiple rows in the matrix array, for example. This integrated circuit can be, for example, external to the matrix array and connected to the matrix array via a wired connection, such as via a flexible ribbon cable. The control circuitry can also be mounted on a board carrying the pixels, as described in patent application WO2012 / 152836A1 filed in the name of the applicant.

[0009] This allows for a reduction in the number of signals applied to the board, thereby reducing the size and number of flexible connectors used to connect the board to surrounding electronics. This integrated control circuit architecture significantly simplifies the detector architecture by reducing the number of components and simplifying the manufacturing process.

[0010] However, this architecture dictates the order in which the matrix rows are driven. This order is determined by the connection between the control circuitry and the matrix rows. In some cases, it may be desirable to change the order in which the matrix rows are controlled. More specifically, it may be desirable to group multiple pixels together for common readout. This grouping, referred to in the literature as "binning," allows for improved signal-to-noise ratio (SNR) of the individual readout pixels. Another advantage of grouping pixels together is improved detector sensitivity. However, grouping together negatively impacts spatial resolution.

[0011] When the information from each pixel is electrical charge, pixel grouping can be achieved by redistributing the charge from the pixels to be grouped together on a common capacitor, for example, located in a converter circuit at the foot of a column. This can be achieved in a detector such as that described in patent application WO2012 / 152836A1 by continuously reading out rows of pixels. However, in such a detector, grouping consecutive rows of pixels together does not improve the detector's readout speed, nor does it increase the frequency of images generated by the detector. Summary of the Invention

[0012] The present invention aims to overcome all or some of the aforementioned problems by providing a detector whose control circuitry allows for conventional sequential readout or grouping of pixels belonging to consecutive rows, thereby improving readout speed. The invention is particularly advantageous in detectors where the control circuitry and pixels are generated on the same substrate.

[0013] Therefore, one subject of the present invention is a matrix array detector, the matrix array detector comprising:

[0014] An array of pixels, the pixels being sensitive to physical effects and arranged in a matrix along pixel rows and columns, each pixel generating a signal according to the physical effects, the rows of the pixels being physically ordered;

[0015] Row conductors, each row conductor allows driving one row of pixels;

[0016] Each driver module is associated with a row conductor, and each driver module transmits a selection signal to one of the row conductors. The driver modules are distributed in multiple groups, which are interleaved according to the order of the rows of pixels.

[0017] The driver modules of each group are linked to each other in the physical order of the rows associated with the driver module group in question, and the linking of each driver module group is independent of the linking of one or more other driver module groups.

[0018] Advantageously, the matrix array detector further includes a module for generating multiple tokens, each token being passed to the input of a first driver module in a group of driver modules, wherein the output of each module in each group of driver modules is connected to the input of a module with a higher sequence number, the driver modules in their respective groups being ordered in order of pixel rows, the conductors of which are transmitted the selection signal by the driver module in question.

[0019] Advantageously, the pixel and the driver module are manufactured on the same substrate, which is based on either n-type thin-film transistors only or p-type thin-film transistors only.

[0020] Another subject of the invention is a method using a matrix array detector according to the invention, wherein driver modules belonging to different groups and connected to continuous row conductors are capable of receiving simultaneous control signals to drive the continuous rows simultaneously, or receiving alternating control signals to drive the continuous rows separately. Attached Figure Description

[0021] The invention will be better understood and further advantages will become apparent from the detailed description of the embodiments given by way of example, illustrated in the accompanying drawings, wherein:

[0022] Figure 1 An exemplary pixel matrix array that can be implemented in a detector according to the present invention is shown;

[0023] Figure 2 An exemplary detector according to the present invention is shown;

[0024] Figure 3 It shows that it can be used Figure 2 An exemplary implementation of multiple driver modules implemented in the detector;

[0025] Figure 4 It shows that it can be used Figure 2 Another exemplary implementation of multiple driver modules implemented in the detector;

[0026] Figure 5 It shows Figure 4 Detailed examples of driver modules;

[0027] Figure 6 An example of the operation of the detector implementing the driver module is shown in the form of a timing diagram. The driver module is as follows: Figure 5 As shown, and linked into only one group;

[0028] Figure 7 An example of the operation of the detector implementing the driver module is shown in the form of a timing diagram. The driver module is as follows: Figure 5 As shown, they are linked into two groups to read out the detector pixels individually;

[0029] Figure 8 An example of the operation of the detector implementing the driver module is shown in the form of a timing diagram. The driver module is as follows: Figure 5 As shown, they are linked into two groups for joint readout of the detector's pixels.

[0030] For clarity, the same elements in each figure will be labeled with the same reference numerals. Detailed Implementation

[0031] The following description is provided with reference to a matrix array detector comprising multiple basic electronic circuits referred to as pixels, each basic electronic circuit including elements sensitive to physical quantities. In the described example, the basic electronic circuits are pixels sensitive to light radiation. It is apparent that the invention can be used with other detectors sensitive to any form of physical quantity, allowing the generation of, for example, pressure maps or temperature maps.

[0032] Figure 1 The detection area 10 of the matrix array detector is schematically shown. For ease of understanding, the detection area contains a two-row, two-column matrix, forming four pixels P, each located at the intersection of a row and a column. Of course, actual matrix arrays are usually much larger and have a large number of rows and columns. The pixel matrix array belongs to the matrix array detector 12 that allows the generation of digital images.

[0033] Each pixel P includes a photosensitive area and electronic processing circuitry. The photosensitive area is represented here by a photodiode D, and the electronic processing circuitry... Figure 1 The example shown is formed by a single transistor T. The reference numerals for components D and T are followed by two coordinates indicating row numbers i and i+1 and column numbers j and j+1, respectively. The rows and columns are ordered according to their physical order of occupation in the pixel matrix array. The pixel shown has one transistor each, hence it is also called a 1T pixel, whose function will be further described below.

[0034] Typically, the common practice is to produce pixel matrix arrays that include thin-film field-effect transistors (TFTs). TFTs can be based on metal oxides, such as transistors based on amorphous or crystalline indium oxide, gallium, and zinc oxide, which are abbreviated as IGZO. Other TFT families can be used, such as organic TFTs, amorphous silicon TFTs, or polycrystalline silicon TFTs. In this last type of TFT, some are synthesized at low temperatures. These are named using the acronym LTPS (Low Temperature Polycrystalline Silicon).

[0035] Pixels P in the same column are connected to the column conductor Col. This conductor allows information to be collected from the pixels connected to it. Pixels P in the same row are connected to the row conductor L, which carries the signal VG, thus allowing control of the corresponding pixel row.

[0036] During the image capture phase, which occurs after the reset operation, the photodiode D receives illumination, reducing the potential of its cathode. This image capture phase is followed by a readout phase, in which the potential of the photodiode D is read. For this purpose, the transistor T is turned on, thus acting as a switch, which is controlled by a control signal VG applied to its gate.

[0037] When selected by signal VG, column conductor Col is used to collect information from the pixels in the corresponding column.

[0038] The invention can be implemented in detectors with simpler pixels, particularly by replacing transistor T with a simple diode turned on by signal VG. It can also be implemented in detectors with pixels comprising multiple transistors. Specifically, 3T pixels are known to be implemented, which, in addition to the aforementioned readout transistor, include a reset transistor for the photodiode and a follower transistor. In this type of 3T pixel, a second row of conductors transmits a reset signal that allows control of resetting the transistors.

[0039] Figure 2 The entire detector 12 is schematically shown. Detector 12 includes a plate 14 forming a substrate on which the components of the detection area 10 are formed. A driver module 16 that transmits control signals to all row conductors L is disposed on the same plate 14. Alternatively, the driver module 16 may be fabricated on a different substrate than plate 14. However, fabricating the driver module 16 and the pixel P on the same substrate can limit the connections between plate 14 and its surrounding components.

[0040] Detector 12 includes a readout circuit 18 connected to the column conductor Col. The readout circuit 18 is typically fabricated on a different substrate than board 14. The readout circuit 18 is connected to board 14 via a ribbon cable.

[0041] The detector 12 includes circuitry 20 that allows the driver module 16 to be driven and allows signals from the readout circuitry 18 to be acquired, particularly for signal multiplexing.

[0042] Figure 3 A first exemplary embodiment of four driver modules 16 is shown, each configured to drive one row of pixels. It will be clearly understood that the invention can be implemented for more rows of pixels. More specifically, the output Out_A(n) of the first driver module, represented by SR_A(N), is connected to the row conductor L(i), which transmits the readout signal VG for the i-th row. The output Out_B(n) of the second driver module, represented by SR_B(N), is connected to the row conductor L(i+1), which transmits the readout signal VG for the (i+1)-th row. The output Out_A(n+1) of the third driver module, represented by SR_A(N+1), is connected to the row conductor L(i+2), which transmits the readout signal VG for the (i+2)-th row. The output Out_B(n+1) of the fourth driver module, represented by SR_B(N+1), is connected to the row conductor L(i+3), which transmits the read signal VG for the (i+3)th row. The row and driver modules are connected in sequence. Figure 3The order of reading is as follows. More specifically, when reading each row of pixels individually, the i-th row is read first, then the (i+1)-th row, then the (i+2)-th row, and finally the (i+3)-th row. As will be seen further, the driver module is configured to also allow reading by grouping consecutive pairs of rows together.

[0043] In the example shown, the driver modules are distributed in two groups: driver modules SR_A(N) and SR_A(N+1) are in the first group A, and driver modules SR_B(N) and SR_B(N+1) are in the second group B. This invention can be implemented with more groups of driver modules. Rows are also divided into two groups: one is group LA for rows L(i) and L(i+2), and the other is group LB for rows L(i+1) and L(i+3). Driver module group A is associated with row group LA, while driver module group B is associated with row group LB. Row groups LA and LB, as well as driver module groups A and B, are interleaved. More specifically, within each group, the driver modules are ordered according to the physical order of the rows of the matrix array. For the two driver module groups A and B, according to the physical order of the rows of the matrix array, the first driver module SR_A(1) of the first group A drives the first row L(1) of the matrix array. The first driver module SR_B(1) of the second group B drives the second row L(2). The second driver module SR_A(2) of group A drives the third row L(4). The second driver module SR_B(2) of group B drives the fourth row L(1), and so on, until the last row of the matrix array. More generally, for K groups of driver modules, the following notation is used:

[0044] i: The index of the current row in the physical order of the rows in the matrix array.

[0045] j: The module's sequence number within its group.

[0046] k: The group number, between 1 and K.

[0047] The i-th row is driven by the module with index j in group k, where:

[0048] i = (j-1)K+k.

[0049] Distributing the row and driver modules into groups that are related to each other makes it possible to drive the groups of rows differently, and in particular by adjusting the synchronization of the groups of driver modules and thus by adjusting the driving of the groups of rows.

[0050] Figure 3An implementation of a particularly simple connection for the driver modules is shown. It is clearly understood that other connections are also possible. Each driver module includes inputs In_A(n), In_B(n), In_A(n+1), In_B(n+1) that enable receiving commands for the module in question; and outputs Out_A(n), Out_B(n), Out_A(n+1), Out_B(n+1) that enable driving the associated rows, respectively. Within each group, the driver modules are linked to each other in the order of the rows associated with the group in question. The linking of a group is independent of the linking of one or more other groups of driver modules. More specifically, in the example shown, output Out_A(n) is connected to input In_A(n+1), and output Out_B(n) is connected to input In_B(n+1).

[0051] Detector 12 includes a generation module 30 that enables the generation of a first token IN_A, which is passed to the input of a first driver module SR_A(N) in group A. Generation module 30 also enables the generation of a second token IN_B, which is passed to the input of a first driver module SR_B(N) in group B. The linking of driver modules allows tokens to travel from one driver module to the next in the same group. More generally, generation module 30 enables the generation of the same number of tokens as the number of driver module groups.

[0052] In addition, the driver module receives one or more control signals: "N Control A" for group A and "N Control B" for group B. These control signals are, for example, clock signals, at which tokens are transmitted from one module to another in the same group. The control signals can be generated by a generation module 30, which can be located on board 14 or on a separate substrate, such as in circuit 20. Connections for control signals between individual driver modules and output-to-input connections between successive modules can be made on board 14, thus eliminating the need for external connections.

[0053] Detector 12 can operate in various ways, either by generating signals VG sequentially for each row of the matrix array (allowing individual readout of pixels from detector 12), or by generating signals VG simultaneously in modules with the same sequence number in two groups. In other words, signals VG are simultaneously sent by driver modules SR_A(N) and SR_B(N), and then simultaneously sent by driver modules SR_A(N+1) and SR_B(N+1), allowing information from pixels originating from different rows to be grouped together. By changing the transmission timing of tokens IN_A and IN_B, and the underlying driver module control signals, two types of detector readout (i.e., individual readout or readout by pixel group) can be selected. Simultaneous transmission of both tokens allows readout by group. Alternating transmission of both tokens allows individual readout.

[0054] By distributing the driver modules in two groups, the readouts of two rows of pixels can be grouped together. More generally, K groups can group the readouts of K rows together. It is also possible to group rows by a divisor of the number of groups. For example, for four groups of driver modules, the readout matrix array can be read individually, in groups of two rows, or in groups of four rows, depending on the offset in the transmission of the token and the corresponding control signal for each group.

[0055] Figure 4 Another exemplary embodiment of four driver modules 16 is shown, each driver module configured to drive a row of pixels. In this example, each driver module includes an input stage E and an output stage S. The input stage E transmits an activation signal Outa or Outb for the corresponding output stage S. When activated by the input stage, the corresponding output stage sends the output signal for the driver module, denoted here by Gateline. This example with two stages corresponds to the scheme described in the aforementioned patent application WO2012 / 152836A1. The transmission of a token between two consecutive driver modules in the same group is achieved by sending an activation signal to the input of the input stage of the module with the higher sequence number. The input stages of the respective modules that allow the transmission of the token and their connections form a shift register. The respective output stages form an amplifier that allows the activation signal to be adapted to the characteristics of the signal VG.

[0056] Figure 5 It shows in more detail Figure 4 A diagram of one of the driver modules. The integrated structure forming the row-addressing device according to the invention can primarily comprise a single type of transistor TFT, i.e., p-type or n-type, with n-type being preferred due to its superior performance. Therefore, all transistors described below can be single n-type or p-type thin-film transistor TFTs.

[0057] Figure 5The illustrated structure corresponds to an advantageous embodiment in which each stage n of the row-addressing device includes an input stage 50 and an output stage 51. For each stage n of the row-addressing device, the input stage 50 and the output stage 51 each include, for example, those referenced above. Figure 3 Most of the elements included in the described row addressing level n are shown. It should be noted that in the described exemplary embodiment, each row n of the matrix array is associated with a level n of the addressing device. However, in alternative examples not shown in the figures, row addressing device structures can be envisioned where a given level controls multiple rows, or where some rows are not controlled by any level.

[0058] Therefore, the input stage 50 for stage n of the row-addressed device can be formed by a shift register including an output row that presents the activation signal Out(n) as an output. Input stage 50 may include an output transistor T30 for the input stage, which transmits a pulse of the clock signal at the activated output Out(n). The gate of the output transistor T30 for the input stage may be connected to an internal node of the input stage of the row-addressed device, its source may be connected to the activated output Out(n), and its drain may receive a signal from a first clock CLK1. A boost capacitor C20 for the input stage may be connected between the gate and source of the output transistor T30 for the input stage. A first control transistor T10 for the input stage may precharge the gate of the output transistor T30 for the input stage. The source of the first control transistor T10 for the input stage is therefore connected to the gate of the output transistor T30 for the input stage. The gate and drain of the first control transistor T10 for the input stage are controlled by the activated output Out(n-1) of stage n-1 of the addressing device for the previous row n-1.

[0059] The second control transistor T20 for the input stage is capable of discharging the gate of the output transistor T30 for the input stage. The drain of the second control transistor T20 for the input stage is therefore connected to the gate of the output transistor T30 for the input stage. The compensation capacitor C10 for the input stage can advantageously be positioned between the signals from the second clock CLK2, which is out of phase with the signals from the first clock CLK1.

[0060] Advantageously, the discharge transistor T40 for the input stage can be connected to the active output Out(n) of the input stage 50 for stage n of the row-addressed device. The gate of the discharge transistor T40 for the input stage is connected to the gate of the second control transistor T20 for the input stage; it is also connected to the active output signal Out(n+1) for the next stage n+1.

[0061] Similarly, the output stage 51 of stage n of the row-addressing device can be formed by a shift register including an output row that presents the signal Sn as an output. Output stage 51 may include an output transistor T31 for the output stage, which transmits a pulse of the clock signal at output Sn. The gate of output transistor T31 may be connected to an internal node of the stage of the row-addressing device, its source may be connected to output Sn, and its drain may receive a signal from a third clock CLK3. A boost capacitor C21 for the output stage may be connected between the gate and source of output transistor T31 for the output stage. A first control transistor T11 for the output stage is capable of pre-charging the gate of output transistor T31 for the output stage. The source of the first control transistor T11 for the output stage is therefore connected to the gate of output transistor T31 for the output stage. The gate and drain of the first control transistor T11 for the output stage are controlled by the active output Out(n) of the input stage 50 of stage n of the addressing device.

[0062] The second control transistor T21 for the output stage is capable of discharging the gate of the output transistor T31 for the output stage. The drain of the second control transistor T21 for the output stage is therefore connected to the gate of the output transistor T31 for the output stage. The compensation capacitor C11 for the output stage can advantageously be positioned between the signals from the fourth clock CLK4, which is out of phase with the signal from the third clock CLK3. The third clock CLK3 and the fourth clock CLK4 are characterized in that their duty cycles can be different, and the sum of their respective high-level periods corresponds to the periods of the first clock CLK1 and the second clock CLK2.

[0063] Advantageously, the discharge transistor T41 for the output stage can be connected to the output Sn of the output stage 51 of the row-addressing device for stage n, transmitting an activation signal for row n. The gate of the discharge transistor T41 for the output stage is connected to the gate of the second control transistor T21 for the output stage; it is also connected to the activation output Out(n+1) of the next stage n+1.

[0064] According to another specific feature of the invention, input stage 50 further includes a reset transistor for input stage TR, the gate of which is controlled by a pulse of a reset signal. The source of the reset transistor for input stage TR can be connected to the source of the second control transistor T20 for input stage. The drain of the reset transistor for input stage TR can be connected to the drain of the second control transistor T20 for input stage.

[0065] Similarly, output stage 51 also includes a reset transistor for output stage TR, the gate of which, as well as the gate of the reset transistor for input stage, are controlled by pulses of a reset signal. The source of the reset transistor for output stage TR can be connected to the source of the second control transistor T21 for output stage and the source of the discharge transistor T41 for output stage, and also to the source of the second control transistor T20 for input stage and the source of the discharge transistor T40 for input stage, respectively. The drain of the reset transistor for output stage TR can be connected to the drain of the second control transistor T21 for input stage.

[0066] Therefore, the reset pulse allows a shutdown state to be applied to each transistor in input stage 50 and output stage 51.

[0067] Furthermore, output stage 51 may include a row reset transistor TL. The row reset transistor TL is controlled by a specific signal via its gate. The drain of the row reset transistor TL is connected to the source of the output transistor T31 for the output stage. The source of the row reset transistor TL may be connected to the sources of transistors T20, T40, T21, and T41. The row reset transistor TL for stage n can force the voltage on row n to a low state. The row reset transistor TL allows control over the voltage on the row, i.e., the output of the output stage relative to the stage, and applies a low-impedance voltage to it, especially during the “dead time”. Specifically, in a typical manner, such as driving an X-ray detector, includes a reset phase, followed by a phase of applying X-rays or an “X-window,” and then a readout phase. During the X-window, the X-rays are converted into electrons in a photodiode; the duration of the X-window is relatively long, typically up to 3.2 seconds, so the row reset transistor TL allows any drift in the matrix array to be avoided.

[0068] Again advantageously, each output stage 51 may include a matrix array reset switch, formed, for example, by a matrix array reset transistor TLON, enabling a complete reset of the matrix array. The matrix array reset transistor TLON can be controlled by a matrix array reset signal applied to its gate and its drain. The source of the matrix array reset transistor TLON can be connected to the source of the output transistor T31 for the output stage. The matrix array reset signal controlling the matrix array reset transistor TLON can be a voltage VGoff or an activation voltage VGon. When the matrix array reset transistor TLON is activated, i.e., when the activation voltage VGon is applied, the activation voltage is subsequently applied to the entire matrix array.

[0069] In practice, a complete reset of the matrix array can be performed for a sufficient duration according to the activation sequence defined by the matrix array reset transistor TLON, and then the row reset transistor TL can be activated so that the row can be set back to the voltage VGoff.

[0070] Figure 6 The settings in a single group are illustrated in the form of a sequence diagram. Figure 5 The operation of the driver module is as described in patent application WO2012 / 152836A1. A single token IN is sent to the gate and drain of the control transistor T10 for the input stage E of the first driver module. Clocks CLK1 and CLK2 are out of phase, with equal proportions of high and low levels. Clocks CLK3 and CLK4 are also out of phase, with a period of half the period of clocks CLK1 and CLK2. The high level duration of clock CLK4 is longer than that of clock CLK3.

[0071] Figure 6 The signal Out(n) for four consecutive rows is also shown. Each signal Out(n) is offset by half a cycle of clock CLK1 relative to the previous signal. The signal Gateline(n) for the same four rows is also shown. A dead time TM is observed between the two high levels of two consecutive signals Gateline. This dead time corresponds to the duration of the high level of clock CLK3. The shortest duration of the high level of clock CLK3 is required to ensure the gate charging of transistor T31. This dead time cannot be eliminated by directly linking the driver modules in a single group.

[0072] Conversely, by distributing the driver modules across multiple groups, the dead time between two consecutive modules in the same group can be masked by using a high level of the Gateline signal from another group for individual pixel readout.

[0073] Figure 7 An example of the operation of detector 12 is illustrated in the form of a timing diagram, which implements as follows: Figure 5 The diagram shows driver modules linked into two groups for individual readout of the detector pixels. For the first group A, there is a token INA and four clocks CLK1A, CLK2A, CLK3A, and CLK4A. Clock CLK1A is out of phase with CLK2A. Clock CLK3A is also out of phase with CLK4A, and its period is half the period of clocks CLK1A and CLK2A. Figure 6 The clocks described in the text are different; the four clocks CLK1A, CLK2A, CLK3A, and CLK4A have the same high and low level shares, respectively.

[0074] exist Figure 7The diagram also shows the token INB and four clocks CLK1B, CLK2B, CLK3B, and CLK4B for group B. The signal for group B is offset by one-quarter of the period of clock CLK1A relative to group A.

[0075] For group A, two signals OutA(1) and OutA(2) and two signals Gateline(1) and Gateline(3) correspond to two consecutive driver modules for group A. Signals Gateline(1) and Gateline(3) enable the driving of rows 1 and 3 of the matrix array. Similarly, for group B, two signals OutB(1) and OutB(2) and two signals Gateline(2) and Gateline(4) correspond to two consecutive driver modules for group B. Signals Gateline(2) and Gateline(4) enable the driving of rows 2 and 4 of the matrix array. In other words, the driver module for group A generates the Gateline signal for the odd-numbered rows of the matrix array, and the driver module for group B generates the Gateline signal for the even-numbered rows of the matrix array.

[0076] The interleaving of the two groups allows for a longer duration of the high level of clock CLK3A. Therefore, charging of the gate of transistor T31 can be ensured without a dead time between consecutive lines. Specifically, the gate of transistor T31 in the driver module of group A is charged while the signal gateline of group B is high.

[0077] Figure 8 Another operational example of detector 12 is illustrated in the form of a timing diagram. Detector 12 is implemented as follows: Figure 5 The driver modules shown are still linked into two groups, this time for the common readout of pixels in consecutive rows. In other words, consecutive even-numbered rows and odd-numbered rows are read out simultaneously. This is achieved using... Figure 8 In the described operation, token INA and token INB are sent simultaneously. Similarly, clocks CLK1A, CLK2A, CLK3A, and CLK4A are sent simultaneously with their corresponding clocks CLK1B, CLK2B, CLK3B, and CLK4B. Therefore, signals OutA(1) and OutA(2), OutA(3) and OutA(4), Gateline(1) and Gateline(2), and Gateline(3) and Gateline(4) are simultaneous.

[0078] Figure 8 The operation is similar to Figure 6The operation has a dead time TM between signals Gateline(2) and Gateline(3). To limit the duration of this dead time, the duration of the high level of clocks CLK3A and CLK3B is shorter than the duration of the low level of these same clocks.

[0079] The detector 12, equipped with multiple sets of driver modules linked to each other, allows for the selection of various operating modes as needed, particularly for individual readout of pixels in the matrix array, while providing the possibility of eliminating any dead time between two readouts from two consecutive rows of the matrix array. The detector 12 also enables the grouping of signals originating from multiple pixels together for co-readout.

[0080] Two operational examples are given for reading out the matrix array of pixel P. Figure 1 In the diagram, row conductor L is used to drive the transistor T(i,j) to turn off. This transistor is used for both reading out and resetting individual pixels P(i,j). For reading out and resetting, pixels can be driven in the same or different ways, such as individual reading out and collective resetting.

Claims

1. A matrix array detector, the matrix array detector comprising: An array (10) of pixels (P), the pixels being sensitive to physical effects and arranged in a matrix along the rows and columns of pixels, each pixel (P) generating a signal according to the physical effects, the rows of pixels being physically ordered; Row conductors (L), each row conductor allows driving one row of pixels (P); Driver modules (SR_A, SR_B), each associated with a row conductor (L), each driver module transmits a selection signal (Out_A, Out_B; Gateline) to one of the row conductors (L). These driver modules are distributed in multiple groups, which are interleaved according to the order of the rows of pixels. The driver modules (SR_A, SR_B) of each group (A, B) are linked to each other in the physical order of the rows associated with the driver module group in question, and the linking of each driver module group is independent of the linking of one or more other driver module groups. Furthermore, the matrix array detector also includes a module (30) for generating multiple tokens (INA, INB), each token being passed to the input (In_A(N), In_B(N)) of the first driver module (SR_A(N)) of each driver module group (A, B). In each group of driver modules, the output (Out_A(n), Out_B(n)) of each module is connected to the input (In_A(n+1), In_B(n+1)) of the module with the higher sequence number. The driver modules in each group (A, B) are ordered according to the order of pixel rows, the conductor of which is transmitted by the driver module in question to the selection signal. The tokens (INA, INB) can be issued simultaneously to allow reading by pixel (P) group; and can be issued alternately to allow reading the pixel (P) individually.

2. The matrix array detector according to claim 1, wherein, The pixel (P) and the driver modules (SR_A, SR_B) are manufactured on the same substrate (14), which is based on either n-type thin-film transistors only or p-type thin-film transistors only.

3. A method using a matrix array detector according to claim 1 or 2, wherein, The driver module (16) belonging to different groups (A, B) and connected to the continuous row conductor (L) can receive simultaneous control signals to drive the continuous row simultaneously, or receive alternating control signals to drive the continuous row separately.

Images