Semiconductor structure forming method, online detection method and test structure

Abstract

A method for forming a semiconductor structure, an online detection method and a test structure, wherein the online detection method comprises: detecting the film thickness of a buffer film on a test structure area; judging whether the material of a precursor film on a chip area remains according to the film thickness of the buffer film on the test structure area, thereby reducing the loss of wafer manufacturing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure, an online detection method and a test structure. Background Art

[0002] In the current semiconductor manufacturing process, it is a widely used process to form an opening in an interlayer dielectric layer using an etching process, and then form a conductive structure in the opening for electrical connection between semiconductor devices.

[0003] In order to reduce the contact resistance, metal (precursor layer) is usually deposited on the surface of the substrate and the surface of the gate structure before forming the interlayer dielectric layer, and the precursor layer contacts the substrate surface where the conductive structure is located and the top surface of the gate structure. Then, a rapid annealing process is performed to react the precursor layer with the contacted substrate and gate to form metal silicide, and remove the unreacted precursor layer.

[0004] When the unreacted deposited metal (precursor layer) is not completely removed and remains on the sidewall surface of the gate structure, since the deposited metal usually has strong conductivity, breakdown is likely to occur between the conductive structure and the adjacent gate during the operation of the semiconductor device (such as Figure 1 As shown), resulting in a bridge between the conductive structure and the adjacent gate. Figure 1 ), causing the device to short-circuit.

[0005] In the prior art, the residual unreacted deposited metal is usually monitored during the wafer acceptance test (WAT) and yield test (CP Test) stages. However, the wafer acceptance test and yield test are relatively delayed in time, making it difficult to detect unqualified residual conditions in time during the wafer manufacturing process, resulting in greater losses in wafer manufacturing. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure, an online detection method and a test structure, so as to realize online detection of the residual condition of the precursor film and reduce the loss in wafer manufacturing.

[0007] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a chip area, and a test structure area located on a cutting path of the substrate, the chip area having a gate structure, the gate structure comprising a gate oxide layer, a gate located on the gate oxide layer, and a gate sidewall located on the gate sidewall; forming a precursor film on the surface of the gate structure, the surface of the chip area and the surface of the test structure area, the precursor film containing a metal element, the precursor film being in contact with the top surface of the gate, a partial surface of the chip area, and a surface of the test structure area; after forming the precursor film, performing a first annealing treatment so that the materials on the top surface of the gate, the partial surface of the chip area, and the surface of the test structure area that are in contact with the precursor film react with the precursor film to form a contact layer; after forming the contact layer, removing the unreacted precursor film; after removing the unreacted precursor film, forming a buffer film on the surface of the gate structure, the surface of the chip area and the surface of the test structure area.

[0008] Optionally, the method further includes: performing a second annealing treatment after removing the unreacted precursor film and before forming the buffer film, wherein the temperature of the second annealing treatment is higher than the temperature of the first annealing treatment.

[0009] Optionally, the gate structure has a source-drain structure in the chip area on at least one side along the first direction, and a portion of the surface of the chip area in contact with the precursor layer includes the surface of the source-drain structure. The first direction is perpendicular to the extension direction of the gate structure, and during the first annealing treatment, the precursor film reacts with the material on the surface of the source-drain structure to form the contact layer.

[0010] Optionally, it also includes: before forming the precursor film, forming a contact barrier layer on the surface of the substrate and the surface of the gate structure, and the contact barrier layer exposes the top surface of the gate in contact with the precursor film, a partial surface of the chip area, and the surface of the test structure area.

[0011] Optionally, the buffer film includes a lower buffer film and an upper buffer film located on the surface of the lower buffer film.

[0012] Optionally, the material of the lower buffer film includes SiN, and the material of the upper buffer film includes SiON.

[0013] Optionally, the material of the precursor film includes NiPt.

[0014] Optionally, the material of the precursor film also includes TiN.

[0015] Optionally, the material of the contact layer includes metal silicide.

[0016] Correspondingly, the technical solution of the present invention also provides a method for online detection of a semiconductor structure formed by the above-mentioned semiconductor structure formation method, including: detecting the film thickness of the buffer film on the test structure area; and judging whether the material of the precursor film on the chip area remains based on the film thickness of the buffer film on the test structure area.

[0017] Optionally, the method for judging whether material of the precursor film on the chip area remains based on the film thickness of the buffer film on the test structure area includes: obtaining a monitoring film thickness deviation based on the film thickness of the buffer film on the test structure area and a preset film thickness; judging whether material of the precursor film on the chip area remains based on the monitoring film thickness deviation; judging that there is no residue of material of the precursor film on the chip area when the monitoring film thickness deviation is within a first preset deviation range; and judging that there is residue of material of the precursor film on the chip area when the monitoring film thickness deviation exceeds the first preset deviation range.

[0018] Optionally, the first preset deviation range is 0 angstroms to 2.5 angstroms.

[0019] Optionally, the method for detecting the film thickness of the buffer film on the test structure area includes: specifying a plurality of sampling positions on the buffer film on the test structure area; and detecting a plurality of film thicknesses at the plurality of sampling positions.

[0020] Optionally, based on the film thickness of the buffer film on the test structure area and the preset film thickness, the method for obtaining the monitoring film thickness deviation includes: obtaining the initial film thickness deviation corresponding to each sampling position based on the deviation between the film thickness at each sampling position and the preset film thickness; among several initial film thickness deviations corresponding to several sampling positions, obtaining the initial film thickness deviation with the largest deviation as the monitoring film thickness deviation.

[0021] Optionally, based on the film thickness of the buffer film on the test structure area and the preset film thickness, the method for obtaining the monitoring film thickness deviation includes: obtaining the average film thickness based on the several film thicknesses at the several sampling positions; and obtaining the monitoring film thickness deviation based on the deviation between the average film thickness and the preset film thickness.

[0022] Optionally, the method for obtaining the monitoring film thickness deviation according to the film thickness of the buffer film on the test structure area and the preset film thickness includes: obtaining the monitoring film thickness deviation according to the deviation between the film thickness at any sampling position and the preset film thickness.

[0023] Optionally, an optical film thickness measuring device is used to detect the film thickness of the buffer film on the test structure area.

[0024] Correspondingly, the technical solution of the present invention also provides a test structure formed by the above-mentioned semiconductor structure formation method, including: a test structure area located in the cutting path of the substrate, the test structure area having a contact layer, the test structure area exposing the surface of the contact layer; and a buffer film located on the surface of the contact layer in the test structure area.

[0025] Optionally, the buffer film includes a lower buffer film and an upper buffer film located on the surface of the lower buffer film.

[0026] Optionally, the material of the lower buffer film includes SiN, and the material of the upper buffer film includes SiON.

[0027] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0028] In the method for forming a test structure provided by the technical solution of the present invention, a precursor film is formed on the surface of the gate structure, the surface of the chip area and the surface of the test structure area, the precursor film contains a metal element, and the precursor film contacts the top surface of the gate, a part of the surface of the chip area, and the surface of the test structure area; after the precursor film is formed, a first annealing treatment is performed to make the materials of the top surface of the gate, the part of the surface of the chip area, and the surface of the test structure area in contact with the precursor film react with the precursor film to form a contact layer; after the contact layer is formed, the unreacted precursor film is removed; after the unreacted precursor film is removed, a buffer film is formed on the surface of the gate structure, the surface of the chip area and the surface of the test structure area. On the one hand, the surface roughness of the substrate and the gate structure surface under the buffer film when there is a precursor film residue is greater than the roughness when there is no precursor film residue. Therefore, compared with the case where there is no precursor film residue, the buffer film formed when there is a precursor film residue is thinner and the deviation from the preset film thickness is greater. On the other hand, since the process of forming the precursor film and removing the unreacted precursor film is consistent on the chip area and the test structure area, and the process of forming the buffer film is also consistent on the chip area and the test structure area, after removing the unreacted precursor film, the residual situation of the precursor film on the surface of the test structure area is consistent with the residual situation of the precursor film on the surface of the chip area and the surface of the gate structure, and the buffer film formed on the surface of the test structure area and the buffer film formed on the surface of the chip area and the surface of the gate structure are also consistent. Thus, according to the film thickness of the buffer film on the test structure area, the residual situation of the material of the precursor film on the surface of the chip area and the surface of the gate structure can be judged. At the same time, since a buffer film of a planar structure is formed on the surface of the test structure area, the difficulty of online detection of the film thickness of the buffer film on the test structure area is low. Thus, through the contact layer in the test structure area and the buffer film on the test structure area, it is possible to judge the residual situation of the material of the precursor film on the surface of the chip area and the surface of the gate structure with a lower difficulty of online detection, thereby reducing the loss of wafer manufacturing. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of the bridge between the conductive structure and the adjacent gate when breakdown occurs;

[0030] Figures 2 to 9 is a structural schematic diagram of each step in a method for forming a test structure according to an embodiment of the present invention;

[0031] Fig.10 It is a flow chart of an online detection method according to an embodiment of the present invention;

[0032] Fig.11 Schematic diagram of detecting the film thickness of a buffer film on a test structure area in one embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background technology, in the prior art, the residue of unreacted deposited metal (precursor layer) is usually monitored during the wafer acceptance test (WAT) and yield test (CP Test) stages. However, the wafer acceptance test and yield test are relatively delayed in time, making it difficult to detect unqualified residues in time during the wafer manufacturing process, resulting in greater losses in wafer manufacturing.

[0034] In order to solve the above-mentioned technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, an online detection method and a test structure, by detecting the film thickness of the buffer film on the test structure area, and judging whether the material of the precursor film on the chip area in the semiconductor structure formed by the semiconductor structure formation method remains based on the film thickness of the buffer film on the test structure area, thereby reducing the loss of wafer manufacturing.

[0035] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0036] Figures 2 to 9 It is a structural schematic diagram of each step in a method for forming a test structure according to an embodiment of the present invention.

[0037] Please refer to Figure 2 , providing a substrate 100, wherein the substrate 100 includes a chip area A and a test structure area B located on a cutting path (not marked in the figure) of the substrate 100.

[0038] The chip area A is used to form a chip.

[0039] The dicing road surrounds the chip region A. By cutting the dicing road, the chip region A can be separated from the substrate 100 without damaging the chip region A, thereby forming an independent chip.

[0040] The material of the substrate 100 includes semiconductor material.

[0041] Specifically, the material of the substrate 100 in this embodiment includes silicon.

[0042] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0043] In this embodiment, the chip region A has a gate structure 110 , and in a first direction X, the chip region A on at least one side of the gate structure 110 has a source-drain structure 120 . The first direction X is perpendicular to the extension direction of the gate structure 110 .

[0044] In this embodiment, the gate structure 110 includes: a gate oxide layer 111 , a gate 112 located on a surface of the gate oxide layer 111 , and a gate spacer 113 located on a sidewall surface of the gate 112 .

[0045] The material of the gate oxide layer 111 includes silicon oxide, the material of the gate 112 includes polysilicon, and the material of the gate spacer 113 includes a dielectric material.

[0046] The source-drain structure 120 may be a doped region or an epitaxial layer.

[0047] Next, a contact barrier layer (SAB) is formed on the surface of the substrate 100 and the surface of the gate structure 110, wherein the contact barrier layer exposes the top surface of the gate 112, a portion of the surface of the chip area A (including the surface of the source-drain structure 120), and the surface of the test structure area B.

[0048] The contact barrier layer is used to isolate the surface of the area of ​​the substrate 100 where the contact layer is not required to be formed from the precursor layer formed subsequently, so as to prevent the reaction between the material on the surface of the area and the precursor layer, thereby achieving the purpose of not forming a contact layer in the area.

[0049] Thus, by exposing the contact barrier layer on the top surface of the gate 112, part of the surface of the chip region A (including the surface of the source-drain structure 120), and the surface of the test structure region B, on the one hand, the top surface of the gate 112, part of the surface of the chip region A (including the surface of the source-drain structure 120), and the surface of the test structure region B can be brought into contact with a subsequently formed precursor layer to form a contact layer, and at the same time, it can be achieved that a contact layer is not formed in the remaining areas of the substrate 100. For specific steps of forming the contact barrier layer, please refer to Figure 3 to Figure 4 .

[0050] Please refer to Figure 3 An initial contact barrier layer 130 is formed on the surface of the substrate 100 and the surface of the gate structure 110 .

[0051] The initial blocking contact layer 130 is formed by a chemical vapor deposition process.

[0052] Please refer to Figure 4, forming a mask layer (not shown) on the surface of the initial contact barrier layer 130, the mask layer exposing the surface of the initial contact barrier layer 130 on the gate structure 110, part of the chip area A, and the test structure area B; using the mask layer as a mask, etching the initial contact barrier layer 130 until the top surface of the gate 112, part of the surface of the chip area A, and the surface of the test structure area B are exposed, to form a contact barrier layer (not shown).

[0053] In this embodiment, the portion of the surface of the chip region A exposed by the contact barrier layer at least includes the surface of the source-drain structure 120 .

[0054] In this embodiment, the contact barrier layer also exposes the surface of the gate spacer 113 .

[0055] The material of the contact barrier layer is a dielectric material. The material of the mask layer is a photoresist.

[0056] In this embodiment, the process of etching the initial contact barrier layer 130 includes: at least one of a dry etching process and a wet etching process.

[0057] In this embodiment, after the contact barrier layer is formed, the mask layer is removed.

[0058] Please refer to Figure 5 After forming the contact barrier layer, a precursor film 140 is formed on the surface of the gate structure 110, the surface of the chip area A and the surface of the test structure area B, wherein the precursor film 140 contains a metal element and contacts the top surface of the gate 112, a portion of the surface of the chip area A, and the surface of the test structure area B.

[0059] In this embodiment, the portion of the surface of the chip region A in contact with the precursor film 140 at least includes the surface of the source-drain structure 120 .

[0060] The process of forming the precursor film 140 includes: a chemical vapor deposition process, a physical vapor deposition process, an electroplating process or an atomic layer deposition process.

[0061] In this embodiment, the material of the precursor film 140 at least includes NiPt.

[0062] Preferably, the material of the precursor film 140 further includes TiN.

[0063] Please refer to Figure 6 , a first annealing treatment is performed to make the materials on the top surface of the gate 112 , a partial surface of the chip area A, and the surface of the test structure area B that are in contact with the precursor film 140 react with the precursor film 140 to form a contact layer 150 .

[0064] Specifically, during the first annealing process, the precursor film 150 reacts with the material on the surface of the source / drain structure 120 .

[0065] The contact layer 150 is used to reduce contact resistance and improve the conductivity of the subsequently formed conductive structure.

[0066] The material of the contact layer 150 includes metal silicide.

[0067] Specifically, the material of the contact layer 150 includes NiSi.

[0068] Please refer to Figure 7 After forming the contact layer 150 , the unreacted precursor film 140 is removed.

[0069] In this embodiment, the process of removing the unreacted precursor film 140 includes a wet cleaning process.

[0070] The isotropic wet cleaning process can provide a higher etching selectivity ratio for each location, so as to better clean the unreacted precursor film 140 and reduce the material residue of the precursor film 140 .

[0071] It should be noted that, in the actual process of manufacturing the semiconductor structure, the precursor film 140 may have residual materials due to incomplete cleaning.

[0072] Please refer to Figure 8 After removing the unreacted precursor film 140 , a second annealing treatment is performed, and the temperature of the second annealing treatment is higher than the temperature of the first annealing treatment.

[0073] Therefore, after the contact layer 150 is formed by the first annealing treatment, a second annealing treatment at a higher temperature is performed. On the one hand, the material of the contact layer 150 undergoes a phase change, and on the other hand, it is beneficial to improve the interface state performance of the contact layer 150, thereby further reducing the resistance of the contact layer 150, so as to better improve the conductivity of the conductive structure formed subsequently.

[0074] Please refer to Fig. 9 After the second annealing treatment, a buffer film 160 is formed on the surface of the gate structure 110 , the surface of the chip region A and the surface of the test structure region B.

[0075] Since a precursor film 140 is formed on the surface of the gate structure 110, the surface of the chip area A and the surface of the test structure area B, the precursor film 140 contains a metal element, and the precursor film 140 is in contact with the top surface of the gate 112, a portion of the surface of the chip area A, and the surface of the test structure area B, then, a first annealing treatment is performed to make the materials on the top surface of the gate 112, a portion of the surface of the chip area A, and the surface of the test structure area B that are in contact with the precursor film 140 react with the precursor film 140 to form a contact layer 150, and then, the unreacted precursor film 140 is removed, and after removing the unreacted precursor film 140, a buffer film 160 is formed on the surface of the gate structure 110, the surface of the chip area A and the surface of the test structure area B.

[0076] Therefore, on the one hand, the surface roughness of the substrate 100 and the gate structure 110 under the buffer film 160 when there is residue of the material of the precursor film 140 is greater than the roughness when there is no residue. Therefore, compared with the case where there is no residue, the buffer film 160 formed when there is residue of the material of the precursor film 140 is thinner and the deviation from the preset film thickness is larger.

[0077] On the other hand, the processes of forming the precursor film 140, removing the unreacted precursor film 140, and forming the buffer film 160 are consistent on the chip area A and the test structure area B. Therefore, after removing the unreacted precursor film 140, the residual material of the precursor film 140 on the surface of the contact layer 150 of the test structure area B is consistent with the residual material of the precursor film 140 on the surface of the chip area A and the surface of the gate structure 110, and the buffer film 160 formed on the surface of the test structure area B and the buffer film 160 formed on the surface of the chip area A and the surface of the gate structure 110 are also consistent.

[0078] Therefore, the residual material of the precursor film 140 on the surface of the chip region A and the surface of the gate structure 110 can be determined based on the film thickness of the buffer film 160 on the test structure region B. At the same time, since the buffer film 160 of a planar structure is formed on the surface of the test structure region B, the film thickness of the buffer film 160 on the test structure region B is easy to detect online (easy to measure).

[0079] Therefore, through the contact layer 150 and the buffer film 160 of the test structure area B, the residual material of the precursor film 150 on the surface of the chip area A and the surface of the gate structure 110 can be determined with lower online detection difficulty, thereby reducing the loss of wafer manufacturing.

[0080] In other embodiments, the second annealing process is not performed, and the buffer film is directly formed after removing the unreacted precursor film 140 .

[0081] In this embodiment, the process of forming the buffer film 160 includes: a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process.

[0082] Preferably, the buffer film 160 is formed by a chemical vapor deposition process.

[0083] In this embodiment, the buffer film 160 includes a lower buffer film (not shown) and an upper buffer film (not shown) located on the surface of the lower buffer film. The material of the lower buffer film includes SiN, and the material of the upper buffer film includes SiON.

[0084] In this embodiment, after the buffer film is formed, the semiconductor structure is inspected online to determine whether the material of the precursor film 140 on the chip region A remains.

[0085] When residue is determined, the operation of the production line where the semiconductor structure with residue is located is stopped, and the equipment on the production line is inspected and cleaned, etc., thereby, the residue of the precursor film 140 can be discovered in time, so that the residue of the semiconductor structure produced subsequently on the production line can be reduced, thereby reducing the loss of wafer manufacturing.

[0086] When it is determined that there is no residue, a contact hole process (CT) is used to form a conductive structure (not shown) on the surface of the source-drain structure 120 and the top surface of the gate 112. The material of the conductive structure includes tungsten.

[0087] Fig.10 It is a flowchart of an online detection method according to an embodiment of the present invention.

[0088] Accordingly, an embodiment of the present invention further provides a method for online detection of the semiconductor structure. Fig. 9 refer to Fig.10 ,include:

[0089] Step S100, detecting the film thickness of the buffer film on the test structure area;

[0090] Step S200 , judging whether the material of the precursor film on the chip area remains according to the film thickness of the buffer film on the test structure area.

[0091] The following is a detailed description with reference to the accompanying drawings.

[0092] Please refer to Fig.11 , Fig.11 1 is a schematic diagram of detecting the film thickness of the buffer film on the test structure area in one embodiment of the present invention, wherein the film thickness of the buffer film 160 on the test structure area B is detected.

[0093] In this embodiment, the method for detecting the film thickness of the buffer film 160 on the test structure area B includes: specifying a plurality of sampling positions (not shown) on the buffer film 160 on the test structure area B; and detecting a plurality of film thicknesses H at the plurality of sampling positions.

[0094] It should be noted that, for the sake of ease of explanation and understanding, Fig.11 Schematically shows any one of several sampling positions and the film thickness H corresponding to the any one sampling position.

[0095] It should be understood that there is a one-to-one correspondence between the sampling positions and the film thickness H. In addition, in actual application scenarios, technicians can specify the number and specific positions of the sampling positions according to requirements.

[0096] Since the buffer film 160 on the test structure area B is a planar structure, the film thickness H can be easily detected by an optical film thickness measurement device, making online detection more convenient and less difficult.

[0097] Specifically, in this embodiment, the film thickness of the buffer film 160 on the test structure area B includes: a plurality of film thicknesses H corresponding to a plurality of sampling positions one by one.

[0098] In this embodiment, an optical film thickness measuring device is used to detect the film thickness of the buffer film 160 on the test structure area B. Specifically, the optical film thickness measuring device is used to detect the plurality of film thicknesses H.

[0099] Please continue to refer to Fig.11 According to the film thickness of the buffer film 160 on the test structure area B, it is determined whether the material of the precursor film 140 on the chip area A remains.

[0100] Thus, by online detecting the film thickness of the buffer film 160 on the test structure area B, it is possible to determine the residual material of the precursor film 140 on the side wall of the conductive opening 131. At the same time, the film thickness of the buffer film 160 on the test structure area B is easy to detect online (easy to measure). Thus, the loss of wafer manufacturing can be reduced. For the specific principle explanation, please refer to the relevant description in the embodiment of the semiconductor structure formation method mentioned above, which will not be repeated here.

[0101] In this embodiment, the method for judging whether the material of the precursor film 140 on the chip area A remains according to the film thickness of the buffer film 160 on the test structure area B includes: obtaining a monitoring film thickness deviation according to the film thickness of the buffer film 160 on the test structure area B and a preset film thickness; judging whether the material of the precursor film 140 on the chip area A remains according to the monitoring film thickness deviation; judging that there is no residue of the material of the precursor film 140 on the chip area A when the monitoring film thickness deviation is within a first preset deviation range; judging that there is residue of the material of the precursor film 140 on the chip area A when the monitoring film thickness deviation exceeds the first preset deviation range.

[0102] Preferably, the first preset deviation range is 0 angstroms to 2.5 angstroms.

[0103] In this embodiment, according to the film thickness of the buffer film 160 on the test structure area B and the preset film thickness, the method for obtaining the monitoring film thickness deviation includes: obtaining the initial film thickness deviation corresponding to each sampling position according to the deviation between the film thickness H at each sampling position and the preset film thickness; among several initial film thickness deviations corresponding to several sampling positions, obtaining the initial film thickness deviation with the largest deviation as the monitoring film thickness deviation.

[0104] By obtaining the initial film thickness deviation with the largest deviation among the initial film thickness deviations corresponding to the sampling positions as the monitoring film thickness deviation, it is possible to more accurately determine whether the material of the precursor film 140 on the chip region A remains.

[0105] In another embodiment, according to the film thickness of the buffer film 160 on the test structure area B and the preset film thickness, the method for obtaining the monitoring film thickness deviation includes: obtaining the average film thickness according to the film thicknesses H of the plurality of sampling positions; and obtaining the monitoring film thickness deviation according to the deviation between the average film thickness and the preset film thickness. Thus, it is helpful to more accurately judge whether the material of the precursor film 140 on the chip area A is residual.

[0106] In another embodiment, according to the film thickness of the buffer film 160 on the test structure area B and the preset film thickness, the method for obtaining the monitoring film thickness deviation includes: obtaining the monitoring film thickness deviation according to the deviation between the film thickness H at any sampling position and the preset film thickness. Thus, it is helpful to reduce the time of online detection and improve manufacturing efficiency.

[0107] Those skilled in the art should understand that the online detection method provided in this embodiment and the method for forming the semiconductor structure described above are complementary to each other in terms of specific implementation principles and logic. Therefore, the explanation of terms involved in this embodiment can refer to the relevant description in the method for forming the semiconductor structure described above, and will not be repeated here.

[0108] Accordingly, an embodiment of the present invention further provides a test structure formed by the above-mentioned method for forming a semiconductor structure, please continue to refer to Fig. 9 , including: a test structure area B located on a cutting path (not marked in the figure) of a substrate 100, wherein the test structure area B has a contact layer 150, and the test structure area B exposes the surface of the contact layer 150; and a buffer film 160 located on the surface of the contact layer 150 of the test structure area B.

[0109] The test structure is used for online detection to determine whether the material of the precursor film 140 on the chip region A remains.

[0110] The material of the substrate 100 includes a semiconductor material. Specifically, the material of the substrate 100 in this embodiment includes silicon. In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-component semiconductor material composed of group III-V elements, silicon on insulator (SOI) or germanium on insulator (GOI), etc. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0111] In this embodiment, the buffer film 160 includes a lower buffer film (not shown) and an upper buffer film (not shown) located on the surface of the lower buffer film. The material of the lower buffer film includes SiN, and the material of the upper buffer film includes SiON.

[0112] Those skilled in the art should understand that the test structure provided in this embodiment, the method for forming the semiconductor structure, and the online detection method are complementary to each other in terms of specific implementation principles and logic. Therefore, the explanation of terms involved in this embodiment can refer to the relevant descriptions in the method for forming the semiconductor structure and the online detection method, and will not be repeated here.

[0113] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a chip region and a test structure region located on a cutting path of the substrate, the chip region having a gate structure, the gate structure comprising a gate oxide layer, a gate located on the gate oxide layer, and a gate spacer located on a sidewall of the gate; Forming a precursor film on the surface of the gate structure, the surface of the chip area and the surface of the test structure area, wherein the precursor film contains a metal element and is in contact with the top surface of the gate, a portion of the surface of the chip area and the surface of the test structure area; After forming the precursor film, performing a first annealing process to make the materials on the top surface of the gate, a part of the surface of the chip area, and the surface of the test structure area in contact with the precursor film react with the precursor film to form a contact layer; After forming the contact layer, removing the unreacted precursor film; After removing the unreacted precursor film, forming a buffer film on the surface of the gate structure, the surface of the chip area and the surface of the test structure area; The buffer film includes a lower buffer film and an upper buffer film located on the surface of the lower buffer film; the material of the lower buffer film includes SiN, and the material of the upper buffer film includes SiON.

2. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After removing the unreacted precursor film and before forming the buffer film, a second annealing treatment is performed, and the temperature of the second annealing treatment is higher than the temperature of the first annealing treatment.

3. The method for forming a semiconductor structure according to claim 1, wherein: The gate structure has a source-drain structure in the chip area on at least one side along the first direction, and a portion of the surface of the chip area in contact with the precursor layer includes the surface of the source-drain structure. The first direction is perpendicular to the extension direction of the gate structure, and during the first annealing treatment, the precursor film reacts with the material on the surface of the source-drain structure to form the contact layer.

4. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before forming the precursor film, a contact barrier layer is formed on the substrate surface and the gate structure surface, and the contact barrier layer exposes the gate top surface in contact with the precursor film, a partial surface of the chip area, and a surface of the test structure area.

5. The method for forming a semiconductor structure according to claim 1, wherein: The material of the precursor film includes NiPt.

6. The method for forming a semiconductor structure according to claim 5, wherein: The material of the precursor film further includes TiN.

7. The method for forming a semiconductor structure according to claim 1, wherein: The material of the contact layer includes metal silicide.

8. A method for online detection of a semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 7, characterized in that: include: detecting the film thickness of the buffer film on the test structure area; Whether the material of the precursor film on the chip area remains is determined according to the film thickness of the buffer film on the test structure area.

9. The method for online detection according to claim 8, characterized in that: The method for judging whether the material of the precursor film on the chip area remains according to the film thickness of the buffer film on the test structure area includes: obtaining a monitoring film thickness deviation according to the film thickness of the buffer film on the test structure area and a preset film thickness; judging whether the material of the precursor film on the chip area remains according to the monitoring film thickness deviation; judging that there is no residue of the material of the precursor film on the chip area when the monitoring film thickness deviation is within a first preset deviation range; judging that there is residue of the material of the precursor film on the chip area when the monitoring film thickness deviation exceeds the first preset deviation range.

10. The method for online detection according to claim 9, characterized in that: The first preset deviation range is 0 angstroms to 2.5 angstroms.

11. The method for online detection according to claim 9, characterized in that: The method for detecting the film thickness of the buffer film on the test structure area comprises: specifying a plurality of sampling positions on the buffer film on the test structure area; and detecting a plurality of film thicknesses at the plurality of sampling positions.

12. The method for online detection according to claim 11, characterized in that: According to the film thickness of the buffer film on the test structure area and the preset film thickness, the method for obtaining the monitoring film thickness deviation includes: obtaining the initial film thickness deviation corresponding to each sampling position according to the deviation between the film thickness at each sampling position and the preset film thickness; among several initial film thickness deviations corresponding to several sampling positions, obtaining the initial film thickness deviation with the largest deviation as the monitoring film thickness deviation.

13. The online detection method according to claim 11, characterized in that: According to the film thickness of the buffer film on the test structure area and the preset film thickness, the method for obtaining the monitoring film thickness deviation includes: obtaining the average film thickness according to the several film thicknesses at the several sampling positions; and obtaining the monitoring film thickness deviation according to the deviation between the average film thickness and the preset film thickness.

14. The online detection method according to claim 11, characterized in that: According to the film thickness of the buffer film on the test structure area and the preset film thickness, the method for obtaining the monitoring film thickness deviation includes: obtaining the monitoring film thickness deviation according to the deviation between the film thickness at any sampling position and the preset film thickness.

15. The method for online detection according to claim 8, characterized in that: An optical film thickness measuring device is used to detect the film thickness of the buffer film on the test structure area.

16. A test structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 7, characterized in that: include: A test structure area located at a cutting path of the substrate, wherein a contact layer is provided in the test structure area, and the test structure area exposes a surface of the contact layer; A buffer film is located on the surface of the contact layer in the test structure area.

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