Formation method of Nor Flash device structure without CLDD mask

Abstract

A method for forming a Nor Flash device structure that eliminates the need for a CLDD mask includes: providing a substrate, the substrate including a storage region and a peripheral region; forming a storage gate structure on the storage region; implanting first ions into the storage region and the peripheral region to form a lightly doped region; forming a first gate structure on the peripheral region; forming a photoresist layer on the storage region; and using the photoresist layer and the first gate structure as a mask, implanting second ions into the peripheral region and the first gate structure, the second ions having an electrical type opposite to that of the first ions. The method involves directly implanting the first ions into the storage region and the peripheral region; and then, using the photoresist layer and the first gate structure as a mask, when implanting the second ions into the peripheral region, adjusting the dose of the second ions so that the implanted second ions can simultaneously form a first source-drain doping layer on both sides of the first gate structure and neutralize the first ions within the first gate structure. This process requires only a single photoresist mask process, effectively reducing process costs and cycle times.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a Nor Flash device structure without a CLDD mask. Background Art

[0002] NOR flash memory, developed based on Intel's ETOX structure, is a non-volatile memory that retains stored data even after the chip loses power. NOR flash memory is a voltage-controlled device that uses hot electron injection to write data and tunneling to erase data. Its notable feature is its high random read speed. As a non-volatile memory, NOR flash memory offers advantages such as non-volatility, high device density, low power consumption, and electrical rewritability. It is widely used in portable electronic products such as mobile phones, digital cameras, and smart cards.

[0003] The structure of a Flash memory cell is similar to that of a MOS device, with a floating gate and dielectric layer used to store charge. The access of electrons to and from the floating gate causes the device threshold voltage to change, thereby indicating the state of the Flash memory cell. The NorFlash array is connected together by horizontal gates, called word lines. The drains are connected to vertical metal strips, called bit lines, through contact holes. The sources of two adjacent devices are connected together to form a horizontal source line.

[0004] However, existing Nor Flash devices still have many problems during their formation. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a Nor Flash device structure without a CLDD mask, so as to reduce process cost and process cycle.

[0006] To solve the above problems, the present invention provides a method for forming a Nor Flash device structure that eliminates the CLDD mask, comprising: providing a substrate, the substrate comprising a storage area and a peripheral area; forming a plurality of mutually discrete storage gate structures on the storage area, and forming a gate film layer on the peripheral area, the storage gate structure comprising a floating gate layer and a control gate layer located on the floating gate layer; using the plurality of storage gate structures as masks, injecting first ions into the storage area and the peripheral area to form lightly doped regions in the storage area on both sides of the storage gate structure; after forming the lightly doped regions, patterning the gate film layer to form a first gate structure on the peripheral area, the first gate structure having the first ions therein; forming a photoresist layer on the storage area, the photoresist layer covering the plurality of storage gate structures; using the photoresist layer and the first gate structure as masks, injecting second ions into the peripheral area and the first gate structure to form first source-drain doping layers in the peripheral areas on both sides of the first gate structure, the second ions having an electrical type opposite to that of the first ions.

[0007] Optionally, the storage gate structure further includes: a tunneling oxide layer located between the floating gate layer and the substrate.

[0008] Optionally, the storage gate structure further includes: a gate dielectric layer located between the floating gate layer and the control gate layer.

[0009] Optionally, the method for forming the storage gate structure includes: forming a tunneling oxide material film on the storage area; forming a floating gate material film on the tunneling oxide material film; forming a gate dielectric material film on the floating gate material film; forming a control gate material film on the gate dielectric material film; forming a first patterned layer on the control gate material film, the first patterned layer exposing a portion of the top surface of the control gate material film; etching a portion of the control gate material film, the gate dielectric material film, the floating gate material film and the tunneling oxide material film using the first patterned layer as a mask until the top surface of the storage area is exposed to form the storage gate structure; after forming the storage gate structure, removing the first patterned layer.

[0010] Optionally, the floating gate material film and the control gate material film are both made of semiconductor materials.

[0011] Optionally, the semiconductor material includes polysilicon.

[0012] Optionally, the gate dielectric material film is a single-layer structure or a multi-layer structure.

[0013] Optionally, when the gate dielectric material film is a multi-layer structure, the gate dielectric material film includes a first silicon oxide layer located on the floating gate material film, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0014] Optionally, the gate dielectric material film and the control gate material film are also formed on the peripheral region, and the gate film layer includes: the gate dielectric material film located on the peripheral region, and the control gate material film located on the peripheral region; the first ions are also injected into the control gate material film on the peripheral region.

[0015] Optionally, the method for forming a first gate structure on the peripheral region includes: forming a second patterned layer on the substrate, the second patterned layer exposing a portion of the top surface of the control gate material film located on the peripheral region; etching the gate film layer using the second patterned layer as a mask until the top surface of the peripheral region is exposed, thereby forming the first gate structure, and the first gate structure has the first ions therein.

[0016] Optionally, the first ion material is N-type ion; the second ion is P-type ion.

[0017] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0018] In the method for forming a Nor Flash device structure that eliminates the need for a CLDD mask, the present invention employs a method for directly injecting first ions into the storage region and the peripheral region using the plurality of storage gate structures as masks to form lightly doped regions within the storage region on both sides of the storage gate structure. Furthermore, using the photoresist layer and the first gate structure as masks, second ions are injected into the peripheral region. The dosage of the second ions is adjusted so that the injected second ions can simultaneously form a first source / drain doping layer within the peripheral regions on both sides of the first gate structure and neutralize the first ions within the first gate structure, thereby reducing the impact of the first ions on the device structure formed by the first gate structure. This process requires only a single masking process using the photoresist layer, which not only reduces process costs but also shortens the process cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 and Figure 2 The present invention is a schematic structural diagram of each step of a method for forming a Nor Flash device structure without a CLDD mask;

[0020] Figures 3 to 6 1 is a schematic structural diagram of each step of a method for forming a Nor Flash device structure without a CLDD mask in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] As described in the background art, existing Nor Flash devices still have many problems in their manufacturing process, which will be described in detail below with reference to the accompanying drawings.

[0022] Figure 1 and Figure 2 The present invention is a schematic structural diagram of each step of a method for forming a Nor Flash device structure without a CLDD mask.

[0023] Please refer to Figure 1 , providing a substrate 100, wherein the substrate 100 includes a storage area A1 and a peripheral area A2; forming a plurality of mutually discrete storage gate structures 101 on the storage area A1, wherein the storage gate structure 101 includes a floating gate layer and a control gate layer (not shown) located on the floating gate layer; forming a first photoresist layer 102 on the peripheral area A2; using the photoresist layer 102 and the plurality of storage gate structures 101 as masks, first ions are injected into the storage area A2 to form lightly doped regions 103 in the storage area A1 on both sides of the storage gate structure 101.

[0024] Please refer to Figure 2 After forming the lightly doped area 103, a first gate structure 104 is formed on the peripheral area A2; a second photoresist layer 105 is formed on the storage area A1, and the second photoresist layer 105 covers several of the storage gate structures 101; using the second photoresist layer 105 and the first gate structure 104 as masks, second ions are injected into the peripheral area A2, and the electrical type of the second ions is opposite to that of the first ions. The injected second ions are used to form a first source-drain doped layer 106 in the peripheral area A2 on both sides of the first gate structure 104.

[0025] In this embodiment, during the first ion implantation, the peripheral area A2 is covered by the first photoresist layer 102 to prevent the first ions from being implanted into the device layer above the peripheral area A2. The second photoresist layer 105 is then used to cover the plurality of storage gate structures 101, and the second ion implantation is performed in the peripheral area A2 to form the first source / drain doped layer 106. This process utilizes two masking processes, namely, the first photoresist layer 102 and the second photoresist layer 105, which not only increases process cost but also increases process cycle time.

[0026] Based on this, the present invention provides a method for forming a Nor Flash device structure that eliminates the need for a CLDD mask. By directly using several storage gate structures as masks, first ions are implanted into the storage region and peripheral regions to form lightly doped regions within the storage region on both sides of the storage gate structure. Then, using a photoresist layer and the first gate structure as masks, second ions are implanted into the peripheral regions. The dose of the second ions is adjusted so that the implanted second ions simultaneously form first source-drain doped layers within the peripheral regions on both sides of the first gate structure and neutralize the first ions within the first gate structure. This process requires only a single photoresist masking process, which not only reduces process costs but also shortens the process cycle.

[0027] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Figures 3 to 6 1 is a schematic structural diagram of each step of a method for forming a Nor Flash device structure without a CLDD mask in an embodiment of the present invention.

[0029] Please refer to Figure 3 , providing a substrate 200, wherein the substrate 200 includes a storage area A1 and a peripheral area A2.

[0030] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0031] In this embodiment, the storage area A1 is used to form a Nor Flash device, and the peripheral area A2 is used to form a driver device for driving the Nor Flash device.

[0032] Please continue to refer to Figure 3 In this embodiment, the driver device includes a CMOS transistor composed of a PMOS transistor and an NMOS transistor. Therefore, the corresponding peripheral area A2 is respectively a first area I and a second area II. The first area I is used to form a PMOS transistor, and the second area II is used to form an NMOS transistor. Correspondingly, an N-well region (not labeled) is formed in the first area I, and a P-well region (not labeled) is formed in the second area II.

[0033] Please continue to refer to Figure 3 A plurality of separate storage gate structures 201 are formed on the storage area A1, and a gate film layer 202 is formed on the peripheral area A2. The storage gate structure 201 includes a floating gate layer and a control gate layer (not shown) located on the floating gate layer.

[0034] In this embodiment, the memory gate structure 201 further includes: a tunneling oxide layer located between the floating gate layer and the substrate, and a gate dielectric layer (not shown) located between the floating gate layer and the control gate layer.

[0035] In this embodiment, the method for the storage gate structure 201 includes: forming a tunneling oxide material film (not shown) on the storage area A1; forming a floating gate material film (not shown) on the tunneling oxide material film; forming a gate dielectric material film (not shown) on the floating gate material film; forming a control gate material film (not shown) on the gate dielectric material film; forming a first patterned layer (not shown) on the control gate material film, the first patterned layer exposing a portion of the top surface of the control gate material film; etching a portion of the control gate material film, the gate dielectric material film, the floating gate material film and the tunneling oxide material film using the first patterned layer as a mask until the top surface of the storage area A1 is exposed, thereby forming the storage gate structure 201; after forming the storage gate structure 201, removing the first patterned layer.

[0036] In this embodiment, the floating gate material film and the control gate material film are both made of semiconductor materials, specifically, polysilicon.

[0037] In this embodiment, the material of the first patterned layer includes photoresist, and the formation process of the first patterned layer includes a photolithography patterning process; the process of removing the first patterned layer includes a wet stripping process or an ashing process, and the gas of the ashing process is an oxygen-containing gas, such as oxygen or ozone.

[0038] In this embodiment, the gate dielectric material film is a single-layer structure.

[0039] In other embodiments, the gate dielectric material film may also have a multi-layer structure. When the gate dielectric material film has a multi-layer structure, the gate dielectric material film includes: a first silicon oxide layer located on the floating gate material film, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

[0040] The first silicon oxide layer and the second silicon oxide layer in the gate dielectric material film can be well bonded to the base crystal, and the silicon nitride layer in the middle can block the extension of defects (such as pinholes). Therefore, the three-layer structure design can complement the deficiencies.

[0041] In this embodiment, the gate dielectric material film and the control gate material film are also formed on the peripheral area A2, and the gate film layer includes: the gate dielectric material film located on the peripheral area A2, and the control gate material film located on the peripheral area A2.

[0042] It should be noted that, when forming the memory gate structure 201 , the first patterned layer only exposes a portion of the top surface of the control gate material film located on the memory area A1 .

[0043] Please continue to refer to Figure 3 Using the plurality of storage gate structures 201 as masks, first ions are implanted into the storage area A1 and the peripheral area A2 to form lightly doped regions 203 in the storage area A1 on both sides of the storage gate structures 201 .

[0044] In this embodiment, in order to obtain the required drive current and suppress the short channel effect, the Nor Flash device generally adopts a semiconductor substrate and source / drain with a higher concentration doping, thereby generating a high electric field in the depletion region of the source / drain. When the high-voltage input / output device operates in a saturated current state, the charges in the inversion layer are accelerated by the lateral electric field on the channel surface and collide with the lattice to ionize, generating a large number of hot carriers (electron-hole pairs). Hot electrons and hot holes can cross the interface barrier and emit to the gate dielectric layer, forming a hot carrier injection effect (Hot-Carrier Injection, HCl). Hot carriers entering the gate dielectric layer have the following effects: an increase in threshold voltage, a decrease in saturation drive current, and a decrease in carrier mobility; at the same time, hot electrons or hot holes can also be affected by the junction electric field and enter the substrate, forming substrate leakage current. The above results caused by hot carriers will seriously affect the operating characteristics and reliability of the device.

[0045] Therefore, in order to improve the hot carrier injection effect problem, the lightly doped drain (LDD) region 203 is formed for optimization, and the performance of the semiconductor device is improved by reducing the dose of the first ion implantation in the lightly doped region 203 and increasing the implantation energy of the first ion.

[0046] It should be noted that, since no mask is used when injecting the first ions, the first ions are also injected into the control gate material film on the peripheral area A2, so that the first gate structure formed subsequently also contains the first ions.

[0047] In this embodiment, the first ions are N-type ions.

[0048] Please refer to Figure 4 After forming the lightly doped region 203 , the gate film layer 202 is patterned to form a first gate structure 205 on the peripheral region A2 , wherein the first ions are contained in the first gate structure 205 .

[0049] In this embodiment, the method for forming the first gate structure 205 on the peripheral area A2 includes: forming a second patterned layer (not shown) on the substrate 200, the second patterned layer exposing a portion of the top surface of the control gate material film located on the peripheral area A2; etching the gate film layer 202 using the second patterned layer as a mask until the top surface of the peripheral area A2 is exposed, thereby forming the first gate structure 205, and the first gate structure 205 has the first ions therein.

[0050] In this embodiment, the first gate structure 205 is formed on the first region I to form a PMOS transistor.

[0051] In this embodiment, the process of forming the first gate structure 205 further includes forming a second gate structure 206. The second gate structure 206 is located on the second region II and is used to form an NMOS transistor. The NMOS transistor and the PMOS transistor constitute a CMOS transistor, and the CMOS transistor drives the Nor Flash device formed in the storage region.

[0052] Please refer to Figure 5 , a photoresist layer 207 is formed on the storage area A1 , and the photoresist layer 207 covers the plurality of storage gate structures 201 .

[0053] In this embodiment, since subsequent steps require ion implantation of the peripheral area A2 to form a first source-drain doped layer corresponding to the first gate structure 205 and a second source-drain doped layer corresponding to the second gate structure 206, to prevent the memory gate structure 201 from being affected during the ion implantation process, a photoresist layer 207 is formed to cover a portion of the memory gate structure 206 for protection.

[0054] In this embodiment, please continue to refer to Figure 5 After forming the first gate structure 205 , the method further includes: forming a first storage source-drain doping layer 204 in the storage area between adjacent storage gate structures 201 , wherein the ions in the first storage source-drain doping layer 204 are N-type ions.

[0055] In this embodiment, please continue to refer to Figure 5 After forming the first gate structure 205, it also includes: forming a first sidewall (not marked) on both sides of the first gate structure 205; after forming the second gate structure 206, it also includes: forming a second sidewall (not marked) on both sides of the second gate structure 206; and forming a storage sidewall (not marked) on the sidewall of the storage gate structure 201.

[0056] In this embodiment, please continue to refer to Figure 5 Before forming the photoresist layer 207, it also includes: forming a second source-drain doping layer 209 in the peripheral area A2 on both sides of the second gate structure 206, and forming a second storage source-drain doping layer 210 in the storage area outside the storage gate structure 201, and the ions in the second source-drain doping layer 209 and the second storage source-drain doping layer 210 are all N-type ions.

[0057] Please refer to Figure 6 Using the photoresist layer 207 and the first gate structure 205 as masks, second ions are injected into the peripheral area A2 and the first gate structure 205 to form a first source-drain doped layer 208 in the peripheral areas on both sides of the first gate structure 205, and the electrical type of the second ions is opposite to that of the first ions.

[0058] In this embodiment, the second ions are P-type ions.

[0059] In this embodiment, since the first gate structure 205 is used to form a PMOS transistor, and the first ions in the first gate structure 205 are N-type ions, when the first gate structure 205 is doped with N-type ions, it will have a significant impact on the performance of the PMOS transistor. Therefore, it is necessary to adjust the dosage of the second ions to neutralize the first ions in the first gate structure 205, thereby reducing the impact on the performance of the PMOS transistor.

[0060] In this embodiment, first ions are directly implanted into the storage area A1 and the peripheral area A2 using the plurality of storage gate structures 201 as masks, thereby forming lightly doped regions 203 within the storage area A1 on both sides of the storage gate structures 201. Then, second ions are implanted into the peripheral area A2 using the photoresist layer 207 and the first gate structure 205 as masks. The dosage of the second ions is adjusted so that the implanted second ions can simultaneously form first source-drain doped layers 208 within the peripheral areas A2 on both sides of the first gate structure 205 and neutralize the first ions within the first gate structure 205, thereby reducing the impact of the first ions on the device structure formed by the first gate structure 205. This process only requires a single masking process using the photoresist layer, which not only reduces process costs but also shortens the process cycle.

[0061] It should be noted that, since the second gate structure 206 is used to form an NMOS transistor, the photoresist layer 207 also covers the second gate structure 206 .

[0062] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a Nor Flash device structure without a CLDD mask, characterized in that: include: providing a substrate, the substrate comprising a storage area and a peripheral area; forming a plurality of mutually separated storage gate structures on the storage area, and forming a gate film layer on the peripheral area, wherein the storage gate structure includes a floating gate layer and a control gate layer located on the floating gate layer; Using the plurality of storage gate structures as masks, first ions are implanted into the storage area and the peripheral area to form lightly doped regions in the storage area on both sides of the storage gate structure, and the first ions are also implanted into the gate film layer on the peripheral area simultaneously; After forming the lightly doped region, patterning the gate film layer to form a first gate structure on the peripheral region, wherein the first gate structure has the first ions therein, and the first ions may affect the performance of the first gate structure; forming a photoresist layer on the storage area, wherein the photoresist layer covers a plurality of the storage gate structures and exposes the first gate structure; Using the photoresist layer and the first gate structure as masks, second ions are implanted into the peripheral region and the first gate structure to form a first source-drain doped layer in the peripheral regions on both sides of the first gate structure, wherein the electrical type of the second ions is opposite to that of the first ions; The dosage of the second ions is adjusted so that the implanted second ions are also used to neutralize the first ions in the first gate structure, so as to reduce the influence of the first ions on the device structure formed by the first gate structure.

2. The method for forming a Nor Flash device structure without a CLDD mask according to claim 1, wherein: The storage gate structure further includes a tunneling oxide layer located between the floating gate layer and the substrate.

3. The method for forming a Nor Flash device structure without a CLDD mask according to claim 2, wherein: The storage gate structure further includes a gate dielectric layer located between the floating gate layer and the control gate layer.

4. The method for forming a Nor Flash device structure without a CLDD mask according to claim 3, wherein: The method for forming a storage gate structure includes: forming a tunneling oxide material film on the storage area; forming a floating gate material film on the tunneling oxide material film; forming a gate dielectric material film on the floating gate material film; forming a control gate material film on the gate dielectric material film; forming a first patterned layer on the control gate material film, wherein the first patterned layer exposes a portion of the top surface of the control gate material film; etching a portion of the control gate material film, the gate dielectric material film, the floating gate material film and the tunneling oxide material film using the first patterned layer as a mask until the top surface of the storage area is exposed, thereby forming the storage gate structure; and removing the first patterned layer after forming the storage gate structure.

5. The method for forming a Nor Flash device structure without a CLDD mask according to claim 4, wherein: The floating gate material film and the control gate material film are both made of semiconductor materials.

6. The method for forming a Nor Flash device structure without a CLDD mask according to claim 5, wherein: The semiconductor material includes polysilicon.

7. The method for forming a Nor Flash device structure without a CLDD mask according to claim 4, wherein: The gate dielectric material film is a single-layer structure or a multi-layer structure.

8. The method for forming a Nor Flash device structure without a CLDD mask according to claim 7, wherein: When the gate dielectric material film is a multi-layer structure, the gate dielectric material film includes a first silicon oxide layer located on the floating gate material film, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer.

9. The method for forming a Nor Flash device structure without a CLDD mask according to claim 4, wherein: The gate dielectric material film and the control gate material film are also formed on the peripheral area, and the gate film layer includes: the gate dielectric material film located on the peripheral area, and the control gate material film located on the peripheral area; the first ions are also injected into the control gate material film on the peripheral area.

10. The method for forming a Nor Flash device structure without a CLDD mask according to claim 9, wherein: The method for forming a first gate structure on the peripheral area includes: forming a second patterned layer on the substrate, the second patterned layer exposing a portion of the top surface of the control gate material film located on the peripheral area; etching the gate film layer using the second patterned layer as a mask until the top surface of the peripheral area is exposed, thereby forming the first gate structure, and the first gate structure has the first ions.

11. The method for forming a Nor Flash device structure without a CLDD mask according to claim 1, wherein: The first ion material is N-type ion; the second ion material is P-type ion.

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