Vector synthesis structure of a phase shifter

Abstract

The application provides a vector synthesis structure of a phase shifter, comprising: a first vector synthesis branch and a second vector synthesis branch; wherein the first vector synthesis branch comprises: a first tail current source, a first DAC bias circuit and a first gate width control circuit, the first tail current source comprises a plurality of first tail current units with gradually increasing width-length ratios, and the first DAC bias circuit is provided with a plurality of first current mirror bias units in correspondence; the second vector synthesis branch comprises: a second tail current source, a second DAC bias circuit and a second gate width control circuit, the second tail current source comprises a plurality of second tail current units with gradually increasing width-length ratios, and the second DAC bias circuit is provided with a plurality of second current mirror bias units in correspondence; the application can improve the linearity of the active phase shifter while ensuring the phase shift precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of electronic technology, and in particular to a vector synthesis structure of a phase shifter.

BACKGROUND

[0002] A phased array system can improve signal-to-noise ratio and has the functions of beamforming and beam scanning because signals can be superimposed in a certain direction. The importance of a phase shifter, as a key module of the phased array system, is self-evident. According to the position of the phase shifter in the system, the phase shifter can be divided into a local oscillator phase shifter, an intermediate frequency phase shifter, and a radio frequency phase shifter. The existing active phase shifter architecture, as shown in FIG. 1, includes a quadrature generator, a VGA, a vector synthesis unit, and a DAC. As shown in FIG. 2, the existing vector synthesis architecture mainly includes a Gilbert unit, a tail current source biased DAC circuit, and the phase shift can be performed by changing the current ratio of I and Q. Figure 1 Figure 2

[0003] The vector synthesis of the prior art uses the Gilbert structure, so that the MOS tubes M9-M14 all work in the saturation region, and there is a certain Vdsat (saturation drain-source voltage). The voltage margin of the RF differential pair tube is reduced, the swing is reduced, and thus the linearity is poor.

SUMMARY

[0004] The purpose of the present application is to overcome at least one of the above technical problems, and to provide a vector synthesis structure of a phase shifter.

[0005] In order to achieve the above-mentioned purpose, the present application provides a vector synthesis structure of a phase shifter, comprising: a first vector synthesis branch and a second vector synthesis branch; wherein,

[0006] The first vector synthesis branch comprises a first tail current source, a first DAC bias circuit, and a first gate width control circuit. The first tail current source comprises a plurality of first tail current units with gradually increasing width-length ratios. The first DAC bias circuit is correspondingly provided with a plurality of first current mirror bias units.

[0007] The second vector synthesis branch comprises a second tail current source, a second DAC bias circuit, and a second gate width control circuit. The second tail current source comprises a plurality of second tail current units with gradually increasing width-length ratios. The second DAC bias circuit is correspondingly provided with a plurality of second current mirror bias units.

[0008] Preferably, the first gate width control circuit comprises a first MOS tube, a second MOS tube, a third MOS tube, and a fourth MOS tube. The gates of the first MOS tube and the fourth MOS tube are connected and connected with a first input signal. The gates of the second MOS tube and the third MOS tube are connected and connected with a second input signal.​​

[0009] Preferably, the second gate width control circuit comprises a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, and an eighth MOS transistor; the gates of the first MOS transistor and the fourth MOS transistor are connected and connected with a first input signal, and the gates of the second MOS transistor and the third MOS transistor are connected and connected with a second input signal.

[0010] Preferably, each of the first tail current units comprises a first one MOS transistor, a first two MOS transistor, and a first three MOS transistor, wherein the gates of the first one MOS transistor and the first two MOS transistor are connected to the first port of the first DAC bias circuit through a first switch and a second switch respectively, the sources of the first one MOS transistor and the first two MOS transistor are connected and connected to the drain of the first three MOS transistor, the gate of the first three MOS transistor is connected to the second port of the first DAC bias circuit, and the source of the first three MOS transistor is grounded.

[0011] Preferably, each of the second tail current units comprises a second one MOS transistor, a second two MOS transistor, and a second three MOS transistor, wherein the gates of the second one MOS transistor and the second two MOS transistor are connected to the third port of the second DAC bias circuit through a third switch and a fourth switch respectively, the sources of the second one MOS transistor and the second two MOS transistor are connected and connected to the drain of the second three MOS transistor, the gate of the second three MOS transistor is connected to the fourth port of the second DAC bias circuit, and the source of the second three MOS transistor is grounded.

[0012] Preferably, the width-to-length ratios of the plurality of first tail current units in the first tail current source increase in binary form from to, and the width-to-length ratios of the plurality of second tail current units in the second tail current source increase in binary form from to.

[0013] Preferably, each of the first current mirror bias units comprises a plurality of first current steering units and a corresponding number of first current mirror units.

[0014] Each of the second current mirror bias units comprises a plurality of second current steering units and a corresponding number of second current mirror units.

[0015] Preferably, the first current steering unit comprises a fourth one MOS transistor, a fifth one MOS transistor, and a fifth one switch, the gate of the fourth one MOS transistor is connected to a bias current, the source of the fourth one MOS transistor is connected to a power supply, the drain of the fourth one MOS transistor is connected to the source of the fifth one MOS transistor, the gate of the fifth one MOS transistor is connected to the fifth one switch, and the drain of the fifth one switch is connected to a port of the first current mirror unit.

[0016] Preferably, the second current steering unit comprises a fourth MOS transistor, a sixth MOS transistor and a seventh switch, a gate of the fourth MOS transistor is connected with a bias current, a source of the fourth MOS transistor is connected with a power supply, a drain of the fourth MOS transistor is connected with a source of the sixth MOS transistor, a gate of the seventh MOS transistor is connected with the seventh switch, and a drain of the seventh switch is connected with a port of the second current mirror unit.

[0017] Preferably, the first current mirror unit comprises an eighth fifth MOS transistor, an eighth sixth MOS transistor, an eighth seventh MOS transistor and an eighth eighth MOS transistor, drains of the eighth fifth MOS transistor and the eighth sixth MOS transistor are connected with a port Ibias2 respectively, gates of the eighth fifth MOS transistor and the eighth sixth MOS transistor are connected, drains of the eighth seventh MOS transistor and the eighth eighth MOS transistor are connected with sources of the eighth fifth MOS transistor and the eighth sixth MOS transistor respectively, gates of the eighth seventh MOS transistor and the eighth eighth MOS transistor are connected and are connected with the port Ibias through control switches respectively; the second current mirror unit has the same structure as the first current mirror unit.

[0018] Compared with the related art, the present application can improve the linearity of the active phase shifter while ensuring the phase shift precision. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without creative labor.

[0020] Figure 1 It is a schematic diagram of the prior art phase shifter architecture;

[0021] Figure 2 It is a schematic diagram of the prior art vector synthesis structure;

[0022] Figure 3 It is a schematic diagram of the quadrature synthesis of the embodiment of the present application;

[0023] Figure 4 It is a schematic diagram of the vector synthesis structure of the embodiment of the present application;

[0024] Figure 5 It is a schematic diagram of the tail current source I of the embodiment of the present application;

[0025] Figure 6 It is a schematic diagram of the tail current source Q of the embodiment of the present application;

[0026] Figure 7 The schematic diagram of the DAC bias circuit of the embodiment of the present application;

[0027] Figure 8 The structure diagram of the current mirror adopted by the embodiment of the present application;

[0028] Figure 9 The structure diagram of a current mirror.

CONCRETE IMPLEMENTATION

[0029] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0030] The synthesis principle of the embodiment is shown in Figure 3 The gain and phase after synthesis are respectively:

[0031]

[0032]

[0033] wherein g mI , g mQ are the transconductances of the tail current source I and the tail current source Q respectively, I ssI , I ssQ are the currents of the tail current source I and the tail current source Q respectively, and R out is the equivalent load impedance.

[0034] It can be known from the equation that the phase will change by changing the current ratio of the tail current source I and the tail current source Q, while the gain will not change by ensuring that the sum of the two currents is unchanged.

[0035] Please refer to Figure 4 , based on the above principle, the embodiment of the present application provides a vector synthesis structure of a phase shifter, comprising: a first vector synthesis branch 100 and a second vector synthesis branch 200.

[0036] The first vector synthesis branch 100 comprises: a first tail current source 110 (tail current source I), a first DAC bias circuit 120, and a first gate width control circuit 130. In combination with Figure 5 , the first tail current source comprises a plurality of first tail current units 111 with gradually increasing width-length ratios, in combination with Figure 7 , the first DAC bias circuit 120 is correspondingly provided with a plurality of first current mirror bias units 121.

[0037] The second vector synthesis branch 200 comprises a second tail current source 210 (micro current source Q), a second DAC bias circuit 220, and a second gate width control circuit 230. In combination Figure 5 As shown, the second tail current source 210 comprises a plurality of second tail current units 211 with gradually increasing width-length ratios. Figure 7 As shown, the second DAC bias circuit 220 is provided with a plurality of second current mirror bias units 221.

[0038] In the embodiment, the first gate width control circuit 130 comprises a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, and a fourth MOS transistor M4. The gates of the first MOS transistor M1 and the fourth MOS transistor M4 are connected and connected with a first input signal Ip. The gates of the second MOS transistor M2 and the third MOS transistor M3 are connected and connected with a second input signal Qn.

[0039] In the embodiment, the second gate width control circuit 230 comprises a fifth MOS transistor M5, a sixth MOS transistor M6, a seventh MOS transistor M7, and an eighth MOS transistor M8. The gates of the first MOS transistor M1 and the fourth MOS transistor M4 are connected and connected with a first input signal Ip. The gates of the second MOS transistor M2 and the third MOS transistor M3 are connected and connected with a second input signal Qn.

[0040] In the embodiment, as Figure 5 As shown, each of the first tail current units 111 comprises a first one MOS transistor MIn1, a first two MOS transistor MIn2, and a first three MOS transistor MIn3. The gates of the first one MOS transistor MIn1 and the first two MOS transistor MIn2 are respectively connected to a first port Ibias1 of the first DAC bias circuit through a first switch SIn1 and a second switch SIn2. The sources of the first one MOS transistor MIn1 and the first two MOS transistor MIn2 are connected and connected to the drain of the first three MOS transistor MIn3. The gate of the first three MOS transistor MIn3 is connected to a second port Ibias2 of the first DAC bias circuit. The source of the first three MOS transistor MIn3 is grounded. In the embodiment, n in the reference sign MIn1 represents the first one MOS in the nth first tail current unit. When the first one MOS transistor MIn1 belongs to the first first tail current unit, it is represented as MI11. The above and the following descriptions of the remaining reference signs are similar and will not be repeated.

[0041] In the embodiment, as Figure 6As shown, each of the second tail current units includes: a second MOSFET MQn1, a second MOSFET MQn2, and a second MOSFET MQn3. The gates of the second MOSFET MQn1 and the second MOSFET MQn2 are connected to the third port Qbias1 of the second DAC bias circuit through the third switch SQn1 and the fourth switch SQn2, respectively. The sources of the second MOSFET MQn1 and the second MOSFET MQn2 are connected together and connected to the drain of the second MOSFET MQn3. The gate of the second MOSFET MQn3 is connected to the fourth port Qbias2 of the second DAC bias circuit. The source of the second MOSFET MQn3 is grounded.

[0042] In this embodiment, the aspect ratio of the plurality of first tail current units in the first tail current source is from arrive Increasing in binary form, the aspect ratio of multiple second tail current units in the second tail current source increases from... arrive Incrementing in binary form.

[0043] In this embodiment, as Figure 7 As shown, each of the first current mirror biasing units 120 includes: a plurality of first current rudder units 121 and a corresponding number of first current mirror units 122; each of the second current mirror biasing units 220 includes: a plurality of second current rudder units 221 and a corresponding number of second current mirror units 222.

[0044] In this embodiment, as Figure 7 As shown, the first current steering unit 121 includes: a fourth MOS transistor Mnb, a fifth MOS transistor Min, and a fifth switch SIn. The gate of the fourth MOS transistor Mnb is connected to the bias current bias, the source of the fourth MOS transistor Mnb is connected to the power supply, the drain of the fourth MOS transistor Mnb is connected to the source of the fifth MOS transistor Min, the gate of the fifth MOS transistor is connected to the fifth switch SIn, and the drain of the fifth switch SIn is connected to the second port Ibias2 of the first current mirror unit.

[0045] In this embodiment, as Figure 7As shown, the second current steering unit 221 includes: a fourth MOS transistor Mnb (shared with the first current steering unit 121), a sixth MOS transistor MQn, and a seventh switch SQn. The gate of the fourth MOS transistor Mnb is connected to the bias current bias, the source of the fourth MOS transistor Mnb is connected to the power supply, the drain of the fourth MOS transistor Mnb is connected to the source of the sixth MOS transistor MQn, the gate of the seventh MOS transistor is connected to the seventh switch SQn, and the drain of the seventh switch SQn is connected to the fourth port Qbias2 of the second current mirror unit.

[0046] In this embodiment, the structure of the second current mirror unit 222 is the same as that of the first current mirror unit 122, and will not be described again here.

[0047] In this embodiment, as Figure 8 As shown, the first current mirror unit 122 is described, which specifically includes: an eighth MOSFET MIN1, an eighth MOSFET MIN2, an eighth MOSFET MIN4, and an eighth MOSFET MIN5. The drains of the eighth MOSFETs MIN1 and MIN2 are respectively connected to the second port Ibias2, and the gates of the eighth MOSFETs MIN1 and MIN2 are connected. The drains of the eighth MOSFETs MIN4 and MIN5 are respectively connected to the sources of the eighth MOSFETs MIN1 and MIN2. The gates of the eighth MOSFETs MIN4 and MIN5 are connected and respectively connected to the second port Ibias2 through control switches. The structure of the second current mirror unit is the same as that of the first current mirror unit, and will not be described again here.

[0048] refer to Figure 9 The diagram shown is a schematic of another current mirror unit structure. Figure 9 The minimum drain voltage of M2 is:

[0049] V D2min =V N -V TH =V GS1 +V GS3 -V TH =(V GS1 -V TH )+(V GS3 -V TH )+V TH =2V ov +V TH

[0050] Among them, V ov For overdrive voltage, VTH This is the threshold voltage.

[0051] like Figure 7 As shown, the minimum drain voltage of M6 is:

[0052] V D6min =2V ov

[0053] From the above formula, we can see Figure 8 The output drain potential ratio of M6 Figure 9 The output drain potential of M2 is lower than a threshold voltage. Figure 8 The current mirror unit shown can achieve a larger swing. In this embodiment, the vector synthesis tail current source uses... Figure 8 As shown in the current mirror, the differential pair can achieve a larger voltage swing, thus obtaining better linearity.

[0054] During the phase shift from 0 degrees to 360 degrees, the currents in the tail current sources I and Q are constantly changing. For example, from 0 degrees to 90 degrees, the current in source I gradually decreases while the current in source Q gradually increases. If tail current sources I and Q have a fixed width-to-length ratio, then for the Q path, as the current gradually increases, the MOSFET will enter the linear region, leading to errors in the current mirror and affecting the phase shift accuracy. To solve this problem, this embodiment of the invention uses multiple pairs of tail current sources, and the current mirror bias of the DAC must correspond accordingly, such as... Figure 7 As shown. The aspect ratio is from arrive Incrementing in binary form, if the nth PMOS of the DAC current mirror is turned on, the nth bias of the NMOS current mirror below is also turned on. Because the width-to-length ratio is increasing, the Ibias potential remains unchanged. Correspondingly, the nth tail current source of the RF differential pair is also turned on, and the source potential of the differential pair remains unchanged. The tail current source MOS is always in the saturation region, which ensures the accuracy of the mirror and the precision of the phase shift.

[0055] The above description is merely an embodiment of the present invention. It should be noted that those skilled in the art can make improvements without departing from the inventive concept of the present invention, but these improvements all fall within the protection scope of the present invention.

Claims

1. A vector synthesis structure of a phase shifter, characterized by, The application relates to a vector synthesis circuit. The first vector synthesis branch comprises a first tail current source, a first DAC bias circuit and a first gate width control circuit, the first tail current source comprises a plurality of first tail current units with gradually increasing width-length ratios, and the first DAC bias circuit is provided with a plurality of first current mirror bias units in correspondence. The second vector synthesis branch comprises a second tail current source, a second DAC bias circuit and a second gate width control circuit, the second tail current source comprises a plurality of second tail current units with gradually increasing width-length ratios, and the second DAC bias circuit is provided with a plurality of second current mirror bias units in correspondence. Each first tail current unit comprises a first MOS transistor, a second MOS transistor and a third MOS transistor, the gates of the first MOS transistor and the second MOS transistor are connected to a first port of the first DAC bias circuit through a first switch and a second switch respectively, the sources of the first MOS transistor and the second MOS transistor are connected to the drain of the third MOS transistor, the gate of the third MOS transistor is connected to a second port of the first DAC bias circuit, and the source of the third MOS transistor is grounded. Each second tail current unit comprises a second MOS transistor, a second MOS transistor and a third MOS transistor, the gates of the second MOS transistor and the second MOS transistor are connected to a third port of the second DAC bias circuit through a third switch and a fourth switch respectively, the sources of the second MOS transistor and the second MOS transistor are connected to the drain of the third MOS transistor, the gate of the third MOS transistor is connected to a fourth port of the second DAC bias circuit, and the source of the third MOS transistor is grounded. The first gate width control circuit comprises a first MOS transistor, a second MOS transistor, a third MOS transistor and a fourth MOS transistor, the gates of the first MOS transistor and the fourth MOS transistor are connected to a first input signal, and the gates of the second MOS transistor and the third MOS transistor are connected to a second input signal. The width-to-length ratio of the plurality of first tail current units in the first tail current source is incremented in binary form from to The width-to-length ratio of the plurality of second tail current units in the second tail current source is incremented in binary form from to .

2. The vector combining structure of the phase shifter according to claim 1, wherein The second gate width control circuit comprises a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor, the gates of the fifth MOS transistor and the eighth MOS transistor are connected to the first input signal, and the gates of the sixth MOS transistor and the seventh MOS transistor are connected to the second input signal.

3. The vector combining structure of the phase shifter according to claim 1, wherein Each first current mirror bias unit comprises a plurality of first current steering units and a corresponding number of first current mirror units.

4. The vector combining structure of the phase shifter according to claim 1, wherein Each second current mirror bias unit comprises a plurality of second current steering units and a corresponding number of second current mirror units. ​ 5. The vector combining structure of the phase shifter according to claim 4, wherein The first current steering unit comprises a fourth PMOS, a fifth PMOS and a fifth switch, the gate of the fourth PMOS is connected to a bias current, the source of the fourth PMOS is connected to a power supply, the drain of the fourth PMOS is connected to the source of the fifth PMOS, the gate of the fifth PMOS is connected to the fifth switch, and the drain of the fifth PMOS is connected to the second port of the first current mirror unit.

6. The vector combining structure of the phase shifter according to claim 4, wherein The second current steering unit comprises a fourth PMOS, a sixth PMOS and a seventh switch, the gate of the fourth PMOS is connected to a bias current, the source of the fourth PMOS is connected to a power supply, the drain of the fourth PMOS is connected to the source of the sixth PMOS, the gate of the sixth PMOS is connected to the seventh switch, and the drain of the sixth PMOS is connected to the fourth port of the second current mirror unit.

7. The vector combining structure of the phase shifter according to claim 4, wherein The first current mirror unit comprises an eighth PMOS, a ninth PMOS, an eighth switch and an eighth switch, the drains of the eighth PMOS and the ninth PMOS are connected to the second port of the first current mirror unit, the gates of the eighth PMOS and the ninth PMOS are connected, the drains of the eighth switch and the eighth switch are connected to the sources of the eighth PMOS and the ninth PMOS, the gates of the eighth switch and the eighth switch are connected, and the gates of the eighth switch and the eighth switch are connected to the second port of the first current mirror unit through control switches respectively; the structure of the second current mirror unit is the same as that of the first current mirror unit.

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