Comparator and dynamic current generation circuit for a comparator

Abstract

The present application provides a comparator dynamic current generation circuit and a comparator and an RC oscillator comprising the comparator dynamic current generation circuit, comprising: a current source circuit configured to provide a current to the comparator dynamic current generation circuit; a differential input circuit configured to receive a comparator first input and a comparator second input and generate an output; a dynamic current output circuit configured to receive the output of the differential input circuit as an input and generate a bias current for biasing of the comparator.

Description

Technical Field

[0001] This disclosure generally relates to comparators, and in particular to low-power comparator dynamic current generation circuitry, low-power comparators including such circuitry, and applications of comparators in oscillators. Background Technology

[0002] Oscillators are essential basic units in digital and analog systems. In order to reduce system power consumption, oscillators must not generate too much power. Figure 1 This is a block diagram of an RC oscillator using comparator offset compensation technology. Its main power consumption comes from the comparator and the charging / discharging circuit. Simple analysis shows that the comparator's accuracy determines the oscillator's frequency stability, but maintaining high accuracy requires consuming more current. This necessitates a trade-off between power consumption and frequency stability. Summary of the Invention

[0003] Technical issues

[0004] For comparators themselves and their applications in circuits such as RC oscillators, the accuracy of a comparator corresponds to the performance of the comparator and the circuits that include it, but it also means greater power consumption. Therefore, a more accurate comparator that can operate in a low-power mode is desired.

[0005] Solution

[0006] According to embodiments of this disclosure, a dynamic current generation circuit for a comparator is proposed, comprising: a current source circuit configured to provide current to the comparator dynamic current generation circuit; a differential input circuit configured to receive a first input and a second input of the comparator, and to generate a differential output signal based on the difference between the first input and the second input; and a dynamic current output circuit configured to receive the differential output signal, and to output a first dynamic current when the difference between the first input and the second input is less than a first threshold, and to output a second dynamic current less than the first dynamic current when the difference between the first input and the second input is greater than the first threshold.

[0007] According to embodiments of this disclosure, a dynamic current generation circuit for a comparator is proposed, wherein the differential input circuit includes a first differential input pair and a second differential input pair, the first differential input pair being configured to receive a first input and a second input of the comparator and generate a first differential output signal based on the difference between the first input and the second input, and the second differential input pair being configured to receive the first input and the second input of the comparator and generate a second differential output signal based on the difference between the first input and the second input.

[0008] According to embodiments of this disclosure, a dynamic current generation circuit for a comparator is proposed, wherein the current source circuit includes: a current source, a first transistor, a second transistor, and a third transistor, wherein the current source is connected to the drain of the first transistor and to the gates of the first transistor, the second transistor, and the third transistor, the second transistor being configured to provide current to the first differential input pair, and the third transistor being configured to provide current to the second differential input pair.

[0009] According to embodiments of this disclosure, a dynamic current generation circuit for a comparator is proposed, wherein the first differential input pair includes a fourth transistor and a fifth transistor, wherein a second transistor is connected to the source of the fourth transistor and the fifth transistor, and the gate of the fourth transistor receives the first input of the comparator and the gate of the fifth transistor receives the second input of the comparator.

[0010] According to embodiments of this disclosure, a dynamic current generation circuit for a comparator is proposed, wherein the first differential input pair further includes a sixth transistor and a seventh transistor, wherein the drain of the fourth transistor is connected to the drain and gate of the sixth transistor and outputs to the dynamic current output circuit, and the drain of the fifth transistor is connected to the drain of the seventh transistor and outputs to the dynamic current output circuit, wherein the sources of the sixth transistor and the seventh transistor are grounded.

[0011] According to embodiments of this disclosure, a dynamic current generation circuit for a comparator is provided, wherein the second differential input pair includes a twelfth transistor and a thirteenth transistor, wherein the third transistor is connected to the source of the twelfth transistor and the thirteenth transistor, and the gate of the twelfth transistor receives the first input of the comparator and the gate of the thirteenth transistor receives the second input of the comparator.

[0012] According to embodiments of this disclosure, a dynamic current generation circuit for a comparator is provided, wherein the second differential input pair includes a fourteenth transistor and a fifteenth transistor, wherein the drain of the thirteenth transistor is connected to the drain and gate of the fifteenth transistor and outputs to the dynamic current output circuit, and the drain of the twelfth transistor is connected to the drain and gate of the fourteenth transistor and outputs to the dynamic current output circuit, wherein the sources of the fourteenth transistor and the fifteenth transistor are grounded.

[0013] According to embodiments of this disclosure, a dynamic current generation circuit for a comparator is provided, wherein the dynamic current output circuit includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor, wherein the sources of the eighth transistor and the ninth transistor are connected to the drains of the tenth transistor and the eleventh transistor, and the drains of the eighth transistor and the ninth transistor generate a dynamic current, wherein the sources of the tenth transistor and the eleventh transistor are grounded.

[0014] According to embodiments of this disclosure, a comparator is proposed, the comparator including a dynamic current generation circuit and a comparison circuit as described above, wherein the comparison circuit is configured to receive a first input and a second input of the comparator to output a comparison result for generating an oscillating output, and the comparison circuit is further configured to receive a bias current provided by the dynamic current generation circuit.

[0015] According to embodiments of this disclosure, an RC oscillator is proposed, the RC oscillator including a comparator and an RC oscillation circuit as described above, wherein the RC oscillation circuit includes a first resistor and a switched capacitor network, wherein the first resistor is configured to generate a reference voltage, and wherein the switched capacitor network is configured to generate a first input and a second input of the comparator.

[0016] Technical effect

[0017] This disclosure achieves a low-power comparator by implementing an adaptive bias current to provide a large current when the differential input of the comparator is close to 0 and a small current at other times, thereby maintaining high accuracy at low power consumption and maintaining stable frequency stability in low-power mode in application circuits such as RC oscillators. Attached Figure Description

[0018] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a circuit diagram of an RC oscillator that uses comparator offset compensation technology;

[0020] Figure 2 This is a schematic diagram of a comparator that includes a dynamic current generation circuit.

[0021] Figure 3 This is a circuit diagram for implementing a dynamic current generation circuit used in a comparator.

[0022] Figure 4 Yes, yes Figure 1 The voltage waveform of the RC oscillator and the current waveform of the improved comparator are shown in the figure. Detailed Implementation

[0023] Before proceeding with the detailed description below, it may be advantageous to define certain words and phrases used throughout this patent document. The terms “comprising” and “including” and their derivatives mean including but not limited to. The term “or” is inclusive, meaning and / or. The phrase “associated with” and its derivatives mean including, comprising, interconnecting, containing, contained within, connected or connected to, coupled or coupled to, communicating with, cooperating, intertwining, juxtaposing, proximate, binding or binding to, having, having attributes, having a relationship or being related to, etc. The term “controller” means any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, local or remote. The phrase “at least one,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and that only one item from the list may be required. For example, "at least one of A, B, and C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0024] Definitions of other specific words and phrases are provided throughout this patent document. Those skilled in the art will understand that, in many, if not most, cases, such definitions apply to the prior and future use of the words and phrases thus defined.

[0025] In this patent document, the application combination of transform blocks and the hierarchical division of sub-transform blocks are for illustrative purposes only. Without departing from the scope of this disclosure, the application combination of transform blocks and the hierarchical division of sub-transform blocks can be in different ways.

[0026] The following discussion Figures 1 to 4 The various embodiments used to describe the principles of this disclosure in this patent document are for illustrative purposes only and should not be construed as limiting the scope of this disclosure in any way. Those skilled in the art will understand that the principles of this disclosure can be implemented in any suitably arranged system or device.

[0027] Figure 1 Circuit diagram of an RC oscillator using comparator offset compensation technology.

[0028] exist Figure 1 In this RC oscillator, there is a comparator, a Schmitt trigger, and an RC oscillation circuit that uses comparator offset compensation. The comparator receives the offset-compensated input, obtains a bias current through a current source circuit and a dynamic current generation circuit, and then outputs the result to the Schmitt trigger.

[0029] In the RC oscillation circuit, resistor R and capacitor C are connected in parallel to transistors S3 and S4; capacitor C1 and transistor S5 are connected in parallel to transistor S1 in series; and transistors S1 and S3 are connected together to the positive input terminal of the comparator. Furthermore, capacitor C2 and transistor S6 are connected in parallel to transistor S2 in series; and transistors S2 and S4 are connected together to the negative input terminal of the comparator.

[0030] After considering the comparator's offset voltage and delay, the oscillation period of the oscillator satisfies the following relationship:

[0031] t φ＝1 =RC-CV OS / I+t Delay

[0032] t φ＝0 =RC+CV OS / I+t Delay

[0033] t p =2(RC+t) Delay )

[0034] In the above formula, R represents the resistor that generates the reference voltage, C = C1 = C2 represents the charging and discharging capacitor, and V OS t represents the offset voltage of the comparator. Delay This represents the delay of comparators, Schmitt triggers, etc., and Φ indicates the potential. From the above formula, we can see that V... OS The larger the value, the greater the time difference between Φ=0 and Φ=1, resulting in unstable output frequency of the oscillator.

[0035] When the difference between V1 and V2 is large, the capacitor is charging, and the comparator does not need to determine whether toggles, so the comparator's power consumption can be reduced. However, when the difference is small, meaning the capacitor is almost fully charged, the comparator needs to make a judgment, so the power consumption can be increased, thus reducing the comparator's V1 / V2 power consumption. OS This achieves adaptive biasing of the comparator current, reducing oscillator power consumption without affecting frequency stability.

[0036] Figure 2 This is a schematic diagram of a comparator circuit that includes a dynamic current generation circuit.

[0037] exist Figure 2According to embodiments of the present disclosure, the comparator circuit includes a comparator, a differential input circuit, a dynamic current output circuit, and a current source circuit, wherein the current source circuit provides current to the differential input circuit, the comparator input is also provided to the differential input circuit, and then the output of the differential input circuit is provided to the dynamic current output circuit to generate an adaptive bias current, which is fed to the comparator.

[0038] Figure 3 This is a circuit diagram for implementing a dynamic current generation circuit used in a comparator.

[0039] exist Figure 3 According to embodiments of this disclosure, a dynamic current generation circuit for a comparator includes: a current source circuit configured to provide current to the comparator dynamic current generation circuit; a differential input circuit configured to receive a first input V1 and a second input V2 of the comparator and generate an output; and a dynamic current output circuit configured to receive the output of the differential input circuit as an input and generate a bias current I. cmp , used for the bias of the comparator.

[0040] According to an embodiment of the present disclosure, the current source circuit includes: a current source I, a first transistor T1, a second transistor T2, and a third transistor T3, wherein the current source I is connected to the source of the first transistor T1 and to the gates of the first transistor T1, the second transistor T2, and the third transistor T3.

[0041] According to embodiments of this disclosure, the differential input circuit includes a first differential input pair and a second differential input pair.

[0042] According to an embodiment of the present disclosure, the first differential input pair includes a fourth transistor T4 and a fifth transistor T5, wherein a second transistor T2 is connected to the source of the fourth transistor T4 and the fifth transistor T5, and the gate of the fourth transistor T4 receives the first input V1 of the comparator and the gate of the fifth transistor T5 receives the second input V2 of the comparator.

[0043] According to an embodiment of the present disclosure, the first differential input pair further includes a sixth transistor T6 and a seventh transistor T7, wherein the drain of the fourth transistor T4 is connected to the drain and gate of the sixth transistor T6 and outputs to the dynamic current output circuit, and the drain of the fifth transistor T5 is connected to the drain of the seventh transistor T7 and outputs to the dynamic current output circuit, wherein the sources of the sixth transistor T6 and the seventh transistor T7 are grounded.

[0044] According to an embodiment of the present disclosure, the second differential input pair includes a twelfth transistor T12 and a thirteenth transistor T13, wherein a third transistor T3 is connected to the source of the twelfth transistor T12 and the thirteenth transistor T13, and the gate of the twelfth transistor T12 receives the first input V1 of the comparator and the gate of the thirteenth transistor T13 receives the second input V2 of the comparator.

[0045] According to an embodiment of this disclosure, the second differential input pair includes: a fourteenth transistor T14 and a fifteenth transistor T15, wherein the drain of the thirteenth transistor T13 is connected to the drain and gate of the fifteenth transistor T15 and outputs to a dynamic current output circuit, and the drain of the twelfth transistor T12 is connected to the drain and gate of the fourteenth transistor T14 and outputs to a dynamic current output circuit, wherein the sources of the fourteenth transistor T14 and the fifteenth transistor T15 are grounded.

[0046] According to an embodiment of this disclosure, the dynamic current output circuit includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11, wherein the sources of the eighth transistor T8 and the ninth transistor T9 are connected to the drains of the tenth transistor T10 and the eleventh transistor T11, and the drains of the eighth transistor T8 and the ninth transistor T9 generate a dynamic current as the output current, wherein the sources of the tenth transistor T10 and the eleventh transistor T11 are grounded.

[0047] According to embodiments of this disclosure, when V1 is much larger than V2, the gate voltages of T8 and T11 are very low, while the gate voltages of T10 and T9 are very high, causing them to enter the linear region. At this time, I... cmp The voltage is very small; as V2 gradually increases to near V1, the gate voltages of T8 and T11 gradually increase, while the gate voltages of T10 and T9 gradually decrease. T8 through T11 gradually reach the saturation region, at which point I... cmp The current gradually increases; when V1 is much smaller than V2, the gate voltages of T10 and T9 are very low, while the gate voltages of T8 and T11 are very high, causing them to enter the linear region. At this time, I... cmp It's also very small.

[0048] Figure 4 Yes, yes Figure 1 The voltage waveform of the RC oscillator and the current waveform of the improved comparator are shown in the figure.

[0049] exist Figure 4 (a), (b), and (c) are Figure 1 The voltage waveform of the RC oscillator is shown in Figure (d), and the current waveform of the improved comparator is shown in Figure (d). As can be seen from the figure above, a large bias current is only provided when the differential input of the comparator is less than the first threshold (e.g., close to 0), that is, the comparator current is only briefly increased near the inversion point of the comparator.

[0050] The text and accompanying drawings are provided by way of example only to aid in understanding this disclosure. They should not be construed as limiting the scope of this disclosure in any way. Although certain embodiments and examples have been provided, it will be apparent to those skilled in the art, based on the content disclosed herein, that changes may be made to the illustrated embodiments and examples without departing from the scope of this disclosure.

[0051] According to embodiments of this disclosure, a comparator dynamic current generation circuit is provided for providing a corresponding bias current based on the input of the comparator, and providing a large bias current only when the differential input of the comparator is less than a first threshold (e.g., close to 0), so that the comparator can operate in a low-power mode over a wide range, while in the application of the comparator in an RC oscillator, the RC oscillator can still maintain high frequency stability with low power consumption.

[0052] Although this disclosure has been described with reference to exemplary embodiments, various changes and modifications may be suggested to those skilled in the art. This disclosure is intended to cover such changes and modifications that fall within the scope of the appended claims.

[0053] Any description in this invention should not be construed as implying that any particular element, step, or function is essential and must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.

Claims

1. A dynamic current generation circuit for a comparator, comprising: A current source circuit is configured to provide current to the comparator dynamic current generation circuit. The differential input circuit is configured to receive a first input and a second input of a comparator, and generate a differential output signal based on the difference between the first input and the second input; A dynamic current output circuit is configured to receive a differential output signal and output a first dynamic current when the difference between the first input and the second input is less than a first threshold, and output a second dynamic current less than the first dynamic current when the difference between the first input and the second input is greater than the first threshold. The differential input circuit includes a first differential input pair and a second differential input pair. The first differential input pair is configured to receive the first input and the second input of the comparator, and generate a first differential output signal based on the difference between the first input and the second input. The second differential input pair is configured to receive the first input and the second input of the comparator, and generate a second differential output signal based on the difference between the first input and the second input. The current source circuit includes: a current source, a first transistor, a second transistor, and a third transistor. The current source is connected to the drain of the first transistor and to the gates of the first transistor, the second transistor, and the third transistor. The second transistor is configured to provide current to the first differential input pair. The third transistor is configured to provide current to the second differential input pair.

2. The dynamic current generating circuit according to claim 1, wherein the first differential input pair comprises: The fourth and fifth transistors, The second transistor is connected to the source of the fourth transistor and the fifth transistor, and the gate of the fourth transistor receives the first input of the comparator and the gate of the fifth transistor receives the second input of the comparator.

3. The dynamic current generating circuit according to claim 2, wherein the first differential input pair further comprises: The sixth and seventh transistors, wherein the drain of the fourth transistor is connected to the drain and gate of the sixth transistor and outputs to the dynamic current output circuit, and the drain of the fifth transistor is connected to the drain of the seventh transistor and outputs to the dynamic current output circuit. The source terminals of the sixth and seventh transistors are grounded.

4. The dynamic current generating circuit according to claim 1, wherein the second differential input pair comprises: The twelfth and thirteenth transistors, The third transistor is connected to the source of the twelfth and thirteenth transistors, and the gate of the twelfth transistor receives the first input of the comparator and the gate of the thirteenth transistor receives the second input of the comparator.

5. The dynamic current generating circuit according to claim 4, wherein the second differential input pair comprises: The fourteenth transistor and the fifteenth transistor, wherein the drain of the thirteenth transistor is connected to the drain and gate of the fifteenth transistor and outputs to the dynamic current output circuit, and the drain of the twelfth transistor is connected to the drain and gate of the fourteenth transistor and outputs to the dynamic current output circuit. The source terminals of the fourteenth and fifteenth transistors are grounded.

6. The dynamic current generating circuit according to claim 1, wherein the dynamic current output circuit comprises: The eighth, ninth, tenth, and eleventh transistors, The sources of the eighth and ninth transistors are connected to the drains of the tenth and eleventh transistors, and dynamic currents are generated at the drains of the eighth and ninth transistors. The sources of the tenth transistor and the eleventh transistor are grounded.

7. A comparator comprising the dynamic current generation circuit and the comparator circuit described in any one of claims 1-6. in, The comparator circuit is configured to receive a first comparator input and a second comparator input to output a comparison result for generating an oscillating output, and the comparator circuit is also configured to receive a bias current provided by the dynamic current generating circuit.

8. An RC oscillator, comprising the comparator as described in claim 7 and an RC oscillation circuit, in, The RC oscillation circuit includes a first resistor and a switched capacitor network. The first resistor is configured to generate a reference voltage. The switched capacitor network is used to generate the first input and the second input of the comparator.

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