Terahertz on-wafer coaxial verification and optimization selection system, method and device

Abstract

The present application is applicable to the field of radio frequency / microwave / millimeter wave testing technology, and provides a terahertz on-wafer coaxial verification and optimization selection system, method and device. The terahertz on-wafer coaxial verification and optimization selection system includes: a vector network analyzer, a first attenuator, a second attenuator, a first power divider and a second power divider; the terahertz on-wafer coaxial verification and optimization selection method includes: through the terahertz on-wafer coaxial verification and optimization selection system, the standard parts are coaxially simulated and verified to determine the combination of standard parts; based on the 16-term error model, the deviation between the measured value and the true value of the standard parts in the combination is calculated; according to the deviation and the measured value of the measured part, the true value of the measured part is obtained. The present application determines the appropriate combination of standard parts by selecting standard parts, and uses the most accurate calibration standard combination while using the minimum number of standard parts, thereby improving the accuracy of calibration and further improving the accuracy of terahertz on-wafer measurement.

Description

Technical Field

[0001] The present application belongs to the field of radio frequency / microwave / millimeter wave testing technology, and in particular, relates to a terahertz on-wafer measurement and calibration method, device and terminal equipment. Background Art

[0002] For on-wafer S-parameter measurements at frequencies of 110 GHz and above, crosstalk errors between probes can become significant because the probe tips need to be brought very close together to reduce unnecessary losses during on-wafer testing at high frequencies, so the edge effects of the probes make the coupling from probe tip to probe tip stronger.

[0003] Most calibration methods used for coaxial, waveguide or low-frequency on-wafer S-parameter measurements, such as the short-open-load-thru (SOLT) calibration method based on a 12-term error model or the thru-reflect-line (TRL) calibration method based on an 8-term error model, do not work well in this case (high-frequency on-wafer measurements) as none of these calibration methods include crosstalk correction.

[0004] The 16-term error model is an error model that takes into account the crosstalk between the measurement ports of the vector network analyzer. Accurately solving the 16-term error model requires at least five sets of two-port calibration standards, and at least one of the five sets of standards should include an asymmetric standard (e.g., load-short circuit) to fully solve all the error terms in the 16-term error model. Increasing the number of calibration standards can eliminate singularities when solving the 16-term error model. However, for calibration on S-parameter wafers, especially at high millimeter-wave frequencies, the use of more additional calibration standards is not advisable because it is very difficult to design and manufacture the standards with sufficient accuracy. Summary of the invention

[0005] In order to overcome the problems existing in the related art, the embodiments of the present application provide a terahertz on-wafer measurement and calibration method, apparatus and terminal device.

[0006] This application is implemented through the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a terahertz on-wafer coaxial verification and optimization selection system, comprising: a vector network analyzer, a first attenuator, a second attenuator, a first power divider, and a second power divider; wherein, the two ends of the first attenuator are respectively connected to the first end of the first power divider and the first port of the vector network analyzer, the second end of the first power divider is connected to the second end of the second power divider through the second attenuator, the first end of the second power divider is connected to the second port of the vector network analyzer, and the third end of the first power divider and the third end of the second power divider are used to connect to the device under test.

[0008] Based on the first aspect, in some possible implementations, the first attenuator is a 3dB attenuator, and the second attenuator is a 20 / 40dB attenuator.

[0009] Based on the first aspect, in some possible implementations, the device under test includes a cascaded unmatched air line and a 10 dB attenuator, and S parameters of the device under test are known and are not equal to 0 or 1.

[0010] In the second aspect, an embodiment of the present application provides a terahertz on-wafer coaxial verification and optimization selection method, including: performing coaxial simulation verification on standard parts through a terahertz on-wafer coaxial verification and optimization selection system to determine a combination of the standard parts; calculating the deviation between the measured value and the true value of the standard parts in the combination based on a 16-term error model; and obtaining the true value of the measured part based on the deviation and the measured value of the measured part.

[0011] Based on the second aspect, in some possible implementations, the coaxial simulation verification is performed on the standard parts through the coaxial simulation system to determine the combination of the standard parts, including: based on the purpose of unifying the crosstalk of the standard parts, ten standard parts with the same length are selected to perform coaxial simulation on the standard parts; the measured values ​​of the standard parts are compared with the true values ​​of the standard parts; at least one asymmetric standard part and one straight-through standard part are selected for combination; the deviation between the measured values ​​and the true values ​​of the standard parts in the combination is compared, and the combination with the smallest deviation is determined as the best combination.

[0012] Based on the second aspect, in some possible implementations, the calculation of the deviation between the measured value and the true value of the standard part in the combination based on the 16-item error model includes: obtaining the error term of the combination based on the 16-item error model; combining the error term with the measured value of the combination, and converting the error term to obtain a cascade parameter; wherein the cascade parameter is used to characterize the deviation between the true value and the measured value of the standard part.

[0013] Based on the second aspect, in some possible implementations, obtaining the true value of the device under test based on the deviation and the measured value of the device under test includes: obtaining the measured value of the device under test through the terahertz on-wafer coaxial verification and optimization selection system; combining the measured value of the device under test with the deviation to obtain the true value of the device under test, wherein the device under test is simulated by cascading an unmatched air line and a 10dB attenuator.

[0014] The above-mentioned terahertz on-wafer coaxial verification and optimization selection method determines the appropriate combination of standard parts through the selection of standard parts. While using the minimum number of standard parts, the highest precision calibration standard combination is used, which improves the accuracy of calibration and further improves the accuracy of terahertz on-wafer measurement.

[0015] In a third aspect, an embodiment of the present application provides a terahertz on-wafer coaxial verification and optimization selection device, comprising: a verification module, which performs coaxial simulation verification on standard parts through a terahertz on-wafer coaxial verification and optimization selection system to determine a combination of the standard parts; a deviation module, which calculates the deviation between the measured value and the true value of the standard parts in the combination based on a 16-term error model; and a calculation module, which obtains the true value of the measured part according to the deviation and the measured value of the measured part.

[0016] In a fourth aspect, an embodiment of the present application provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the terahertz on-wafer coaxial verification and optimization selection method as described in any one of the first aspects is implemented.

[0017] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the terahertz on-wafer coaxial verification and optimization selection method as described in any one of the first aspects is implemented.

[0018] It can be understood that the beneficial effects of the third to fifth aspects mentioned above can be found in the relevant description of the second aspect mentioned above, and will not be repeated here.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 This is a schematic diagram of a terahertz on-wafer coaxial verification and optimization selection system provided by an embodiment of the present application;

[0022] Figure 2 This is a schematic diagram of a terahertz on-wafer coaxial verification and optimization selection system provided by an embodiment of the present application;

[0023] Figure 3 It is a flow chart of a terahertz on-wafer coaxial verification and optimization selection method provided by an embodiment of the present application;

[0024] Figure 4 is a schematic diagram of the deviation between the reference and measurement results when calibration is performed using a combination of T, LL, OO, OS and OL provided in an embodiment of the present application;

[0025] Figure 5 It is a flowchart of a method for determining a standard part provided in an embodiment of the present application;

[0026] Figure 6 This is a physical diagram of a coaxial measurement system for simulating a terahertz on-wafer system with leakage provided in an embodiment of the present application;

[0027] Figure 7 It is a structural schematic diagram of a terahertz on-wafer coaxial verification and optimization selection device provided in one embodiment of the present application;

[0028] Figure 8 It is a structural schematic diagram of a terahertz on-wafer coaxial verification and optimization selection device provided in an embodiment of the present application;

[0029] Fig. 9 It is a schematic diagram of the structure of the terminal device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0031] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0032] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0033] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0034] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0035] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0036] For on-wafer S-parameter measurements at frequencies of 110 GHz and above, crosstalk errors between probes can become significant because the probe tips need to be brought very close together to reduce unnecessary losses during on-wafer testing at high frequencies, so the edge effects of the probes make the coupling from probe tip to probe tip stronger.

[0037] Most calibration methods used for coaxial, waveguide or low-frequency on-wafer S-parameter measurements, such as the short-open-load-thru (SOLT) calibration method based on a 12-term error model or the thru-reflect-line (TRL) calibration method based on an 8-term error model, do not work well in this case (high-frequency on-wafer measurements) as none of these calibration methods include crosstalk correction.

[0038] The 16-term error model is an error model that takes into account the crosstalk between the measurement ports of the vector network analyzer. Accurately solving the 16-term error model requires at least five sets of two-port calibration standards, and at least one of the five sets of standards should include an asymmetric standard (e.g., load-short circuit) to fully solve all the error terms in the 16-term error model. Increasing the number of calibration standards can eliminate singularities when solving the 16-term error model. However, for calibration on S-parameter wafers, especially at high millimeter-wave frequencies, the use of more additional calibration standards is not advisable because it is very difficult to design and manufacture the standards with sufficient accuracy.

[0039] Based on the above problems, a terahertz on-wafer coaxial verification and optimization selection system and method are designed in the embodiment of the present application. Through the terahertz on-wafer coaxial verification and optimization selection system, the standard parts are coaxially simulated and verified to determine the combination of standard parts; based on the 16-term error model, the deviation between the measured value and the true value of the standard parts in the combination is calculated; based on the deviation and the measured value of the measured part, the true value of the measured part is obtained.

[0040] Figure 1 The terahertz on-wafer coaxial verification and optimization selection system provided by the embodiment of the present application is shown. Figure 1 The terahertz on-wafer coaxial verification and optimization selection system may include: a vector network analyzer 10, a first attenuator 11, a second attenuator 12, a first power divider 21 and a second power divider 22. The two ends of the first attenuator 11 are respectively connected to the first end of the first power divider 21 and the first port of the vector network analyzer 10, the second end of the first power divider 21 is connected to the second end of the second power divider 22 through the second attenuator 12, the first end of the second power divider 22 is connected to the second port of the vector network analyzer 310, and the third end of the first power divider 21 and the third end of the second power divider 22 are used to connect to the device under test 30.

[0041] In some scenarios, the first attenuator 11 is a 3 dB attenuator, the second attenuator 12 is a 20 / 40 dB attenuator, the device under test 30 includes a cascaded unmatched air line and a 10 dB attenuator, and the S parameters of the device under test 30 are known and are not equal to 0 or 1.

[0042] The above-mentioned terahertz on-wafer coaxial verification and optimization selection system determines the appropriate combination of standard parts through the selection of standard parts. While using the minimum number of standard parts, it uses the highest precision calibration standard combination, thereby improving the accuracy of calibration and further improving the accuracy of terahertz on-wafer measurement.

[0043] The following takes the terahertz on-wafer coaxial verification and optimization selection system as an example, combined with Figure 1 The above-mentioned terahertz on-wafer coaxial verification and optimization selection system method is described in detail.

[0044] For example, see Figure 2 The terahertz on-wafer coaxial verification and optimization selection system may include: a vector network analyzer, a 3dB attenuator, a 20Db / 40dB attenuator, a first power divider and a second power divider.

[0045] Among them, the two ends of the first attenuator are respectively connected to the first end of the first power divider and the first end of the second power divider, the second end of the first power divider is connected to the first port of the vector network analyzer through the second attenuator, the second end of the second power divider is connected to the second port of the vector network analyzer, and the third end of the first power divider and the third end of the second power divider are used to connect to the device under test.

[0046] In one scenario, the first attenuator is a 3dB attenuator, and the second attenuator is a 20 / 40dB attenuator.

[0047] The first attenuator is Figure 2 The diagonally filled rectangle in the figure can be a 3dB attenuator, which is used to simulate the asymmetry of the real on-chip system; the second attenuator is as shown in FIG. Figure 2 As shown in the diamond-filled rectangle, a 20 / 40 dB attenuator can be used to simulate the crosstalk between two probe heads of a real terahertz on-chip system; the first power divider and the second power divider are two power dividers such as Figure 2 The two rectangular combinations shown in FIG. 1 are used to connect the second attenuator simulating crosstalk, namely the 20 / 40dB attenuator.

[0048] In another scenario, the device under test is Figure 2 As shown in the gray rectangle containing the word "DUT", it may include a cascaded unmatched air line and a 10dB attenuator. The S parameters of the device under test are known and are not equal to 0 or 1.

[0049] For example, the combination of a cascaded unmatched air line and a 10 dB attenuator exhibits a certain mismatch at the input and a fairly good match at the output, thus better simulating the impedance state of the actual on-wafer device than the attenuator alone.

[0050] The following combination Figure 1 and Figure 2 The terahertz on-wafer coaxial verification and optimization selection method of the present application is described in detail.

[0051] Figure 3 FIG. 1 is a schematic flow chart of a terahertz on-wafer coaxial verification and optimization selection method provided by an embodiment of the present application. Figure 3 The detailed description of the terahertz on-wafer coaxial verification and optimization selection method is as follows:

[0052] In step 101, a terahertz on-wafer coaxial verification and optimization selection system is used to perform coaxial simulation verification on standard parts to determine a combination of standard parts.

[0053] Specifically, for the purpose of unifying the crosstalk of standard parts, ten standard parts with the same length are selected, and coaxial simulation is performed on the standard parts; the measured values ​​of the standard parts are compared with the true values ​​of the standard parts; at least one asymmetric standard part and one straight-through standard part are selected for combination; the deviations between the measured values ​​and the true values ​​of the standard parts in the combination are compared, and the combination with the smallest deviation is determined to be the best combination.

[0054] In order to ensure that the crosstalk of each calibration standard is the same during the terahertz on-chip calibration, the following 1 standard with the same length is selected, including four symmetric standards and six asymmetric standards. See Table 1 and Table 2. As shown in Table 1, there are four symmetric standards, including: T (Thru), Short-Short, Open-Open, Load-Load; as shown in Table 2, there are six asymmetric standards, including: Open-Short, Open-Load, Short-Open, Short-Load, Load-Open, Load-Short.

[0055] Table 1 Symmetry standards

[0056] T(Thru) Short-Short Open-Open Load-Load

[0057] Table 2 Asymmetric standards

[0058] Open-Short Open-Load Short-Open Short-Load Load-Open Load-Short

[0059] Among the above 10 standards, if any 5 standards are selected as a combination, there are 252 combinations. In order to eliminate singular values ​​and make the calibration meaningful, at least 1 asymmetric standard and 1 through standard (T) are selected.

[0060] Therefore, there are 126 non-singular combinations using the five criteria, which can be divided into the following four groups for analysis:

[0061] Group 1: 6 combinations of 4 symmetric standards and 1 asymmetric standard (6 out of 6 in total);

[0062] Group 2: 45 combinations of 3 symmetric criteria and 2 asymmetric criteria ((6 choose 2) × (3 choose 1) = (6 x 5 / 2) x 3 = 45);

[0063] Group 3: 60 combinations of 2 symmetric criteria and 3 asymmetric criteria ((6 out of 3) × (3 out of 2) = (6 x 5 x 4 / 2 / 3) x 3 = 60);

[0064] Group 4: 15 combinations including 1 symmetric standard and 4 asymmetric standards (6 out of 4 = 15).

[0065] Comparing the criteria for each of the four groups above, the following results are obtained:

[0066] When calibrating with a combination of T, LL, OO, OS, and OL, the maximum deviation between the reference and measured results exceeds 1 dB, such as Figure 4 Similar calibration combinations include T, LL, SS, SL, LS and through, LL, SS, SO, OS, all three of which are in Group 3 and are not applicable above 20 GHz. Similarly, by using five standards, 17 best combinations were obtained from all 126 calibrations, as shown in Table 1.

[0067] Table 1 Combinations of 17 optimal calibration standards when calibrating using 5 standards

[0068] Serial number Group Calibration standard combination 1 1 T,LL,SS,OO,SL 2 1 T,LL,SS,OO,SO 3 2 T,LL,OO,SO,SL 4 2 T,LL,OO,SL,LO 5 2 T,SS,OO,SO,LS 6 2 T,SS,OO,OS,SL 7 2 T,SS,OO,SL,LS 8 2 T,SS,OO,SL,OL 9 3 T,SS,SO,OS,OL 10 3 T,SS,SO,OS,LO 11 3 T,SS,SO,OL,LO 12 3 T,SS,OS,SL,OL 13 3 T,OO,SO,SL,LS 14 3 T,OO,OS,SL,LS 15 3 T,OO,SL,OL,LO 16 4 T,SO,SL,LS,LO 17 4 T,SO,SL,OL,LO

[0069] In step 102, the deviation between the measured value and the true value of the standard part in the combination is calculated based on the 16-term error model.

[0070] Specifically, based on the 16-term error model, the combined error terms are obtained; the error terms are combined with the combined measured values, and the error terms are transformed to obtain cascade parameters; wherein the cascade parameters are used to characterize the deviation between the true value and the measured value of the standard part

[0071] For example, see Figure 5 , through the terahertz on-wafer coaxial verification and optimization selection system, the true value and measured value of each standard part are obtained; the T matrix of each standard part is solved, and 16 error models are further obtained; through the error model constructed by a certain standard part, the measured value of the measured part under this standard is calculated; the measured value of the measured part under this standard is compared with the true value. The smaller the deviation, the more accurate the error model of this standard is, and the best combination of standard parts is determined.

[0072] The error term can be expressed by a matrix as shown in formula (1):

[0073]

[0074] Let Sa represent the actual S parameter of the DUT or the standard part, and Sm represent the measured value of the S parameter of the DUT or the standard part. Solve the relationship between the two and obtain formulas (2) and (3) as follows:

[0075] S m =E1+E2S a (I-E4S a )-1 E3 (2)

[0076] S a ={E3(S m -E1) -1 E2+E4} -1 (3)

[0077] Since the error term in (3) is nonlinear and difficult to solve, (1) is converted into cascade T parameters as shown in (4). (2) and (3) can be rewritten as (5) and (6), respectively:

[0078]

[0079] S a T1+T2-S m T3S a -S m T4=0 (5)

[0080] S a =(T1-S m T3) -1 (S m T4-T2) (6)

[0081] Among them, e in formula (1) ij Each parameter corresponds to the article Figure 3 The signals of E i represents a 2x2 matrix consisting of 4 corresponding e; S in formula (2) m It represents the original S parameters of the standard component or the device under test (DUT) measured by the vector network analyzer before calibration. In formula (3), S a Indicates the true S parameters of the standard or DUT; during calibration, the S a is known; when measuring the DUT, the S a By DUT's S m and calculated using the 16-term error model obtained through calibration.

[0082] Optionally, due to the existence of singular points when solving formula (5) by four sets of equations, formulas (5) and (6) cannot be solved by only four sets of equations. The singular value decomposition (SVD) algorithm can be used as an approximation method to approach (but not equal to) the exact value of the error term. Therefore, in order to obtain a more ideal result, no less than 5 sets of calibration standards are required. At the same time, using 6 sets of standards does not improve accuracy, and the calibration accuracy will be reduced in most cases when using 7 sets of standards.

[0083] In step 103, the true value of the device under test is obtained according to the deviation and the measured value of the device under test.

[0084] Specifically, the true value of the device under test is obtained according to the deviation and the measured value of the device under test, including: obtaining the measured value of the device under test through a terahertz on-wafer coaxial verification and optimization selection system; combining the measured value of the device under test with the deviation to obtain the true value of the device under test, wherein the device under test is simulated by cascading an unmatched air line and a 10dB attenuator.

[0085] Since the cascaded combination of the unmatched air line and the 10dB attenuator presents a certain mismatch at the input, but a very good match at the output, the S parameters of the combination are accurately known and are not equal to 0 or 1. Therefore, compared with a single attenuator, the combination can better simulate the impedance state of the actual on-wafer device.

[0086] In one scenario, see Figure 6 In some embodiments, based on Figure 1 and Figure 2 In the embodiment shown, the above-mentioned terahertz on-wafer coaxial verification and optimization selection method may be specifically implemented as follows:

[0087] The terahertz on-wafer coaxial verification and optimization selection device consists of a PNA-X network analyzer (Keysight N5245A), two power dividers (Keysight 11667C) and two attenuators. The attenuators are 3dB and 40dB respectively. A 25Ω mismatched transmission line (Keysight's PN 85057-60002) cascaded with a 10dB attenuator is used as the device under test.

[0088] The reference value of the DUT (marked as S) is obtained by measuring with the PNA-X pre-calibrated by SOLT. a -dut). Since this measurement is performed on a coaxial system, it is assumed that there is no crosstalk in the results.

[0089] The measured value of the DUT (marked as S m -dut) Figure 2 The coaxial simulation system shown is measured after calibration with a 16-term error model. This system simulates the terahertz on-wafer measurement environment with crosstalk (leakage). During the measurement, a 20 / 40dB attenuator and two power dividers are used to simulate the crosstalk between the two probe heads of the real terahertz on-wafer system.

[0090] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0091] Corresponding to the terahertz on-wafer coaxial verification and optimization selection method described in the above embodiment, Figure 7A structural block diagram of a terahertz on-wafer coaxial verification and optimization selection device provided in an embodiment of the present application is shown. For ease of explanation, only the parts related to the embodiment of the present application are shown.

[0092] See also Figure 7 The terahertz on-wafer coaxial verification and optimization selection device in the embodiment of the present application may include: a verification module 301, a deviation module 302 and a calculation module 303.

[0093] The verification module 301 is used to perform coaxial simulation verification on the standard parts through the terahertz on-wafer coaxial verification and optimization selection system to determine the combination of standard parts. The deviation module 302 is used to calculate the deviation between the measured value and the true value of the standard parts in the combination based on the 16-term error model. The calculation module 303 is used to obtain the true value of the measured part according to the deviation and the measured value of the measured part.

[0094] In some embodiments, see Figure 8 ,based on Figure 7 In the illustrated embodiment, the verification module 301 may include: a coaxial simulation unit 3011 , a comparison unit 3012 , a combination unit 3013 and a determination unit 3014 .

[0095] The coaxial simulation unit 3011 is used to select ten standard parts with the same length for the purpose of unifying the crosstalk of the standard parts, and perform coaxial simulation on the standard parts. The comparison unit 3012 is used to compare the measured value of the standard parts with the true value of the standard parts. The combination unit 3013 is used to select at least one asymmetric standard part and one straight-through standard part for combination. The determination unit 3014 is used to compare the deviation between the measured value and the true value of the standard parts in the combination, and determine that the combination with the smallest deviation is the best combination.

[0096] In some embodiments, the deviation module 302 can be specifically used to: obtain the error term of the combination based on the 16-term error model; combine the error term with the measured value of the combination, and transform the error term to obtain a cascade parameter; wherein the cascade parameter is used to characterize the deviation between the true value and the measured value of the standard part.

[0097] In some embodiments, the calculation module 303 can be specifically used to: obtain the measurement value of the device under test through the terahertz on-wafer coaxial verification and optimization selection system; combine the measurement value of the device under test with the deviation to obtain the true value of the device under test, wherein the device under test is simulated by cascading an unmatched air line and a 10dB attenuator.

[0098] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0099] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0100] The present application also provides a terminal device, see Fig. 9 The terminal device 500 may include: at least one processor 510, a memory 520, and a computer program stored in the memory 520 and executable on the at least one processor 510. When the processor 510 executes the computer program, the steps in any of the above-mentioned method embodiments are implemented, for example Figure 3 Steps 101 to 103 in the illustrated embodiment. Alternatively, when the processor 510 executes the computer program, the functions of each module / unit in the above-mentioned device embodiments are implemented, for example Figure 7 Functions of modules 301 to 303 are shown.

[0101] Exemplarily, the computer program may be divided into one or more modules / units, one or more modules / units are stored in the memory 520, and executed by the processor 510 to complete the present application. The one or more modules / units may be a series of computer program segments capable of completing specific functions, and the program segments are used to describe the execution process of the computer program in the terminal device 500.

[0102] Those skilled in the art will understand that Fig. 9 It is only an example of a terminal device and does not constitute a limitation on the terminal device. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components, such as input and output devices, network access devices, buses, etc.

[0103] The processor 510 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0104] The memory 520 may be an internal storage unit of the terminal device, or an external storage device of the terminal device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. The memory 520 is used to store the computer program and other programs and data required by the terminal device. The memory 520 may also be used to temporarily store data that has been output or is to be output.

[0105] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0106] The terahertz on-wafer coaxial verification and optimization selection method provided in the embodiment of the present application can be applied to terahertz on-wafer coaxial verification and optimization selection systems, computers, tablet computers, laptops, netbooks, mobile phones and other terminal devices. The embodiment of the present application does not impose any restrictions on the specific type of terminal devices.

[0107] An embodiment of the present application further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the steps in each embodiment of the above-mentioned terahertz on-chip coaxial verification and optimization selection method can be implemented.

[0108] An embodiment of the present application provides a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in each embodiment of the above-mentioned terahertz on-chip coaxial verification and optimization selection method when executing the computer program product.

[0109] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application implements all or part of the processes in the above-mentioned embodiment method, which can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the camera / terminal device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), electric carrier signal, telecommunication signal and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disk. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electric carrier signals and telecommunication signals.

[0110] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0111] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0112] In the embodiments provided in the present application, it should be understood that the disclosed devices / network equipment and methods can be implemented in other ways. For example, the device / network equipment embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0113] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0114] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A terahertz on-wafer coaxial verification and optimization selection method, characterized in that: include: Through the terahertz on-wafer coaxial verification and optimization selection system, the coaxial simulation verification of the standard parts is carried out to determine the combination of the standard parts; Based on the 16-term error model, calculating the deviation between the measured value and the true value of the standard part in the combination; Obtaining a true value of the measured object according to the deviation and the measured value of the measured object; The terahertz on-wafer coaxial verification and optimization selection system is used to perform coaxial simulation verification on standard parts to determine the combination of the standard parts, including: For the purpose of unifying the crosstalk of the standard parts, ten standard parts with the same length are selected and coaxial simulation is performed on the standard parts; comparing the measured value of the standard component with the true value of the standard component; Select at least one asymmetric standard component and one through standard component for combination; The deviations between the measured values ​​and the true values ​​of the standard parts in the combination are compared, and the combination with the smallest deviation is determined as the best combination.

2. The terahertz on-wafer coaxial verification and optimization selection method according to claim 1, characterized in that: The calculating the deviation between the measured value and the true value of the standard part in the combination based on the 16-item error model includes: Based on the 16-item error model, obtaining an error term of the combination; The error term is combined with the measured value of the combination, and the error term is converted to obtain a cascade parameter; wherein the cascade parameter is used to characterize the deviation between the true value and the measured value of the standard component.

3. The terahertz on-wafer coaxial verification and optimization selection method according to claim 1, characterized in that: The obtaining the true value of the device under test according to the deviation and the measured value of the device under test comprises: Obtaining the measurement value of the device under test by using the terahertz on-wafer coaxial verification and optimization selection system; The measured value of the device under test is combined with the deviation to obtain a true value of the device under test, wherein the device under test is simulated by cascading an unmatched air line and a 10 dB attenuator.

4. The terahertz on-wafer coaxial verification and optimization selection method according to claim 1, characterized in that: The terahertz on-wafer coaxial verification and optimization selection system comprises: a vector network analyzer, a first attenuator, a second attenuator, a first power divider and a second power divider; The two ends of the first attenuator are respectively connected to the first end of the first power divider and the first port of the vector network analyzer, the second end of the first power divider is connected to the second end of the second power divider through the second attenuator, the first end of the second power divider is connected to the second port of the vector network analyzer, and the third end of the first power divider and the third end of the second power divider are used to be connected to the device under test.

5. The terahertz on-wafer coaxial verification and optimization selection method according to claim 4, characterized in that: The first attenuator is a 3dB attenuator, and the second attenuator is a 20 / 40dB attenuator.

6. The terahertz on-wafer coaxial verification and optimization selection method according to claim 4, characterized in that: The device under test includes a cascaded unmatched air line and a 10 dB attenuator, and the S parameters of the device under test are known and are not equal to 0 or 1.

7. A terahertz on-wafer coaxial verification and optimization selection device, comprising: A verification module, which performs coaxial simulation verification on standard parts through a terahertz on-wafer coaxial verification and optimization selection system to determine the combination of the standard parts; A deviation module, which calculates the deviation between the measured value and the true value of the standard part in the combination based on a 16-term error model; A calculation module, which obtains a true value of the device under test according to the deviation and the measured value of the device under test; The verification module is specifically used for: selecting ten standard parts with the same length for the purpose of unifying the crosstalk of the standard parts, and performing coaxial simulation on the standard parts; comparing the measured value of the standard parts with the true value of the standard parts; At least one asymmetric standard component and one through standard component are selected for combination; the deviations between the measured values ​​and the true values ​​of the standard components in the combination are compared, and the combination with the smallest deviation is determined as the best combination.

8. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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