Multilayer capacitor and substrate on which the multilayer capacitor is mounted

Abstract

The present disclosure provides a multilayer capacitor and a substrate on which the multilayer capacitor is mounted. The multilayer capacitor includes a capacitor body and a first external electrode and a second external electrode, the capacitor body including a first surface to a sixth surface, and including a dielectric layer, a first internal electrode, and a second internal electrode. The first external electrode includes a first sintered layer and a first plating layer, and the second external electrode includes a second sintered layer and a second plating layer. An insulating layer is provided on the capacitor body to cover an end of a first band portion of the first sintered layer and an end of a second band portion of the second sintered layer, and has a maximum thickness of 10 μm or more. A portion of the first band portion of the first sintered layer is exposed from the insulating layer. A portion of the second band portion of the second sintered layer is exposed from the insulating layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2020-0124224 filed on September 24, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a multilayer capacitor and a substrate on which the multilayer capacitor is mounted. Background Art

[0003] Recently, with the development of electronic technology and IT industrial technology, the demand for passive components with improved performance and reliability is increasing.

[0004] In particular, the electronics industry requires reliability in an environment of strong mechanical stress due to the characteristics of industrial products, and according to this trend, the demand for products having a certain level of warpage strength characteristics, such as multilayer capacitors, is increasing. Summary of the invention

[0005] An aspect of the present disclosure is to provide a multilayer capacitor having improved warpage strength characteristics and a mounting substrate thereof.

[0006] According to one aspect of the present disclosure, a multilayer capacitor includes: a capacitor body including a first surface and a second surface opposite to each other, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other, and the capacitor body includes a dielectric layer, a first inner electrode and a second inner electrode, the dielectric layer is stacked in a first direction connecting the first surface and the second surface and interposed between the first inner electrode and the second inner electrode, the first inner electrode is exposed through the third surface, and the second inner electrode is exposed through the fourth surface; and a first outer electrode and a second outer electrode are respectively arranged on both ends of the capacitor body in a second direction connecting the third surface and the fourth surface, the first outer electrode includes a first sintered layer connected to the first inner electrode and a first plating layer arranged above the first sintered layer, and the second outer electrode includes a second sintered layer connected to the second inner electrode and a second plating layer arranged above the second sintered layer. The insulating layer may have a maximum thickness of 10 μm or more. A portion of the first band portion of the first sintered layer may be exposed from the insulating layer. A portion of the second band portion of the second sintered layer may be exposed from the insulating layer.

[0007] In an embodiment of the present disclosure, the first sintered layer may include a first connection portion and the first band portion, the first connection portion being disposed on the third surface of the capacitor body, the first band portion extending from the first connection portion to a portion of the first surface, a portion of the second surface, a portion of the fifth surface, and a portion of the sixth surface of the capacitor body. The second sintered layer may include a second connection portion and the second band portion, the second connection portion being disposed on the fourth surface of the capacitor body, the second band portion extending from the second connection portion to a portion of the first surface, a portion of the second surface, a portion of the fifth surface, and a portion of the sixth surface of the capacitor body.

[0008] In an embodiment of the present disclosure, the connection between the first connection portion and the first belt portion is defined as a first corner portion in the first sintered layer, and the connection between the second connection portion and the second belt portion is defined as a second corner portion in the second sintered layer. The first corner portion may contact the first plating layer, and the second corner portion may contact the second plating layer.

[0009] In an embodiment of the present disclosure, the first plating layer may be provided on portions of the first connection portion and the first belt portion exposed from the insulating layer, and the second plating layer may be provided on portions of the second connection portion and the second belt portion exposed from the insulating layer.

[0010] In an embodiment of the present disclosure, an end of the first belt portion may be exposed from the first plating layer and may be covered by the insulating layer, an end of the second belt portion may be exposed from the second plating layer and may be covered by the insulating layer. Both ends of the insulating layer may be in contact with the first plating layer and the second plating layer, respectively.

[0011] In an embodiment of the present disclosure, the multilayer capacitor also includes: a first conductive resin layer and a second conductive resin layer, the first conductive resin layer covers the first sintered layer and one end of the insulating layer, the second conductive resin layer covers the other end of the second sintered layer and the insulating layer, and the first plating layer and the second plating layer can be configured to cover the first conductive resin layer and the second conductive resin layer, respectively.

[0012] In an embodiment of the present disclosure, the first conductive resin layer and the second conductive resin layer may each include a conductive metal and a matrix resin.

[0013] In an embodiment of the present disclosure, each of the first conductive resin layer and the second conductive resin layer may include a plurality of metal particles, an intermetallic compound, and a matrix resin.

[0014] According to another aspect of the present disclosure, a mounting substrate for a multilayer capacitor includes: a substrate having a first electrode pad and a second electrode pad on an upper surface; and a multilayer capacitor mounted on the substrate so that a first plating layer and a second plating layer are respectively connected to the first electrode pad and the second electrode pad.

[0015] According to another aspect of the present disclosure, a multilayer capacitor includes: a capacitor body including a first surface and a second surface opposite to each other, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other, and the capacitor body includes a dielectric layer, a first inner electrode and a second inner electrode, the dielectric layer is stacked in a first direction connecting the first surface and the second surface and interposed between the first inner electrode and the second inner electrode, the first inner electrode is exposed through the third surface, and the second inner electrode is exposed through the fourth surface; a first outer electrode and a second outer electrode are respectively arranged on both ends of the capacitor body in a second direction connecting the third surface and the fourth surface, the first outer electrode includes a first sintered layer connected to the first inner electrode and a first plating layer arranged above the first sintered layer, and the second outer electrode includes a second sintered layer connected to the second inner electrode and a second plating layer arranged above the second sintered layer; and an insulating layer is arranged on the capacitor body to cover an end of a first band portion of the first sintered layer and an end of a second band portion of the second sintered layer. A portion of the first band portion of the first sintered layer may be exposed from the insulating layer. A portion of the second band portion of the second sintered layer may be exposed from the insulating layer. A portion of the insulating layer located at a central portion in the second direction may have a thickness greater than a maximum thickness of the first band portion of the first sintered layer or a maximum thickness of the second band portion of the second sintered layer.

[0016] In an embodiment of the present disclosure, a thickness of the portion of the insulating layer located at the central portion in the second direction may be 10 μm or more. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0018] Figure 1 is a schematic perspective view of a multilayer capacitor according to an embodiment of the present disclosure;

[0019] Figure 2 is along Figure 1 A cross-sectional view taken along line II';

[0020] FIG. 3A to FIG. 3B It is shown Figure 1 A plan view of a dielectric layer and a first inner electrode and a second inner electrode of a multilayer capacitor;

[0021] Figure 4 are photographs showing embodiments of the insulating layer;

[0022] Figure 5 is a schematic perspective view of a multilayer capacitor according to another embodiment of the present disclosure;

[0023] Figure 6 is along Figure 5 A cross-sectional view taken along line II-II';

[0024] Figure 7 is a cross-sectional view showing a state in which a multilayer capacitor according to an embodiment of the present disclosure is mounted on a substrate;

[0025] Figure 8 is a schematic diagram schematically illustrating a method for testing warpage strength;

[0026] Fig. 9 is a diagram showing comparison results of a warpage strength test of a conventional multilayer capacitor (without an insulating layer) and a multilayer capacitor according to another embodiment of the present disclosure;

[0027] Fig.10 is a diagram showing comparison results of a warpage strength test of a multilayer capacitor according to thicknesses of insulating layers in another embodiment of the present disclosure; and

[0028] Fig.11 is a SEM photograph showing a cross section of an insulating layer in a multilayer capacitor according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] This disclosure may, however, be embodied in many different forms and should not be construed as limited to the specific embodiments set forth herein.

[0031] Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0032] In the drawings, the shapes and sizes of elements may be exaggerated for clarity.

[0033] Furthermore, in the drawings, elements having the same functions within the same scope of the present invention will be denoted by the same reference numerals.

[0034] Throughout the specification, unless specifically stated otherwise, when a component is referred to as “including” or “comprising”, it means that it may also include other components, rather than excluding other components.

[0035] Hereinafter, when the direction of the capacitor body 110 is defined to clearly explain the embodiments in the present disclosure, X, Y, and Z shown in the drawings represent a length direction, a width direction, and a thickness direction of the capacitor body 110 , respectively.

[0036] Figure 1 is a schematic perspective view of a multilayer capacitor according to an embodiment of the present disclosure, Figure 2 is along Figure 1 A cross-sectional view taken along line II' of FIG. 3A to FIG. 3B It is shown Figure 1 1. A plan view of a dielectric layer and a first internal electrode and a second internal electrode of a multilayer capacitor.

[0037] Reference Figures 1 to 3B , a multilayer capacitor 100 according to the present disclosure includes a capacitor body 110 , a first external electrode 130 , a second external electrode 140 , and an insulating layer 150 .

[0038] The capacitor body 110 is formed by stacking a plurality of dielectric layers 111 and then sintering the plurality of dielectric layers 111 , and may integrate boundaries between adjacent dielectric layers 111 so that it is difficult to confirm the boundaries without using a scanning electron microscope (SEM).

[0039] In this case, the capacitor body 110 may have a substantially hexahedral shape, but the present disclosure is not limited thereto. In addition, the shape and size of the capacitor body 110 and the number of stacked layers of the dielectric layer 111 are not limited to those shown in the drawings of the present embodiment.

[0040] In this embodiment, for the sake of convenience of explanation, the two surfaces of the capacitor body 110 opposite to each other in the Z direction are defined as the first surface 1 and the second surface 2, the two surfaces connected to the first surface 1 and the second surface 2 and opposite to each other in the X direction are defined as the third surface 3 and the fourth surface 4, and the two surfaces connected to the first surface 1 and the second surface 2, connected to the third surface 3 and the fourth surface 4 and opposite to each other in the Y direction are defined as the fifth surface 5 and the sixth surface 6.

[0041] The dielectric layer 111 may include a ceramic material having a high dielectric constant, for example, barium titanate (BaTiO 3 )-based ceramic powder, strontium titanate (SrTiO 3 )-based ceramic powder, etc. However, the present disclosure is not limited thereto as long as sufficient capacitance can be obtained therewith.

[0042] In addition, ceramic additives, organic solvents, plasticizers, binders, dispersants, etc. may be added together with the ceramic powder as materials for forming the dielectric layer 111 .

[0043] As the ceramic additive, for example, transition metal oxides or transition metal carbides, rare earth elements, magnesium (Mg), aluminum (Al), etc. may be used.

[0044] The capacitor body 110 may include an active area serving as a portion contributing to the capacitance formation of the capacitor, and an upper cover area formed above the active area as an upper edge portion 112 and a lower cover area formed below the active area as a lower edge portion 113 .

[0045] The upper cover region and the lower cover region may have the same material and configuration as those of the dielectric layer 111 except that the inner electrodes are not included.

[0046] An upper covering region may be formed by stacking a single dielectric layer or two or more dielectric layers on an upper surface of the active region in the Z direction, and a lower covering region may be formed by stacking a single dielectric layer or two or more dielectric layers on a lower surface of the active region in the Z direction, and the upper covering region and the lower covering region may prevent damage to the internal electrode due to physical or chemical stress.

[0047] The capacitor body 110 includes a first internal electrode 121 and a second internal electrode 122 .

[0048] The first inner electrode 121 and the second inner electrode 122 are electrodes to which voltages of different polarities are applied, and may be respectively formed on surfaces of the dielectric layer 111, and one end of the first inner electrode 121 may be exposed through the third surface 3 of the capacitor body 110 to be connected to the first outer electrode 130, and one end of the second inner electrode 122 may be exposed through the fourth surface 4 of the capacitor body 110 to be connected to the second outer electrode 140.

[0049] In this case, the first and second internal electrodes 121 and 122 may be electrically insulated from each other by the dielectric layer 111 disposed therebetween.

[0050] According to the above configuration, when a predetermined voltage is applied to the first and second external electrodes 130 and 140 , charges are accumulated between the first and second internal electrodes 121 and 122 .

[0051] In this case, the capacitance of the multilayer capacitor 100 is proportional to the overlapping area of ​​the first and second internal electrodes 121 and 122 stacked on each other in the Z direction in the active region.

[0052] In addition, the material used to form the first internal electrode 121 and the second internal electrode 122 is not particularly limited, and can be formed by using, for example, a conductive paste made of a precious metal material (such as platinum (Pt), palladium (Pd), palladium-silver (Pd-Ag) alloy, etc.) and one or more of nickel (Ni) and copper (Cu).

[0053] In this case, the conductive paste may be printed by a screen printing method, a gravure printing method, or the like, but the present disclosure is not limited thereto.

[0054] The first and second external electrodes 130 and 140 are applied with voltages having different polarities, may be disposed on both ends of the capacitor body 110 in the X direction, and may be connected (eg, electrically connected) to exposed portions of the first and second internal electrodes 121 and 122, respectively.

[0055] The first external electrode 130 includes a first sintered layer 131 and a first plating layer 133 .

[0056] The first sintered layer 131 may be formed by applying a paste containing a conductive metal to one end portion of the capacitor body 110 in the X direction and sintering it.

[0057] The conductive metal may be, for example, copper (Cu), silver (Ag), nickel (Ni), and alloys thereof, and the present disclosure is not limited thereto.

[0058] In addition, the first sintered layer 131 may be formed using an atomic layer deposition (ALD) method, a molecular layer deposition (MLD) method, a chemical vapor deposition (CVD) method, a sputtering method, or the like.

[0059] Alternatively, the first sintering layer 131 may be formed by transferring a sheet including a conductive metal onto the capacitor body 110 .

[0060] The first sintered layer 131 may include a first connection portion 131 a and a first band portion 131 b .

[0061] The first connection portion 131 a may be formed on the third surface 3 of the capacitor body 110 and connected to an exposed portion of the first internal electrode 121 .

[0062] The first band portion 131 b may extend from the first connection portion 131 a to a portion of the first surface 1 , a portion of the second surface 2 , a portion of the fifth surface 5 , and a portion of the sixth surface 6 of the capacitor body 110 .

[0063] The first plating layer 133 may be disposed on the first sintered layer 131 , and may include a third connection portion 133 a and a third band portion 133 b .

[0064] The third connection portion 133 a may be formed on the first connection portion 131 a of the first sintered layer 131 , and the third band portion 133 b may extend from the third connection portion 133 a to the first band portion 131 b of the first sintered layer 131 .

[0065] The first plating layer 133 may be a Ni plating layer or a Sn plating layer, and may be formed to have a structure in which a Ni plating layer and a Sn plating layer are sequentially formed on the first sintering layer 131. If necessary, the first plating layer 133 may include a plurality of Ni plating layers and / or a plurality of Sn plating layers. However, the present disclosure is not limited thereto.

[0066] The second external electrode 140 may include a second sintering layer 141 and a second plating layer 143 .

[0067] The second sintering layer 141 may be formed by applying a paste containing a conductive metal to the other end portion of the capacitor body 110 in the X direction and sintering it.

[0068] The conductive metal may be, for example, copper (Cu), silver (Ag), nickel (Ni), and alloys thereof, and the present disclosure is not limited thereto.

[0069] In addition, the second sintered layer 141 may be formed using an atomic layer deposition (ALD) method, a molecular layer deposition (MLD) method, a chemical vapor deposition (CVD) method, a sputtering method, or the like.

[0070] Alternatively, the second sintering layer 141 may be formed by transferring a sheet including a conductive metal onto the capacitor body 110 .

[0071] The second sintered layer 141 may include a second connection portion 141 a and a second belt portion 141 b .

[0072] The second connection portion 141 a may be formed on the fourth surface 4 of the capacitor body 110 and connected to an exposed portion of the second internal electrode 122 .

[0073] The second band portion 141 b may extend from the second connection portion 141 a to a portion of the first surface 1 , a portion of the second surface 2 , a portion of the fifth surface 5 , and a portion of the sixth surface 6 of the capacitor body 110 .

[0074] The second plating layer 143 may be disposed on the second sintered layer 141 , and may include a fourth connection portion 143 a and a fourth band portion 143 b .

[0075] The fourth connection portion 143 a may be formed on the second connection portion 141 a of the second sintered layer 141 , and the fourth band portion 143 b may extend from the fourth connection portion 143 a to the second band portion 141 b of the second sintered layer 141 .

[0076] The second plating layer 143 may be a Ni plating layer or a Sn plating layer, and may be formed to have a configuration in which a Ni plating layer and a Sn plating layer are sequentially formed on the second sintered layer 141, and may include a plurality of Ni plating layers and / or a plurality of Sn plating layers if necessary. However, the present disclosure is not limited thereto.

[0077] The insulating layer 150 may be formed on the capacitor body 110 to cover an end portion of the first band portion 131 b of the first sintered layer 131 and an end portion of the second band portion 141 b of the second sintered layer 141 .

[0078] For example, the insulating layer 150 may be provided to cover the first surface 1 , the second surface 2 , the fifth surface 5 , and the sixth surface 6 of the capacitor body 110 , and may be formed to have a strip shape.

[0079] In addition, the insulating layer 150 may be formed to have a substantially flat surface, or may be formed to be convex outward, or alternatively, the insulating layer 150 may be formed to be concave inward.

[0080] The shape of the insulating layer 150 may be determined according to the thickness of each position of the insulating layer 150. For example, Figure 4 As shown, when the thickness of the A portion and the B portion close to the first and second external electrodes is less than the thickness of the C portion located at the central portion of the capacitor body, the insulating layer 150 may protrude outward.

[0081] If the thicknesses of the A and B portions are greater than that of the C portion, the insulating layer may be concave inwardly, and if the thicknesses of the A, B, and C portions are similar, the insulating layer may have a substantially flat shape.

[0082] In addition, if Figure 1 As shown, the thickness of the portion of the insulating layer 150 located at the central portion in the X direction is greater than the maximum thickness of the first band portion 131 b of the first sintered layer 131 or the maximum thickness of the second band portion 141 b of the second sintered layer 141 .

[0083] The insulating layer 150 may serve to block a path for moisture to penetrate into the capacitor body 110 to improve moisture-proof reliability.

[0084] In addition, when the multilayer capacitor 100 is mounted on a substrate, stress may be generated when the substrate is deformed due to thermal shock or physical shock, and the insulating layer 150 may prevent the stress from being transferred to the capacitor body 110 and may serve to prevent cracking of the capacitor body 110 .

[0085] In this case, the insulating layer 150 may have a thickness of 10 μm or more. Here, the thickness of the insulating layer 150 is a maximum thickness obtained based on the thickest portion as a whole.

[0086] When the maximum thickness of the insulating layer 150 is less than 10 μm, cracks may occur in the capacitor body 110 .

[0087] In addition, when the maximum thickness of the insulating layer 150 is 10 μm or more, the bending of the capacitor body 110 can be reduced, so that even if the multilayer capacitor 100 is used for high voltage, it is expected to have the effect of reducing arc discharge. For example, the maximum thickness of the insulating layer 150, etc. can be measured in a cross section cut on the X-direction-Z-direction plane of the multilayer capacitor 100. In one example, the cut cross section may pass through the central part of the multilayer capacitor 100 in the Y direction. The thickness of the insulating layer 150 can be determined by: defining a predetermined number of points (e.g., 5 points) to the left and a predetermined number of points (e.g., 5 points) to the right from the reference center point of the insulating layer 150 at equal intervals (or alternatively, non-equal intervals); measuring the thickness at each of the points distributed at equal intervals (or alternatively, non-equal intervals); and selecting the maximum thickness among the thicknesses measured multiple times. The reference center point may be at the central area in the cut cross section. Alternatively, the maximum thickness of the insulating layer 150 may be the thickness at the central part of the cut cross section. For example, the measurement can be performed by a scanning electron microscope (SEM). Even if not described in the present disclosure, other methods and / or tools understood by a person of ordinary skill in the art may be used.

[0088] In this case, the length of the first band portion 131b of the first sintered layer 131 in the X direction is formed to be greater than the length of the first band portion 131b covered by the insulating layer 150 in the X direction, and the length of the second band portion 141b of the second sintered layer 141 in the X direction is formed to be greater than the length of the second band portion 141b covered by the insulating layer 150 in the X direction.

[0089] Therefore, regions not covered by the insulating layer 150 are respectively provided in the first belt portion 131 b and the second belt portion 141 b .

[0090] In the present embodiment, the third band portion 133 b of the first plating layer 133 is disposed to be in direct contact with the portion of the first band portion 131 b that is not covered by the insulating layer 150 .

[0091] The fourth band portion 143 b of the second plating layer 143 is disposed to be in direct contact with a portion of the second band portion 141 b that is not covered by the insulating layer 150 .

[0092] Therefore, the end of the first band portion 131b may not be covered by the third band portion 133b of the first plating layer 133 and may be covered by the insulating layer 150, and the end of the second band portion 141b may not be covered by the fourth band portion 143b of the second plating layer 143 and may be covered by the insulating layer 150.

[0093] That is, when the connection between the first connection portion 131a and the first band portion 131b is defined as a first corner in the first sintered layer 131, and when the connection between the second connection portion 141a and the second band portion 141b is defined as a second corner in the second sintered layer 141, the insulating layer 150 may not cover the first corner and the second corner, the first corner may be covered while being in direct contact with the first plating layer 133, and the second corner may be covered while being in direct contact with the second plating layer 143.

[0094] In this case, one end of the insulating layer 150 may contact an end of the third band portion 133 b of the first plating layer 133 , and the other end of the insulating layer 150 may contact an end of the fourth band portion 143 b of the second plating layer 143 .

[0095] Therefore, since the first sintered layer 131 and the second sintered layer 141 are not exposed to the outside, the reliability of the multilayer capacitor 100 may be prevented from being deteriorated.

[0096] When a substrate having a multilayer capacitor mounted thereon is compressed, stress may be applied to the multilayer capacitor as the substrate bends, and a warpage strength characteristic may be defined as a compression depth when there is no internal damage to the multilayer capacitor and a corresponding characteristic change.

[0097] In an external electrode including a conventional sintering type electrode layer, the electrode layer may be formed by mixing metal powder and a binder.

[0098] The sintered type electrode layer has the advantage of excellent electrical connectivity with the internal electrode, but has low ductility and is easily affected by mechanical stress, resulting in low warpage strength characteristics.

[0099] In order to improve the mechanical reliability of the multilayer capacitor, the external electrodes may be constructed by coating a conductive resin layer on a sintered type electrode layer.

[0100] Such a conductive resin layer has higher ductility than the sintered electrode, so that the mechanical properties of the multilayer capacitor can be improved, but even in this case, there are still difficulties in meeting the standards of electronic components (which require higher reliability).

[0101] If the length of the strip portion of the external electrode is extended, the reliability of the multilayer capacitor can be improved, but in this case, the probability of a short circuit increases as the distance between the two external electrodes becomes narrower.

[0102] In the multilayer capacitor of the present embodiment, an insulating layer may be provided to surround the capacitor body, so that the mechanical properties of the multilayer capacitor may be improved.

[0103] In this case, the insulating layer may be formed to cover a portion between the first and second external electrodes, a portion of the first sintered layer of the first external electrode, and a portion of the second sintered layer of the second external electrode of the outer surface of the capacitor body to be directly connected to the first and second external electrodes.

[0104] Further, the insulating layer may cover an end portion of the first band portion of the first sintered layer of the first external electrode and an end portion of the second band portion of the second sintered layer of the second external electrode.

[0105] In this case, a portion of the first belt portion and a portion of the second belt portion may not be covered by the insulating layer, and a portion of the first plating layer may directly contact the portion of the first belt portion and a portion of the second plating layer may directly contact the portion of the second belt portion.

[0106] Due to this structure, in the present embodiment, mechanical stress applied from the substrate through the external electrodes to the multilayer capacitor can be reduced, and the warpage strength characteristics of the multilayer capacitor can also be improved.

[0107] In addition, since a portion of the first sintered layer and a portion of the second sintered layer are not covered by the insulating layer and are formed to directly contact the first and second plating layers, respectively, electrical connectivity of the first and second external electrodes can be ensured at a certain level or higher.

[0108] Therefore, even if the length of the first band portion in the first sintered layer and the length of the second band portion in the second sintered layer are not significantly increased, the electrical connectivity of the external electrode and the warping strength characteristics of the multilayer capacitor can be ensured at a certain level or higher, and the incidence of short circuits that may occur when the first band portion and the second band portion contact each other can be effectively reduced.

[0109] Figure 5 is a perspective view schematically showing a multilayer capacitor according to another embodiment of the present disclosure, and Figure 6 It is along Figure 5 A cross-sectional view taken along line II-II'.

[0110] Reference Figure 5 and Figure 6 In the multilayer capacitor 100 ′ according to the present embodiment, the first and second external electrodes 130 ′ and 140 ′ may further include a first and second conductive resin layers 132 and 142 .

[0111] The first and second conductive resin layers 132 and 142 may protect the multilayer capacitor 100 ′ by absorbing impact from the outside, and may have excellent elongation, thereby improving the warpage strength characteristics of the multilayer capacitor 100 ′.

[0112] In the present embodiment, the first conductive resin layer 132 may cover the first sintered layer 131 and one end portion of the insulating layer 150 ′.

[0113] Therefore, one end portion of the insulating layer 150 ′ may be disposed between the first band portion 131 b of the first sintered layer 131 and an end portion of the first conductive resin layer 132 .

[0114] The first conductive resin layer 132 may include a conductive metal and a matrix resin.

[0115] In this case, the conductive metal may be one of copper, silver, nickel, and alloys thereof, and the present disclosure is not limited thereto.

[0116] The matrix resin may be a thermosetting resin, for example, may include epoxy resin, but the present disclosure is not limited thereto.

[0117] The second conductive resin layer 142 may cover the second sintered layer 141 and the other end of the insulating layer 150 ′.

[0118] Therefore, the other end portion of the insulating layer 150 ′ may be disposed between the second band portion 141 b of the second sintered layer 141 and the end portion of the second conductive resin layer 142 .

[0119] The second conductive resin layer 142 may include a conductive metal and a matrix resin.

[0120] In this case, the conductive metal may be one of copper, silver, nickel, and alloys thereof, and the present disclosure is not limited thereto.

[0121] The matrix resin may be a thermosetting resin, for example, may include epoxy resin, but the present disclosure is not limited thereto.

[0122] As another example, the first conductive resin layer 132 and the second conductive resin layer 142 may include a plurality of metal particles, an intermetallic compound, and a matrix resin.

[0123] The intermetallic compound may be used to improve electrical connectivity by connecting a plurality of metal particles, and may surround a plurality of metal particles and connect them to each other.

[0124] In this case, the intermetallic compound may include a metal having a melting point lower than a curing temperature of the base resin.

[0125] That is, since the intermetallic compound includes a metal having a melting point lower than the curing temperature of the matrix resin, the metal having a melting point lower than the curing temperature of the matrix resin may be melted during the drying and curing process and may form the intermetallic compound surrounding the metal particles with a portion of the metal particles.

[0126] In this case, the intermetallic compound may preferably include a metal having a low melting point of 300° C. or less.

[0127] For example, the intermetallic compound may include Sn having a melting point of 213° C. to 220° C. During the drying and curing process, the Sn may melt, and the molten Sn may wet metal particles having a high melting point (e.g., Ag, Ni, or Cu) by capillary phenomenon, and may react with a portion of the Ag, Ni, or Cu metal particles to form an intermetallic compound (e.g., Ag). 3 Sn、Ni 3 Sn 4 , Cu 6 Sn 5 and Cu 3 Sn).

[0128] In this case, Ag, Ni, or Cu which is not consumed in the reaction remains in the form of metal particles.

[0129] Therefore, the plurality of metal particles may include one or more of Ag, Ni, and Cu, and the intermetallic compound may include Ag. 3 Sn、Ni 3 Sn 4 , Cu 6 Sn 5 and Cu 3 One or more of Sn.

[0130] The first and second plating layers 133 ′ and 143 ′ may be disposed to cover the first and second conductive resin layers 132 and 142 , respectively.

[0131] An end portion of the third band portion 133 b ′ of the first plating layer 133 ′ and an end portion of the fourth band portion 143 b ′ of the second plating layer 143 ′ may be located above the insulating layer 150 ′, respectively.

[0132] Therefore, since the first sintering layer 131 and the second sintering layer 141 are not exposed to the outside, reliability degradation may be prevented.

[0133] In addition, the insulating layer 150' may be formed using a resin having elasticity. For example, the insulating layer 150' may be an epoxy resin as a polymer material. As another example, the insulating layer 150' may also include silicon dioxide, aluminum oxide, glass, and zirconium dioxide (ZrO 2 ), but the present disclosure is not limited thereto. The material of the insulating layer 150 ′ can be used to form the insulating layer 150 described above.

[0134] Fillers may also be added to the insulating layer 150' in an amount of 0.1 wt% in order to improve the heat resistance and coating properties of the polymer.

[0135] Reference Fig.11 In the photo, it can be seen that the insulation layer includes fillers. Fig.11 In the figure, the D portion is an insulating layer, the portion formed over the insulating layer is a conductive resin layer, and the portion formed over the conductive resin layer is a plating layer.

[0136] Figure 7 2 is a cross-sectional view showing a state where a multilayer capacitor according to an embodiment of the present disclosure is mounted on a substrate. Figure 7 The multilayer capacitor shown in Figure 2 The multilayer capacitor shown in the figure can also be Figure 6 The multilayer capacitor shown in FIG.

[0137] Reference Figure 7 , the mounting substrate according to the present embodiment includes a substrate 210 and a first electrode pad 221 and a second electrode pad 222 which are provided on the upper surface of the substrate 210 and are spaced apart from each other in the X direction.

[0138] In this case, the multilayer capacitor 100 is connected in a state such that the first plating layer 133 of the first external electrode 130 and the second plating layer 144 of the second external electrode 140 contact the first electrode pad 221 and the second electrode pad 222 , respectively, and is mounted on the substrate 210 .

[0139] The first plating layer 133 may be bonded to the first electrode pad 221 by the solder 231 for electrical and physical connection, and the second plating layer 143 may be bonded to the second electrode pad 222 by the solder 232 for electrical and physical connection.

[0140] Fig. 9 is a graph showing comparison results of a warpage strength test of a conventional multilayer capacitor (without an insulating layer) and a multilayer capacitor according to another embodiment of the present disclosure.

[0141] Here, the comparative example shows a multilayer capacitor in which the external electrode includes a sintered layer and a conductive resin layer and does not include an insulating layer, and the embodiment example shows a capacitor having Figure 6 A multilayer capacitor having an outer electrode structure and including an insulating layer.

[0142] In the comparative example, the thickness of the sintered layer is 10 μm, and the thickness of the conductive resin layer is 35 μm. In the embodiment example, the thickness of the sintered layer is 10 μm, the thickness of the conductive resin layer is 35 μm, and the thickness of the insulating layer is 25 μm.

[0143] In this case, the number of multilayer capacitors used in each set of samples was 30, and the multilayer capacitors were manufactured so that the length in the X direction was 3.2 mm, the length in the Y direction was 1.6 mm, and the length in the Z direction was 1.6 mm.

[0144] like Figure 8 As shown, a multilayer capacitor was mounted on a PCB and the substrate was bent by about 1 mm to 6 mm (the pressure point of the substrate moved by about 1 mm to 6 mm due to the pressure), and the presence of peeling (where the conductive resin layer of the outer electrode was separated from the capacitor body) or cracks (where a part of the capacitor body was damaged) or plating separation was observed. The results are shown in FIG. Fig. 9 shown.

[0145] Reference Fig. 9 In the case of the comparative example, cracks began to appear at 2.5 mm, and peeling began to occur at 3.5 mm (as shown in FIG. Fig. 9 "Stripping (behind edge)" shown) and separation of the plating.

[0146] On the other hand, in the case of the example of the embodiment, no peeling phenomenon occurred until 5.5 mm (eg Fig. 9 The "peeling (before edge)" and "peeling (after edge)"), cracks and plating separation shown in the figure, even at 6mm, there is no peeling phenomenon and cracks, and only 14 out of 30 multilayer capacitors have plating separation defects. In the figure, "before edge" means that the peeling phenomenon proceeds to the edge position, and "after edge" means that the peeling phenomenon exceeds the edge position, where the edge position can refer to Figure 6 Part E in the figure shows the corner of the capacitor body.

[0147] Therefore, it can be seen that the multilayer capacitor having a structure including an insulating layer of the present disclosure has excellent warpage strength characteristics compared to conventional multilayer capacitors.

[0148] Fig.10 : is a diagram showing comparison results of a warpage strength test of a multilayer capacitor according to thicknesses of insulating layers of a multilayer capacitor in another embodiment of the present disclosure.

[0149] The example applied here shows a Figure 6 A multilayer capacitor having an outer electrode structure and including an insulating layer.

[0150] In this case, the thickness of the sintered layer is 10μm, the thickness of the conductive resin layer is 35μm, and the maximum thickness of the insulating layer of sample No. 1 (#1) is 9.34μm, the maximum thickness of the insulating layer of sample No. 2 (#2) is 11.57μm, and the maximum thickness of the insulating layer of sample No. 3 (#3) is 16.34μm.

[0151] The number of multilayer capacitors used in each set of samples was 30, and the multilayer capacitors were manufactured so that the length in the X direction was 3.2 mm, the length in the Y direction was 1.6 mm, and the length in the Z direction was 1.6 mm.

[0152] like Figure 8 As shown, it can be seen that the multilayer capacitor is mounted on a PCB and the substrate is bent by about 1 mm to 6 mm to cause a peeling phenomenon (where the conductive resin layer of the outer electrode is separated from the capacitor body) or a crack (where a part of the capacitor body is damaged) or plating separation, as shown in FIG. Fig.10 shown.

[0153] Reference Fig.10 In the case of sample No. 1, cracks appeared when it exceeded 4 mm, and in the case of samples No. 2 and No. 3, no defects appeared until 5 mm, and even though some peeling occurred at 6 mm (such as Fig.10 "Peeling (after edge)" shown), but no cracks were present.

[0154] Therefore, it can be seen that the maximum thickness of the ideal insulating layer to prevent the occurrence of cracks is 10 μm or more.

[0155] As described above, according to an embodiment of the present disclosure, an insulating layer may be formed to cover a portion of the band portion of the sintered layer, and the remaining portion of the band portion may not be covered by the insulating layer but may be covered by a plating layer, thereby ensuring a certain level of bonding strength of the external electrodes while improving the bending strength characteristics of the multilayer capacitor.

[0156] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present invention as defined by the appended claims.

Claims

1. A multilayer capacitor comprising: a capacitor body including a first surface and a second surface opposite to each other, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other, and the capacitor body including a dielectric layer, a first inner electrode and a second inner electrode, the dielectric layer being stacked in a first direction connecting the first surface and the second surface and interposed between the first inner electrode and the second inner electrode, the first inner electrode being exposed through the third surface, and the second inner electrode being exposed through the fourth surface; a first external electrode and a second external electrode, respectively disposed on two ends of the capacitor body in a second direction connecting the third surface and the fourth surface, the first external electrode comprising a first sintered layer connected to the first internal electrode and a first plating layer disposed above the first sintered layer, and the second external electrode comprising a second sintered layer connected to the second internal electrode and a second plating layer disposed above the second sintered layer; an insulating layer disposed on the capacitor body to cover an end of the first band portion of the first sintered layer and an end of the second band portion of the second sintered layer, and a first conductive resin layer and a second conductive resin layer, wherein the maximum thickness of the insulating layer is 10 μm or greater, wherein a portion of the first band portion of the first sintered layer is exposed from the insulating layer, a portion of the second band portion of the second sintered layer is exposed from the insulating layer, the first conductive resin layer covers one end portion of the first sintered layer and the insulating layer, and the second conductive resin layer covers the other end portion of the second sintered layer and the insulating layer, and Wherein, the first plating layer and the second plating layer are arranged to cover the first conductive resin layer and the second conductive resin layer respectively.

2. The multilayer capacitor according to claim 1, wherein The first sintered layer includes a first connection portion and the first band portion, the first connection portion is disposed on the third surface of the capacitor body, the first band portion extends from the first connection portion to a portion of the first surface, a portion of the second surface, a portion of the fifth surface, and a portion of the sixth surface of the capacitor body. The second sintered layer includes a second connecting portion and a second band portion, the second connecting portion is arranged on the fourth surface of the capacitor body, and the second band portion extends from the second connecting portion to a portion of the first surface, a portion of the second surface, a portion of the fifth surface, and a portion of the sixth surface of the capacitor body.

3. The multilayer capacitor according to claim 2, wherein A connection between the first connection portion and the first band portion in the first sintered layer is defined as a first corner portion, and a connection between the second connection portion and the second band portion in the second sintered layer is defined as a second corner portion, The first corner is covered by the first plating layer, and the second corner is covered by the second plating layer.

4. The multilayer capacitor according to claim 2, wherein The first plating layer is provided on the first connecting portion and the first belt portion at portions exposed from the insulating layer. The second plating layer is disposed on portions of the second connecting portion and the second belt portion exposed from the insulating layer.

5. The multilayer capacitor according to claim 2, wherein The end of the first strip portion is disposed between the insulating layer and the capacitor body, The end of the second belt portion is disposed between the insulating layer and the capacitor body.

6. The multilayer capacitor according to claim 1, wherein The insulating layer includes resin and filler.

7. The multilayer capacitor according to claim 1, wherein The first conductive resin layer and the second conductive resin layer each include a conductive metal and a matrix resin.

8. The multilayer capacitor according to claim 1, wherein The first conductive resin layer and the second conductive resin layer each include a plurality of metal particles, an intermetallic compound, and a matrix resin.

9. A mounting substrate for a multilayer capacitor, comprising: a substrate having a first electrode pad and a second electrode pad on an upper surface; as well as The multilayer capacitor according to any one of claims 1 to 8, mounted on the substrate such that the first plated layer and the second plated layer of the multilayer capacitor are connected to the first electrode pad and the second electrode pad, respectively.

10. A multilayer capacitor comprising: a capacitor body including a first surface and a second surface opposite to each other, a third surface and a fourth surface connected to the first surface and the second surface and opposite to each other, and a fifth surface and a sixth surface connected to the first surface and the second surface and connected to the third surface and the fourth surface and opposite to each other, and the capacitor body including a dielectric layer, a first inner electrode and a second inner electrode, the dielectric layer being stacked in a first direction connecting the first surface and the second surface and interposed between the first inner electrode and the second inner electrode, the first inner electrode being exposed through the third surface, and the second inner electrode being exposed through the fourth surface; a first external electrode and a second external electrode, respectively disposed on two ends of the capacitor body in a second direction connecting the third surface and the fourth surface, the first external electrode comprising a first sintered layer connected to the first internal electrode and a first plating layer disposed above the first sintered layer, and the second external electrode comprising a second sintered layer connected to the second internal electrode and a second plating layer disposed above the second sintered layer; an insulating layer disposed on the capacitor body to cover an end of the first band portion of the first sintered layer and an end of the second band portion of the second sintered layer, and a first conductive resin layer and a second conductive resin layer, wherein a portion of the first band portion of the first sintered layer is exposed from the insulating layer, a portion of the second band portion of the second sintered layer is exposed from the insulating layer, the first conductive resin layer covers one end portion of the first sintered layer and the insulating layer, and the second conductive resin layer covers the other end portion of the second sintered layer and the insulating layer, The first plating layer and the second plating layer are provided to cover the first conductive resin layer and the second conductive resin layer, respectively, and The thickness of the portion of the insulating layer located at the central portion in the second direction is greater than the maximum thickness of the first band portion of the first sintered layer or the maximum thickness of the second band portion of the second sintered layer.

11. The multilayer capacitor according to claim 10, wherein The thickness of the portion of the insulating layer located at the central portion in the second direction is 10 μm or more.

12. The multilayer capacitor according to claim 10, wherein The first sintered layer includes a first connection portion and the first band portion, the first connection portion is disposed on the third surface of the capacitor body, the first band portion extends from the first connection portion to a portion of the first surface, a portion of the second surface, a portion of the fifth surface, and a portion of the sixth surface of the capacitor body. The second sintered layer includes a second connecting portion and a second band portion, the second connecting portion is arranged on the fourth surface of the capacitor body, and the second band portion extends from the second connecting portion to a portion of the first surface, a portion of the second surface, a portion of the fifth surface, and a portion of the sixth surface of the capacitor body.

13. The multilayer capacitor according to claim 12, wherein The end of the first strip portion is disposed between the insulating layer and the capacitor body, The end of the second belt portion is disposed between the insulating layer and the capacitor body.

14. The multilayer capacitor according to claim 10, wherein The insulating layer includes resin and filler.

15. The multilayer capacitor according to claim 10, wherein The first conductive resin layer and the second conductive resin layer each include a conductive metal and a matrix resin.

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