Improved heat management on semiconductor devices and methods of making the same

Abstract

The present application relates to improved heat management in semiconductor devices and methods for manufacturing the same. Disclosed herein are improved memory modules and methods for constructing the same. The memory module includes a substrate having a first surface and a second surface opposite the first surface, the first surface and the second surface each having a center portion, a first array region, and a second array region. The first array region is cooler than the second array region during operation. The memory module also includes a power management integrated circuit attached to the center portion of the first surface. The memory module also includes a first semiconductor die attached to the substrate in the first array region. The first semiconductor die has a first performance level for operating parameters at high temperatures. The memory module also includes a second semiconductor die attached to the substrate in the second array region. The second semiconductor die has a second performance level for operating parameters at high temperatures that is better than the first performance level.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices. In particular, the present technology relates generally to improved management of heat on memory modules. Background Art

[0002] Semiconductor devices (e.g., double data rate random access memory (DDR RAM) dual in-line memory modules, die stack assemblies, NAND-type flash memory devices, etc.) typically include multiple semiconductor dies along with one or more heat-generating components. As the footprint of semiconductor devices shrinks and processing speeds increase, the operating temperature of the semiconductor devices typically increases, which can impair the performance of the semiconductor dies.

[0003] For example, a DIMM typically includes several semiconductor dies, such as dynamic random access memory integrated circuits, mounted on one or more surfaces of a DIMM substrate (e.g., a printed circuit board). In a typical fourth-generation double data rate ("DDR4") configuration of a DIMM, the DIMM includes a substrate, several semiconductor dies mounted on both sides of the substrate, a register clock driver ("RCD"), and several connectors. In newer generations (e.g., DDR5 DIMMs), the DIMM also includes a power management integrated circuit ("PMIC") mounted to the substrate. The PMIC generates additional heat, and the RCD operates at a shorter clock cycle, which has led to an increase in the operating temperature of DDR5 DIMM devices. In addition, semiconductor dies are mounted closer together to make room for the PMIC, increase the capacity of the new generation, and allow for the smaller DIMM pitch of the new generation. Higher temperatures, in turn, lead to increased power consumption from the semiconductor dies and more frequent die failures. Summary of the Invention

[0004] An aspect of the present invention provides a method for constructing an improved memory module having two or more semiconductor dies, wherein the method includes: determining performance levels of temperature-affected operating parameters of individual semiconductor dies of the memory module at a first temperature; determining the performance levels of the operating parameters of the individual semiconductor dies at a second temperature higher than the first temperature; identifying at least one first semiconductor die that is temperature-affected at high temperatures and at least one second semiconductor die that is not as temperature-affected as the first semiconductor die based on the determined performance levels at the first and second temperatures; mounting the first semiconductor die in a first array region of a memory module substrate and mounting the second semiconductor die in a second array region of the memory module substrate, wherein the first array region is cooler than the second array region during operation.

[0005] Another aspect of the present invention provides a memory module comprising: a substrate having a surface, the surface having a central portion, a first array region on one side of the central portion, and a second array region on an opposite side of the central portion, wherein the first array region is cooler than the second array region during operation; a first semiconductor die attached to the substrate in the first array region on the surface such that the first semiconductor die is positioned upstream of the central portion with respect to airflow across the surface, wherein the first semiconductor die has a first performance level for an operating parameter affected by temperature; and a second semiconductor die attached to the substrate in the second array region such that the second semiconductor die is positioned downstream of the central portion with respect to the airflow across the surface, wherein the second semiconductor die has a second performance level for the operating parameter indicating that the second semiconductor die operates more efficiently at high temperatures than the first semiconductor die, and wherein the first and second semiconductor die are the same type of die.

[0006] Another aspect of the present invention provides a memory module comprising: a substrate including a central portion, an upstream edge, a downstream edge opposite the upstream edge, a first array region between the upstream edge and the central portion, a second array region between the downstream edge and the central portion, and a surface extending from the upstream edge to the downstream edge, wherein: the surface includes one or more die attach locations in each of the first and second array regions, the upstream edge is located upstream of the central portion with respect to airflow across the substrate, and the downstream edge is located downstream of the central portion with respect to the airflow across the substrate; a first semiconductor die attached to the surface of the substrate in a first die attach location in the first array region; and a second semiconductor die attached to the surface of the substrate in a second die attach location in the second array region; wherein a performance indicator of an operating parameter of the first semiconductor die has a first variation based on temperature, and the performance indicator of the operating parameter of the second semiconductor die has a second variation that is less than the first variation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Many aspects of the present technology can be better understood with reference to the accompanying drawings. The components in the figures are not necessarily drawn to scale. Instead, emphasis should be placed upon clearly illustrating the principles of the present technology.

[0008] Figure 1A is a top plan view of a dual in-line memory module ("DIMM") in accordance with some embodiments of the present technology.

[0009] Figure 1B According to some embodiments of the present technology Figure 1A A bottom-up plan view of a DIMM.

[0010] Figure 2A is a top plan view of a DIMM before any semiconductor die are mounted to a substrate, according to some embodiments of the present technology.

[0011] Figure 2B is a process according to some embodiments of the present technology prior to mounting any semiconductor die to a substrate. Figure 2A A bottom-up plan view of a DIMM.

[0012] Figure 3A is after mounting two first semiconductor dies to a substrate according to some embodiments of the present technology Figure 2A A top plan view of the DIMM.

[0013] Figure 3B is after mounting two first semiconductor dies to a substrate according to some embodiments of the present technology Figure 3A A bottom-up plan view of a DIMM.

[0014] Figure 4A is after mounting two second semiconductor dies to the substrate according to some embodiments of the present technology Figure 3A A top plan view of the DIMM.

[0015] Figure 4B is after mounting two second semiconductor dies to the substrate according to some embodiments of the present technology Figure 3A A bottom-up plan view of a DIMM.

[0016] Figure 5A is after mounting two third semiconductor dies to the substrate according to some embodiments of the present technology Figure 4A A top plan view of the DIMM.

[0017] Figure 5B is after mounting two third semiconductor dies to the substrate according to some embodiments of the present technology Figure 4A A bottom-up plan view of a DIMM.

[0018] Figure 6A is after mounting two fourth semiconductor dies to the substrate according to some embodiments of the present technology Figure 5A A top plan view of the DIMM.

[0019] Figure 6B is after mounting two fourth semiconductor dies to the substrate according to some embodiments of the present technology Figure 5A A bottom-up plan view of a DIMM.

[0020] Figure 7A is after the remaining semiconductor die is mounted to the substrate according to some embodiments of the present technology Figure 6A A top plan view of the DIMM.

[0021] Figure 7B is after the remaining semiconductor die is mounted to the substrate according to some embodiments of the present technology Figure 6A A bottom-up plan view of a DIMM.

[0022] Figure 8 is a cross-sectional view of a semiconductor die assembly configured in accordance with embodiments of the present technology.

[0023] Figure 9 is a schematic diagram of a system including a semiconductor die assembly configured in accordance with embodiments of the present technology. DETAILED DESCRIPTION

[0024] Disclosed herein are improved configurations of semiconductor devices and methods for manufacturing the same. In some embodiments, the semiconductor device is a dual in-line memory module (DIMM). The DIMM includes a DIMM substrate (e.g., a printed circuit board) having a first surface and a second surface opposite the first surface. Each of the first and second surfaces has a center portion, a first array region on one side of the center portion, and a second array region on an opposite side of the center portion. In some embodiments, during operation of the DIMM (e.g., when the first array region is upstream of the center portion relative to the direction of airflow across the DIMM), the first array region is cooler than the second array region. A power management integrated circuit (PMIC) may be attached to the center portion of the first surface. A first semiconductor die may be attached to the substrate in the first array region such that the first semiconductor die is positioned upstream of the PMIC. A second semiconductor die may be attached to the substrate in the second array region such that the second semiconductor die is positioned downstream of the PMIC. Each semiconductor die has a performance rating for an operating parameter indicating the efficiency of the semiconductor die in operating at high temperatures (e.g., a degree of variation of the operating parameter of the semiconductor die at high temperatures, a raw score of the operating parameter at high temperatures, etc.). In various embodiments, the operating parameter may be power consumption, data retention, and / or some combination thereof.The second semiconductor die may have a better performance level than the first semiconductor die and thus be better suited for operation at high temperatures.

[0025] As disclosed herein, the present technology also includes a method for constructing an improved DIMM. The method may include determining performance levels for temperature-affected operating parameters of individual semiconductor dies of the DIMM at a first temperature; then, determining performance levels for the operating parameters of the semiconductor dies at a second temperature higher than the first temperature. After determining the performance levels, the method may include identifying at least one first semiconductor die and at least one second semiconductor die, wherein the second semiconductor die is less temperature-affected than the first semiconductor die based on the determined performance levels. Once these are identified, the method may include constructing the DIMM to account for the performance levels. For example, the method may include mounting one or more heat-generating components to a central portion of a DIMM substrate, mounting a first semiconductor die in a first array region of the DIMM substrate, and mounting a second semiconductor die in a second array region of the DIMM substrate. The first array region may be selected for the first semiconductor die because, during operation of the DIMM, the first array region is cooler than the second array region. For example, the first array region may be located upstream of the one or more heat-generating components relative to the direction of airflow across the DIMM, such that heat from the PMIC is directed away from the first array region.

[0026] In the following description, numerous specific details are discussed to provide a thorough and informative description of embodiments of the present technology. However, one skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known structures or operations typically associated with memory devices are not shown or described in detail to avoid obscuring other aspects of the present technology. In general, it will be understood that various other devices, systems, and methods beyond those specific embodiments disclosed herein may also be within the scope of the present technology.

[0027] As used herein, the terms "upstream," "downstream," "up," "down," "distal," "proximal," "front," and "rear" may refer to the relative directions or positions of features in a semiconductor device in view of the orientation shown in the figures. For example, "distal" or "farthest" may refer to a feature that is positioned farther from a heat-generating component of the semiconductor device than other features. However, these terms should be broadly interpreted to include semiconductor devices having other orientations (e.g., inverted or tilted orientations), where top / bottom, over / under, above / under, up / down, front / back, and left / right may be interchanged depending on the orientation.

[0028] Furthermore, as used herein, the term "semiconductor die" may include a semiconductor die package and / or a semiconductor die assembly (e.g., one or more semiconductor dies attached to a package substrate and / or sealed by a protective coating). Thus, the term "semiconductor die" should not be interpreted as excluding semiconductor packages or assemblies unless explicitly indicated.

[0029] Figure 1A is a top plan view, and Figure 1B FIG. 1 is a bottom plan view illustrating a dual in-line memory module 100 ("DIMM") according to some embodiments of the present technology. In the illustrated embodiment, the DIMM 100 includes a DIMM substrate 102 having Figure 1A The first surface 104 (eg, top surface) and Figure 1B 1. The DIMM substrate 102 includes a second surface 106 (e.g., a bottom surface) opposite the first surface 104 as illustrated in FIG. The DIMM substrate 102 also has a first edge 108, a second edge 110 opposite the first edge 108, and a longitudinal edge 112 extending from the first edge 108 to the second edge 110. The first edge 108 can be positioned "upstream" of the second edge 110 relative to an airflow 114 that travels across the first and second surfaces 104, 106 and is generally parallel to the longitudinal edge 112.

[0030] As further illustrated, the first and second surfaces 104, 106 of the DIMM substrate 102 include a central portion 116, a first array region 118, and a second array region 120. The first array region 118 is on a first side of the central portion 116 and between the central portion 116 and the first edge 108. The second array region 120 is on a second side of the central portion 116, opposite the first side, and between the central portion 116 and the second edge 110. Thus, the first array region 118 is upstream of the central portion 116 relative to the airflow direction 114, while the second array region 120 is downstream.

[0031] In some embodiments, DIMM 100 may include several connectors 122 along one of longitudinal edges 112. Connectors 122 may allow DIMM 100 to connect to other components in a semiconductor system.

[0032] refer to Figure 1A, DIMM 100 also includes a power management integrated circuit 124 ("PMIC 124") attached to the central portion 116 of the first surface 104 of the DIMM substrate 102, and semiconductor dies 128 attached to the first surface 104 in both the first array area 118 and the second array area 120. In the illustrated embodiment, DIMM 100 includes ten semiconductor dies 128 in two rows in the first array area 118, and ten semiconductor dies 128 in two rows in the second array area 120. In various other embodiments, DIMM 100 may include other numbers of semiconductor dies 128, which may be attached to the first surface 104 in the first array area 118 and the second array area 120, and / or arranged in various other patterns. For example, in some embodiments, DIMM 100 may include twenty semiconductor dies arranged in four rows in the first array area 118, and fifteen semiconductor dies arranged in three rows in the second array area 120.

[0033] refer to Figure 1B , DIMM 100 also includes a register clock driver 126 (“RCD 126”) attached to the central portion 116 of the second surface 106 of the DIMM substrate 102 and semiconductor dies 128 attached to the second surface 106 in both the first array area 118 and the second array area 120. Furthermore, while the illustrated embodiment has ten semiconductor dies 128 attached to each of the first array area 118 and the second array area 120 of the second surface 106, DIMM 100 may include any other number of semiconductor dies 128 in various other arrangements.

[0034] In some embodiments, all active semiconductor components are attached and mounted to only one surface of DIMM 100. For example, in some embodiments, PMIC 124 and / or RCD 126 are attached to center portion 116 of first surface 104, while all semiconductor dies 128 are mounted on first surface 104.

[0035] In the illustrated embodiment, the PMIC 124 and RCD 126 are significant heat sources in the DDR5 DIMM. Furthermore, the semiconductor die 128 is packaged into a relatively small footprint. Consequently, the operating temperature of the DIMM 100 is often high enough to affect the performance level of one or more operating parameters of the semiconductor die 128. For example, operating parameters affected by temperature may include power consumption, computing speed, data retention, and / or a combination thereof. For example, semiconductor dies 128 with high cell data retention failure rates, IDD2N, or IDD3N have been found to consume more power at high temperatures. Therefore, controlling the operating temperature of the DIMM 100 can improve the performance and retention of the semiconductor die 128. However, temperature control mechanisms other than the airflow 114 consume space and power, thereby undermining the reduction in size and power consumption improvements of the DDR5 DIMM.

[0036] Conversely, semiconductor die 128 may be arranged with consideration given to the effects of operating temperature. For example, airflow 114 transfers heat such that portions of DIMM 100 downstream of PMIC 124 and RCD 126 may have a higher temperature than upstream portions. For example, in the illustrated embodiment, first array region 118 of first and second surfaces 104, 106 may have a lower average temperature than second array region 120 of first and second surfaces 104, 106. Furthermore, because PMIC 124 typically dissipates more heat than RCD 126, first array region 118 of second surface 106 may have a lower average temperature than first array region 118 of first surface 104. Thus, by mounting semiconductor die, which are relatively more affected by temperature, in first array region 118 and semiconductor die, which are relatively less affected by temperature, in second array region 120, the overall performance of the illustrated DIMM 100 may be improved.

[0037] In some embodiments, the maximum temperature difference in the illustrated DIMM 100 may be at the first die attach location 130a ( Figure 1B ) ) ) and the second die attach location 130b ( ) in the second array region 120 on the first surface 104 ) Figure 1A) (e.g., the hottest die attach location). In some embodiments, the temperature difference from the hottest die attach location to the coldest die attach location can be approximately 40° C. Therefore, the overall performance of the illustrated DIMM 100 can be further improved by mounting semiconductor dies that are relatively more temperature-affected in the first die attach location 130 a and semiconductor dies that are relatively less temperature-affected in the second die attach location 130 b. In some embodiments, the die that is most temperature-affected can be mounted in the first die attach location 130 a, and / or the die that is least temperature-affected can be mounted in the second die attach location 130 b.

[0038] In some embodiments, the improvements described above can be summarized and captured by a construction method that includes determining performance levels of one or more operating parameters for each individual semiconductor die 128 to be included in the DIMM 100 at a first temperature. In some embodiments, the first temperature can be generally equal to the coldest operating region of the DIMM 100 (e.g., the operating temperature at the coldest die attach location 130a).

[0039] The method continues by determining a performance level for one or more operating parameters of each individual semiconductor die 128 of the DIMM 100 at a second temperature that is higher than the first temperature. In some embodiments, the second temperature may be generally equal to the hottest operating region of the DIMM 100 (e.g., the operating temperature at the hottest die attach location 130b).

[0040] The method continues by identifying at least one first semiconductor die that is relatively more affected by temperature than other semiconductor dies and at least one second semiconductor die that is relatively less affected by temperature than other semiconductor dies. The degree to which the semiconductor dies are affected by temperature may be based on performance levels of one or more operating parameters determined at the first and second temperatures. In some embodiments, a third step may include identifying one or more semiconductor dies that are most affected by temperature as the first semiconductor die, and / or identifying one or more semiconductor dies that are least affected by temperature as the second semiconductor die. In some embodiments, the third step may include identifying a predetermined percentage of semiconductor dies (e.g., approximately 1%, 5%, 10%, 20%, or other suitable portion) as being more affected by temperature than other semiconductor dies, and / or identifying a predetermined portion as being less affected by temperature than other semiconductor dies.

[0041] The method further includes mounting components of the DIMM 100 to the DIMM substrate 102. For example, the PMIC 124 may be mounted to the center portion 116 of the first surface 104 of the DIMM substrate 102, and the RCD 126 may be mounted to the center portion 116 of the second surface 106 of the DIMM substrate 102, which is opposite the first surface 104. The PMIC 124 and the RCD 126 are mounted to the center portion 116 to balance timing between semiconductor dies 128 in the DIMM 100. For example, semiconductor dies 128 that are approximately equidistant from the center portion 116 in either the upstream or downstream direction will receive signals from the RCD 126 at approximately equal times. Thus, mounting the PMIC 124 and the RCD 126 in the center portion 116 allows for easy balancing of timing between the semiconductor dies 128. Furthermore, at least one first semiconductor die may be mounted to the first array region 118, and at least one second semiconductor die may be mounted to the second array region 120.

[0042] In various embodiments, the method may include various additional processes to further improve the performance of the DIMM 100. For example, in some embodiments, the method may include identifying one or more first die attach locations 130a on the DIMM substrate 102 (e.g., die attach locations with a cooler operating temperature) and installing a first semiconductor die in the first die attach locations 130a. In some embodiments, if there are N first semiconductor dies, the method may include identifying N cooler die attach locations. Similarly, in some embodiments, the method may include identifying one or more second die attach locations 130b on the DIMM substrate 102 (e.g., die attach locations with the hottest operating temperature) and installing a second semiconductor die in a hotter die attach location. In some embodiments, if there are N second semiconductor dies, the method may include identifying N hotter die attach locations.

[0043] In some embodiments, the method may include identifying at least one third semiconductor die that is less temperature-affected than the first semiconductor die and more temperature-affected than the second semiconductor die. In some embodiments, the at least one third semiconductor die may be the second most temperature-affected die and may be mounted in the first array region 118 of the DIMM substrate 102 and / or in a second cooler die attach location on the DIMM substrate 102 (see Figure 5A and 5BIn some embodiments, the method may include identifying at least one fourth semiconductor die that is less temperature-affected than the third semiconductor die and more temperature-affected than the second semiconductor die. In some embodiments, the at least one fourth semiconductor die may be the second least temperature-affected die and may be mounted in the second array region 120 of the DIMM substrate 102 and / or in a second hottest die attach location on the DIMM substrate 102 (see Figure 6A and 6B ).

[0044] Figures 2A to 7B Stages of constructing DIMM 100 according to an embodiment of the method discussed above are illustrated. Figure 2A is a top plan view, and Figure 2B 1 is a bottom plan view illustrating a DIMM 100 before any semiconductor die 128 are mounted to the DIMM substrate 102, according to some embodiments of the present technology. In the illustrated embodiment, the DIMM 100 includes the DIMM substrate 102, a PMIC 124 attached to a central portion 116 of a first surface 104 of the DIMM substrate 102, and an RCD 126 attached to a central portion 116 of a second surface 106 of the DIMM substrate 102. As further illustrated, the first array area 118 includes a number of die attach locations 130 on the first surface 104, and a number of die attach locations 130 on the second surface 106. Similarly, the second array area 120 includes a number of die attach locations 130 on the first surface 104, and a number of die attach locations 130 on the second surface 106.

[0045] Because the PMIC 124 is attached to the center portion 116 of the first surface 104, the first surface 104 tends to have hotter die attach locations 130 than the second surface 106. Furthermore, because airflow travels across the DIMM 100 from the first edge 108 to the second edge 110, the first array region 118 (upstream of the PMIC 124) tends to have cooler die attach locations 130 than the second array region 120 (downstream of heat-generating components). Consequently, the coldest die attach locations 130 on the DIMM substrate 102 tend to be those in the first array region 118 on the second surface 106 that are farthest from the center portion 116, while the second-coldest die attach locations tend to be those in the first array region 118 on the first surface 104 that are farthest from the center portion 116. Conversely, the hottest die attach locations 130 tend to be those in the second array region 120 that are closest to the center portion 116.

[0046] Figure 3A is a top plan view, and Figure 3B1 is a bottom plan view illustrating the DIMM 100 after two first semiconductor dies 128a have been mounted to the DIMM substrate 102, in accordance with some embodiments of the present technology. In the illustrated embodiment, the first semiconductor dies 128a have been mounted to the DIMM substrate 102 in the two first die attach locations 130a in the first array region 118 that are farthest from the PMIC 124 (e.g., adjacent the first edge 108 and upstream from the center portion 116). Thus, in some embodiments, the first semiconductor dies 128a are mounted in the coolest die attach locations on the DIMM substrate 102.

[0047] As discussed above, the first semiconductor die 128a can be more affected by temperature than the other semiconductor dies in the DIMM 100 (e.g., the performance level of one or more operating parameters can have a greater drop between low and high temperatures, can have a worse performance level at high temperatures, etc.). Therefore, placing the first semiconductor die 128a in the first array region 118 can improve the overall functionality of the DIMM 100 by partially avoiding the detrimental effects of high temperatures on the operating parameters of the first semiconductor die 128a. In the illustrated embodiment, placing the first semiconductor die 128a in the first die attach location 130a (e.g., positioned in the coolest location on the DIMM) can further improve the overall functionality of the DIMM 100 by further avoiding the detrimental effects of high temperatures. In some embodiments, the first semiconductor die 128a can be the most affected by temperature (e.g., having operating parameters that are worse overall or worse on average than the other semiconductor dies). Thus, in these embodiments, placing the first semiconductor die 128a in the first die attach location 130a may also further improve the overall functionality of the DIMM 100 by further avoiding the deleterious effects of high temperatures.

[0048] Although the DIMM 100 is illustrated as having two first semiconductor dies 128 a, the DIMM 100 may include other numbers of first semiconductor dies 128 a (and therefore occupy different numbers of first die attach locations 130 a). For example, in some embodiments, the DIMM 100 includes only a single first semiconductor die 128 a, which may be mounted in a single first die attach location 130 a (e.g., the coolest die attach location, typically the farthest location upstream from the PMIC 124 in the first array region 118 on the second surface 106). In other embodiments, the DIMM 100 may include four first semiconductor dies 128 a mounted in four first die attach locations 130 a, such as all four locations in the first array region 118 that are farthest from the PMIC 124.

[0049] Figure 4A is a top plan view, and Figure 4B1 is a bottom plan view illustrating the DIMM 100 after two second semiconductor dies 128b have been mounted to the DIMM substrate 102, in accordance with some embodiments of the present technology. In the illustrated embodiment, the second semiconductor dies 128b have been mounted to the DIMM substrate 102 in the two second die attach locations 130b closest to the PMIC 124 in the second array region 120 (e.g., downstream of the center portion 116). Thus, in some embodiments, the second semiconductor dies 128b are mounted in the hottest die attach locations on the DIMM substrate 102.

[0050] As discussed above, the second semiconductor die 128b can have one or more operating parameters that are less affected by temperature than the other semiconductor dies in the DIMM 100. Therefore, placing the second semiconductor die 128b in the second array region 120 can improve the overall functionality of the DIMM 100 by partially reducing the detrimental effects of high temperatures (e.g., by positioning a semiconductor die that is less affected by temperature in a hotter die attach location). In the illustrated embodiment, placing the second semiconductor die 128b in the second die attach location 130b can further improve the overall functionality of the DIMM 100 by further reducing the detrimental effects of high temperatures. In some embodiments, the second semiconductor die 128b can be the least affected by temperature (e.g., having operating parameters that are collectively or on average better than all the other semiconductor dies in the DIMM 100). Therefore, in these embodiments, placing the second semiconductor die 128b in the second die attach location 130b can also further improve the overall functionality of the DIMM 100 by further reducing the detrimental effects of high temperatures.

[0051] In some embodiments, the second semiconductor die 128b may have operating parameters that improve at high temperatures. For example, in some embodiments, the processing speed of the second semiconductor die 128b may improve at high temperatures. Therefore, in these embodiments, placing the second semiconductor die 128b in the second die attach location 130b may improve the overall functionality of the DIMM 100 by utilizing high temperatures. In some embodiments, the second semiconductor die 128b may be the semiconductor die that improves most at high temperatures. Therefore, in these embodiments, placing the second semiconductor die 128b in the second die attach location 130b may further improve the overall functionality of the DIMM 100.

[0052] Although the DIMM 100 is illustrated as having two second semiconductor dies 128 b, the DIMM 100 may include other numbers of second semiconductor dies 128 b (and therefore occupy different numbers of second die attach locations 130 b). For example, in some embodiments, the DIMM 100 includes only a single second semiconductor die 128 b, which may be mounted to a single second die attach location 130 b (e.g., the hottest die attach location, typically the location closest to the PMIC 124 in the second array region 120 on the first surface 104). In other embodiments, the DIMM 100 may include four second semiconductor dies 128 b mounted to four second die attach locations 130 b, such as all four locations closest to the PMIC 124 in the second array region 120.

[0053] Figure 5A is a top plan view, and Figure 5B is a bottom plan view illustrating the DIMM 100 after two third semiconductor dies 128c have been mounted to the DIMM substrate 102, in accordance with some embodiments of the present technology. In the illustrated embodiment, the third semiconductor dies 128c have been mounted to the DIMM substrate 102 in two third die attach locations 130c in the first array area 118 that are second away from the PMIC 124 after the first semiconductor die 128a has been mounted. Thus, in some embodiments, the third semiconductor die 128c are mounted in the second coolest die attach locations available on the DIMM substrate 102.

[0054] In some embodiments, the third semiconductor die 128c may have one or more operating parameters that are less affected by temperature than the first semiconductor die 128a, but more affected by temperature than the second semiconductor die 128b. Therefore, in these embodiments, placing the third semiconductor die 128c in the next, third die attach location 130c may improve the overall functionality of the DIMM 100 by at least partially avoiding the detrimental effects of high temperatures. In some embodiments, the third semiconductor die 128c may be the second most affected by temperature. Therefore, in these embodiments, placing the third semiconductor die 128c in the third die attach location 130c further improves the overall functionality of the DIMM 100 by further avoiding the detrimental effects of high temperatures.

[0055] Figure 6A is a top plan view, and Figure 6Bis a bottom plan view illustrating the DIMM 100 after two fourth semiconductor dies 128d have been mounted to the DIMM substrate 102, in accordance with some embodiments of the present technology. In the illustrated embodiment, the fourth semiconductor die 128d has been mounted to the DIMM substrate 102 in two fourth die attach locations 130d in the second array area 120 that are second closest to the PMIC 124 after the second semiconductor die 128b has been mounted. Thus, in some embodiments, the fourth semiconductor die 128d is mounted in the second hottest die attach location available on the DIMM substrate 102.

[0056] In some embodiments, the fourth semiconductor die 128 d may have one or more operating parameters that are less affected by temperature than the third semiconductor die 128 c, but more affected by temperature than the second semiconductor die 128 b. Thus, in these embodiments, placing the fourth semiconductor die 128 d in the fourth die attach location 130 d may improve the overall functionality of the DIMM 100 by partially reducing the detrimental effects of high temperatures (e.g., by positioning a semiconductor die that is less affected by temperature in a hotter die attach location). In some embodiments, the fourth semiconductor die 128 d may be the second least affected by temperature. Thus, in these embodiments, placing the fourth semiconductor die 128 d in the fourth die attach location 130 d may further improve the overall functionality of the DIMM 100 by further reducing the detrimental effects of high temperatures.

[0057] Figure 7A is a top plan view, and Figure 7B FIG2 is a bottom plan view illustrating the DIMM 100 after any remaining semiconductor die 128 e have been mounted to the DIMM substrate 102, according to some embodiments of the present technology. In the illustrated embodiment, the remaining semiconductor die 128 e have already been mounted to the DIMM substrate 102 in the remaining die attach locations, without regard to the effects of high temperatures on their operating parameters. That is, in the illustrated embodiment, the method described above stops selectively mounting semiconductor die after the fourth semiconductor die is mounted. For example, in some embodiments, continued selective placement may result in minimal further improvement in the overall performance of the DIMM 100. In some embodiments, for example, the remaining semiconductor die 128 e may have operating parameters at high temperatures that generally do not vary (or do not vary significantly) among the remaining semiconductor die 128 e. In some embodiments, the remaining die attach locations may have relatively small differences in operating temperatures.

[0058] In some embodiments, the semiconductor dies 128 may be installed in various other arrangements or sequences. For example, the second semiconductor die 128b may be installed first, all semiconductor dies that are less affected by temperature may be installed first, the semiconductor dies 128 may be installed from left to right while selectively placing the first, second, third, and / or fourth semiconductor dies 128a to d. In various embodiments, the selective placement method may stop at various other points after selectively installing any number of semiconductor dies. For example, in some embodiments, the method may stop only after the first semiconductor die 128a has been selectively installed. In some embodiments, the method may stop only after the second semiconductor die 128b has been selectively installed. In some embodiments, the method may stop only after the first and second semiconductor dies 128a, 128b have been selectively installed. In some embodiments, the method may continue to selectively place the semiconductor dies 128 in the die attach position until each semiconductor die 128 has been mounted to the DIMM substrate 102.

[0059] As disclosed above, the method of selectively placing semiconductor dies to passively mitigate and / or maximize temperature effects can be applied to various other semiconductor devices to improve their performance (e.g., any generation of DIMMs with any level of semiconductor dies, other memory modules, semiconductor die stacks, and other semiconductor devices). For example, Figure 8 is a cross-sectional view of a semiconductor die assembly 800 ("assembly 800") configured in accordance with embodiments of the present technology. In the illustrated embodiment, assembly 800 includes a package support substrate 802 (e.g., an interposer), a controller die 824 mounted to support substrate 802, and several semiconductor die 828 (labeled 828a-e, respectively) mounted to controller die 824 in a stack 840 of semiconductor die ("stack 840").

[0060] In the illustrated embodiment, the controller die 824 can be a significant heat source in the assembly 800. Consequently, the operating temperature of the assembly 800 can be hotter near the controller die 824 and cooler farther away, such that the operating temperature of the semiconductor dies 828 in the stack 840 gradually decreases as more semiconductor dies 828 are added. In the illustrated embodiment, for example, the first semiconductor die 828a is the top semiconductor die in the stack 840, farthest from the controller die 824. Consequently, the performance of the assembly 800 can be improved when the first semiconductor die 828a is more affected by temperature than the other semiconductor dies 828 in the stack 840. In some embodiments, the first semiconductor die 828a can be the most affected by temperature of all the semiconductor dies 828, further improving the performance of the assembly 800.

[0061] Furthermore, the second semiconductor die 828b is the lowest semiconductor die in the stack 840 (e.g., the second semiconductor die 828b is mounted on the controller die 824). Therefore, the performance of the assembly 800 can be improved when the second semiconductor die 828b is less affected by temperature than the other semiconductor dies 828 in the stack 840. In some embodiments, the second semiconductor die 828b can be the least affected by temperature of all the semiconductor dies 828, further improving the performance of the assembly 800.

[0062] As further illustrated, the third semiconductor die 828c is below the first semiconductor die 828a and is the second highest in the stack 840 (e.g., in the second coolest position in the stack 840). Therefore, when the third semiconductor die 828c is more temperature-affected than the other semiconductor die 828 in the stack 840, performance of the assembly 800 can be improved. In some embodiments, the third semiconductor die 828c can be the second most temperature-affected of all the semiconductor die 828. The fourth semiconductor die 828d is above the second semiconductor die 828b and is the second lowest in the stack 840 (e.g., in the second hottest position in the stack 840). Therefore, when the fourth semiconductor die 828d is less temperature-affected than the other semiconductor die 828 in the stack 840, performance of the assembly 800 can be improved. In some embodiments, the fourth semiconductor die 828d can be the second least temperature-affected of all the semiconductor die 828. Finally, in the illustrated embodiment, the fifth semiconductor die 828e is located in the middle (e.g., in a mid-temperature position) of the stack 840. The fifth semiconductor die 828e can be affected by temperature more than the second and / or fourth semiconductor dies 128b, 128d, but less than the first and / or third semiconductor dies 128a, 128c.

[0063] In some embodiments, the fifth semiconductor die can be used as a separated die in the stack 840, where the semiconductor die that is more affected by temperature is placed above the fifth semiconductor die 828e (but in no particular order) and the die that is less affected by temperature is placed below the fifth semiconductor die 828e (but in no particular order).

[0064] By selectively placing semiconductor die 828 in stack 840, the method can result in improved performance of assembly 800. For example, in some embodiments, semiconductor die 128 can be placed based on the effect of temperature on power consumption in the assembly. In these embodiments, selective placement can reduce the amount of power leaked from assembly 800 during operation without introducing additional components to assembly 800.

[0065] With the above reference Figures 1A to 8Any one of the semiconductor devices of the described features may be incorporated into any of a number of larger and / or more complex systems, representative examples of which are Figure 9 900 is schematically shown in FIG. The system 900 may include a memory 990 (e.g., SRAM, DRAM, flash memory, and / or other memory devices), a power supply 992, a driver 994, a processor 996, and / or other subsystems or components 998, generally as described above. Figures 1A to 9 The semiconductor device described may be included in Figure 9 For example, the memory 990 may be in any element shown in Figure 7A and 7B DDR5 DIMMs configured in the illustrated embodiment. The resulting system 900 can be configured to perform any of a variety of appropriate computing, processing, storage, sensing, imaging, and / or other functions. Thus, representative examples of system 900 include, but are not limited to, computers and / or other data processors, such as desktop computers, laptop computers, internet appliances, handheld devices (e.g., palmtop computers, wearable computers, cellular or mobile phones, personal digital assistants, music players, etc.), tablet computers, multi-processor systems, processor-based or programmable consumer electronics, network computers, and minicomputers. Additional representative examples of system 900 include lights, cameras, vehicles, and the like. With respect to these and other examples, system 900 can be housed in a single unit or distributed across multiple interconnected units, such as via a communications network. Components of system 900 may therefore include local and / or remote memory storage devices and any of a variety of appropriate computer-readable media.

[0066] It will be appreciated from the foregoing that although specific embodiments of the present technology have been described herein for illustrative purposes, various modifications may be made without departing from the present invention. In addition, specific aspects of the present technology described in the context of specific embodiments may also be combined or eliminated in other embodiments. For example, with reference to Figures 1A to 7B The various embodiments described may be modified to incorporate different numbers of first, second, third, and / or fourth semiconductor dies (e.g., three first dies, five first dies, six first dies, four first dies, etc.) that are correspondingly mounted at the die attach locations. Figures 1A to 8 The described selective placement methods can be applied to other semiconductor devices, such as various other generations of DIMMs and / or other memory modules. Accordingly, the present disclosure is limited only by the appended claims. Furthermore, while advantages associated with specific embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments must exhibit such advantages to fall within the scope of the present technology. Accordingly, the present invention and related technology may encompass other embodiments not explicitly shown or described herein.

Claims

1. A method for constructing an improved memory module having two or more semiconductor dies, comprising: determining a performance level of a temperature-affected operating parameter of individual semiconductor dies of the memory module at a first temperature, wherein the operating parameter is power consumption from the semiconductor die; determining the performance level of the operating parameter of the individual semiconductor die at a second temperature greater than the first temperature; identifying, based on the determined performance levels at the first temperature and the second temperature, at least one first semiconductor die that is relatively more affected by temperature at a high temperature and at least one second semiconductor die that is relatively less affected by temperature; mounting the first semiconductor die in a first array region of a memory module substrate and mounting the second semiconductor die in a second array region of the memory module substrate, wherein the first array region is cooler than the second array region during operation; and A power management integrated circuit is mounted to a central portion of the memory module substrate.

2. The method according to claim 1, further comprising: identifying a coldest die location in the first array region, the coldest die location having a lowest temperature in the first array region during operation; placing one of the first semiconductor dies in a coolest die position in the first array region; identifying a hottest die location in the second array region, the hottest die location having a highest temperature in the second array region during operation; and One of the second semiconductor dies is placed in a hottest die location in the second array region.

3. The method according to claim 1, further comprising: identifying, based on the determined performance levels at the first and second temperatures, at least one third semiconductor die that is less temperature-affected at high temperatures than the first semiconductor die and more temperature-affected at high temperatures than the second semiconductor die; and The third semiconductor die is mounted in a third array region of the memory module substrate, wherein the third array region is cooler than the second array region during operation and warmer than the first array region during operation.

4. The method according to claim 3, further comprising: identifying, based on the determined performance levels at the first and second temperatures, at least one fourth semiconductor die that is less temperature-affected at high temperatures than the third semiconductor die and more temperature-affected at high temperatures than the second semiconductor die; and The fourth semiconductor die is mounted on a fourth array region of the memory module substrate, wherein the fourth array region is cooler than the second array region during operation and warmer than the third array region during operation.

5. A memory module comprising: a substrate having a surface with a central portion, a first array region on one side of the central portion, and a second array region on an opposite side of the central portion, wherein the first array region is cooler than the second array region during operation; a first semiconductor die attached to the substrate in the first array region on the surface such that the first semiconductor die is positioned upstream of the central portion relative to airflow across the surface, wherein the first semiconductor die has a first performance level for an operating parameter affected by temperature, wherein the operating parameter is power consumption from the semiconductor die; a second semiconductor die attached to the substrate in the second array region such that the second semiconductor die is positioned downstream from the central portion relative to the airflow across the surface, wherein the second semiconductor die has a second performance level for the operating parameter indicating that the second semiconductor die operates more efficiently at high temperatures than the first semiconductor die, and wherein the first and second semiconductor die are the same type of die; and A power management integrated circuit is mounted to the central portion of the surface.

6. The memory module according to claim 5, wherein: The first semiconductor die is mounted in the first array region on the surface of the substrate in a distalmost position relative to the central portion.

7. The memory module of claim 5, wherein the second semiconductor die is mounted to the second array area on the surface of the substrate in a proximal-most position of the central portion.

8. The memory module according to claim 5, wherein: The surface is a first surface; the substrate including a second surface opposite the first surface, the second surface having a central portion, a first array region on one side of the central portion, and a second array region on an opposite side of the central portion, wherein during operation the first array region on the second surface is cooler than the second array region on the second surface; and The memory module further includes a third semiconductor die attached to the substrate at the first array area on the second surface, wherein: the third semiconductor die has a third performance level for the operating parameter indicating that the third semiconductor die operates less efficiently than the second semiconductor die at the elevated temperature, and The third semiconductor die is mounted in the first array area on the second surface of the substrate in a distalmost position relative to the central portion.

9. The memory module according to claim 5, wherein: The surface is a first surface; the substrate including a second surface opposite the first surface, the second surface having a central portion, a first array region on one side of the central portion, and a second array region on an opposite side of the central portion, wherein during operation the first array region on the second surface is cooler than the second array region on the second surface; and The memory module further includes a third semiconductor die attached to the substrate at the first array area on the second surface, wherein: the third semiconductor die having a third performance level for the operating parameter indicating that the third semiconductor die operates more efficiently than the first semiconductor die at the high temperature, and The third semiconductor die is mounted in the second array area on the second surface of the substrate in a proximal-most position relative to the central portion.

10. The memory module of claim 5, wherein the operating parameter is semiconductor data retention.

11. The memory module of claim 5, wherein the first semiconductor die is the semiconductor die most affected by temperature such that at the high temperature, the first semiconductor die has the lowest performance level for the operating parameter of any semiconductor die attached to the substrate.

12. A memory module comprising: A substrate comprising a central portion, an upstream edge, a downstream edge opposite the upstream edge, a first array region between the upstream edge and the central portion, a second array region between the downstream edge and the central portion, and a surface extending from the upstream edge to the downstream edge, wherein: the surface including one or more die attach locations in each of the first and second array regions, the upstream edge is located upstream of the central portion relative to gas flow across the substrate, and the downstream edge is located downstream of the central portion relative to the gas flow across the substrate, and a first semiconductor die attached to the surface of the substrate in a first die attach location in the first array region, wherein the first die attach location is adjacent the upstream edge; and a second semiconductor die attached to the surface of the substrate at a second die attach location in the second array region; wherein a performance indicator of an operating parameter of the first semiconductor die has a first variation based on temperature, and the performance indicator of the operating parameter of the second semiconductor die has a second variation that is less than the first variation, wherein the operating parameter is power consumption from the semiconductor die.

13. The memory module of claim 12, wherein the second die attach location is adjacent to the center portion.

14. The memory module of claim 12, wherein: The surface is a first surface; The substrate includes a second surface opposite the first surface, the second surface extending from the upstream edge to the downstream edge; and The memory module further includes a third semiconductor die attached to the second surface of the substrate at a third die attach location in the first array region, wherein the performance indicator of the operating parameter of the third semiconductor die has a third variation that is greater than the second variation.

15. The memory module of claim 12, wherein the first variation in the performance metric of the first semiconductor die is greater than the variation in the performance metric of any other semiconductor die attached to the memory module.

16. The memory module of claim 14, further comprising one or more heat generating elements attached to the central portion of the first surface.

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