Semiconductor package structure

Abstract

A semiconductor package structure includes a first dielectric layer, a bond pad having a protrusion portion protruding from the first dielectric layer, a solder bump into which the protrusion portion is embedded, and a first barrier layer interposed between the bond pad and the first dielectric layer, wherein a gap is present between the first barrier layer and the solder bump, and the bond pad is spaced apart from the first dielectric layer by the gap. Another aspect of the present invention provides a method of forming a semiconductor package structure to at least enhance the strength of the semiconductor package structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more specifically, to a semiconductor packaging structure. Background Technology

[0002] The increasing demands for functionality and miniaturization in electronic products necessitate ever-shrinking wire dimensions within a limited area (e.g., linewidth / pitch below 2µm / 2µm), especially in high-end packaging—such as 2.5D / 3D (3DIC) products. Traditional technologies (e.g., substrates) are insufficient to meet these functional and miniaturization requirements. Thinning is a highly effective method for product miniaturization, addressing the challenges of tiny wires and warpage. Traditional manufacturing methods use support designs to overcome warpage, but these methods face issues such as delamination at the interface of heterogeneous materials (e.g., glass and dielectric materials). Furthermore, thinning processes (e.g., polishing) are necessary. Additionally, the die bond precision (>2µm) offered by substrate technology is insufficient for high-end packaging; these issues remain significant challenges. Summary of the Invention

[0003] In view of the problems existing in the related technologies, the purpose of the present invention is to provide a semiconductor packaging structure and a method for forming the same, so as to at least enhance the strength of the semiconductor packaging structure.

[0004] To achieve the above objectives, the present invention provides a semiconductor package structure comprising: a first dielectric layer; a bonding pad having a protrusion extending from the first dielectric layer; a solder bump having the protrusion embedded in the solder bump; and a first barrier layer sandwiched between the bonding pad and the first dielectric layer, wherein a gap exists between the first barrier layer and the solder bump, and the bonding pad and the first dielectric layer are separated by the gap.

[0005] According to an embodiment of the present invention, it further includes: a second dielectric layer located on the side of the first dielectric layer opposite to the solder bump, wherein the portion of the second dielectric layer exposed between the bonding pad and the first dielectric layer is covered by the first barrier layer.

[0006] According to an embodiment of the present invention, the first dielectric layer has a first surface and a second surface opposite to the first surface, solder bumps are located on one side of the first surface, and the first barrier layer includes: a lateral portion covering the second surface of the first dielectric layer; and an inclined portion extending from the lateral portion and covering the peripheral sidewall of the opening for the bonding pad protrusion of the first dielectric layer, wherein the lateral portion is in direct contact with the second dielectric layer, and the gap is located at the extended end of the inclined portion.

[0007] According to an embodiment of the present invention, the protrusion direction of the protrusion is downward relative to the first dielectric layer, and the entire solder bump is located below the first dielectric layer.

[0008] According to an embodiment of the present invention, the surface of the first barrier layer facing the solder bump is concave, and the concave surface constitutes part of the boundary surface of the void.

[0009] According to an embodiment of the present invention, the gap is arranged in a continuous ring around the solder bump.

[0010] According to an embodiment of the present invention, the bonding pad is a Cu layer, the first barrier layer is a Ti layer, and the first dielectric layer is a PI layer.

[0011] According to an embodiment of the present invention, the solder bump is a solder ball.

[0012] This application also provides a semiconductor package comprising: a redistribution layer including: a dielectric layer; a bonding pad having a peripheral edge in the dielectric layer and a central portion surrounded by the peripheral edge, the central portion protruding downward beyond the bottom surface of the dielectric layer; a chip located above the redistribution layer and electrically connected to the bonding pad; solder bumps, the central portion of the bonding pad being partially embedded in the solder bumps; and a first barrier layer, wherein the lower surface of the bonding pad is spaced from the dielectric layer by the first barrier layer and a gap, wherein the gap is adjacent to the first barrier layer and the gap spaces the solder bump from the dielectric layer.

[0013] According to an embodiment of the present invention, it further includes: a molding material located above the dielectric layer and covering the chip.

[0014] According to an embodiment of the present invention, a second barrier layer and a metal layer are sequentially stacked on the bonding pad from bottom to top. The chip is electrically connected to the metal layer. A portion of the second barrier layer conformally contacts the middle portion of the bonding pad, while another portion of the second barrier layer contacts the dielectric layer. The second barrier layer and the metal layer are conformally connected.

[0015] According to an embodiment of the present invention, it further includes: a filler material located between the chip and the metal layer, and microbumps embedded in the filler material, wherein the chip and the metal layer are electrically connected through the microbumps.

[0016] According to an embodiment of the present invention, the dielectric layer includes a first dielectric layer and a second dielectric layer located on the first dielectric layer, a first barrier layer is located between the bonding pad and the first dielectric layer, the first barrier layer has an exposed portion that is exposed relative to the bonding pad and the first dielectric layer, wherein one end of the exposed portion is in direct contact with the second dielectric layer, and the other end is adjacent to the gap.

[0017] According to an embodiment of the present invention, the first dielectric layer is a passivation layer, and the maximum thickness of the redistribution layer is less than 20 μm.

[0018] This application also provides a method for forming a semiconductor package structure, comprising: forming a conformal first barrier layer and a bonding pad sequentially from bottom to top in a first dielectric layer above a carrier; bonding and electrically connecting a chip to the top of the bonding pad; after removing the carrier, thinning a portion of the first dielectric layer so that the first barrier layer and the bonding pad protrude from the first dielectric layer; removing a portion of the first barrier layer to expose the bonding pad and causing the first barrier layer to be recessed into the first dielectric layer, thereby forming a gap between the bonding pad and the first dielectric layer; forming solder bumps that are in contact with the exposed bonding pads; wherein the solder bumps are spaced apart from the first barrier layer and from the first dielectric layer by the gaps.

[0019] According to an embodiment of the present invention, bonding and electrically connecting a chip to a bonding pad includes: forming a patterned second dielectric layer over a first dielectric layer, the patterned second dielectric layer having an opening that exposes the bonding pad; sequentially forming a conformal second barrier layer and a metal layer in the opening; and bonding and electrically connecting the chip to the metal layer.

[0020] According to an embodiment of the present invention, a molding material for covering the chip is formed over the second dielectric layer before the carrier is removed and after the chip is bonded and electrically connected to the metal layer.

[0021] According to an embodiment of the present invention, microbumps are used to electrically connect the chip and the metal layer, wherein the microbumps are surrounded by a filler material between the chip and the metal layer.

[0022] According to an embodiment of the present invention, the entire solder bump is located below the bottom surface of the first dielectric layer.

[0023] According to an embodiment of the present invention, in the step of forming solder bumps, the interface between the formed solder bumps and the bonding pads is a discontinuous plane.

[0024] According to an embodiment of the present invention, the interface between the solder bump and the bonding pad is concave.

[0025] The beneficial technical effects of this invention are as follows:

[0026] The bonding pads and solder bumps in this application are not continuous planes, making peeling less likely; a barrier layer is provided between the bonding pads and the dielectric layer to prevent peeling due to weak adhesion between the bonding pads and the dielectric layer; gaps are provided between the bonding pads and the dielectric layer to enhance the strength of the semiconductor packaging structure. Attached Figure Description

[0027] Figures 1 to 20 A cross-sectional view is shown of an intermediate stage in forming a semiconductor package structure according to some embodiments.

[0028] Figure 21Illustrations are shown according to some embodiments Figure 20 A magnified view of a portion of the semiconductor packaging structure.

[0029] Figures 22 to 28 Cross-sectional views of semiconductor package structures according to different embodiments are shown.

[0030] Figure 29 The process flow for forming a semiconductor package structure is shown according to some embodiments. Detailed Implementation

[0031] To better understand the spirit of the embodiments of this application, the following description is based on some preferred embodiments of this application.

[0032] Embodiments of this application will be described in detail below. Throughout this specification, identical or similar components and components having identical or similar functions are indicated by similar reference numerals. The embodiments described herein with reference to the accompanying drawings are illustrative and diagrammatic in nature and are intended to provide a basic understanding of this application. The embodiments of this application should not be construed as limiting this application.

[0033] As used herein, the terms “approximately,” “generally,” “substantially,” and “about” are used to describe and indicate small variations. When used in conjunction with an event or situation, the terms may refer to examples in which the event or situation occurred precisely and examples in which the event or situation occurred very approximately. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the two values ​​can be considered "substantially" the same.

[0034] In this specification, unless otherwise specified or limited, relative terms such as “central,” “longitudinal,” “lateral,” “front,” “rear,” “right,” “left,” “inner,” “outer,” “lower,” “higher,” “horizontal,” “vertical,” “above,” “below,” “above,” “below,” “top,” “bottom,” and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) should be interpreted as referring to the directions described in the discussion or depicted in the accompanying drawings. These relative terms are used for descriptive convenience only and do not require that this application be constructed or operated in a particular orientation.

[0035] Additionally, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that such range format is for convenience and brevity and should be interpreted flexibly to include not only the numerical values ​​explicitly specified as range limits, but also all individual numerical values ​​or subranges covered within the range, as if each numerical value and subrange were explicitly specified.

[0036] Furthermore, for ease of description, "first," "second," "third," etc., can be used in this article to distinguish different components of a figure or a series of figures. "First," "second," "third," etc., are not intended to describe the corresponding components.

[0037] Using substrate technology in the fabrication of semiconductor packaging structures presents several challenges: the need for thinning processes (such as polishing) leads to high manufacturing costs and long cycle times; the coarser texture of substrate technology compared to the raised surfaces used in microbump pad fabrication results in lower chip bonding tolerances. In traditional designs, it is difficult to achieve fine-pitch connections, such as: redistribution layer (RDL) thicknesses below 100µm (including solder mask); linewidth / pitch (L / S) designs below 2µm / 2µm; and microbump (uBump) pitches below 100µm. Furthermore, existing designs require support structures (such as glass films) to prevent structural warping, and delamination at the interface between organic and inorganic layers is common in current designs.

[0038] While the cost of bumping technology is slightly higher than that of substrate technology, it allows for the creation of smaller wires, thinner structures, and a greater number of connection points. Bumping technology is clearly the preferred choice for products with functional and miniaturized requirements, and its advantages have been favored, valued, and widely utilized by the industry.

[0039] This application provides a high-bonding semiconductor package structure fabricated using bump technology, offering a solution to the aforementioned challenges, including increased number of connection points, reduced conductor linewidth / spacing, increased connection point precision, and structural thinning.

[0040] In existing packaging structures, the bonding pads and solder bumps are prone to peeling at the joint. After testing, especially after the heating effect, cracks are easily generated in the solder bumps of existing packaging structures.

[0041] The semiconductor packaging structure and formation process of this application will be further described below with reference to the accompanying drawings.

[0042] See Figure 1 Ti seed layer 12 and Cu seed layer 14 are formed by spraying on the carrier 10, which can be glass.

[0043] See Figure 2 The first dielectric layer 20 is further printed over the Cu seed layer 14. The first dielectric layer 20 can be a polyamide (PA) layer or a polyimide (PI) layer. A first exposure process 101 is then performed to cure the first dielectric layer 20. In embodiments, the first dielectric layer 20 can be an organic material passivated using liquid or thin film, such as bismaleimide-triazine (BT), Ajinomoto build-up film (ABF), polyimide (PI), solder resist ink, or photosensitive and / or photosensitive liquid and / or dry film epoxy resin. The first dielectric layer 20 can also be a deposited inorganic material, such as oxides (SiOx, SiNx, TaOx), glass, silicon, ceramics, etc.

[0044] See Figure 3 A portion of the first dielectric layer 20 is removed, and a first barrier layer 30 is deposited in a blanket manner. In one embodiment, the first barrier layer 30 may be a Ti seed layer. The first barrier layer 30 is conformally formed with the first dielectric layer 20. In an embodiment, the first barrier layer 30 has a thickness between 1 μm and 5 μm. The adhesion strength between the first barrier layer 30 and the first dielectric layer 20 is greater than the adhesion strength between the bonding pad 50 and the first dielectric layer 20. The use of the first barrier layer 30 increases the external forces (e.g., thermal stress) that the structure can withstand. In an embodiment, the first barrier layer 30 may also be made of Ni, W, Pt, alloys, etc.

[0045] See Figure 4 A photoresist (PR) layer 40 is formed on the first barrier layer 30, and a second exposure process 201 is performed to cure the photoresist (PR) layer 40.

[0046] See Figure 5An opening is formed in the PR layer 40 to expose the first barrier layer 30, and a bonding pad 50 is formed in the opening. In one embodiment, the bonding pad 50 is formed by plating Cu. The first barrier layer 30 prevents metal in the bonding pad 50 from migrating outward.

[0047] See Figure 6 Remove PR layer 40 and etch a portion of the first barrier layer 30 covered by PR layer 40. Due to the etch anisotropy between bonding pad 50 and the first barrier layer 30, another portion of the first barrier layer 30 covered by bonding pad 50 is not etched.

[0048] See Figure 7 A second dielectric layer 70 is formed, covering the first dielectric layer 20, the first barrier layer 30, and the bonding pad 50. The second dielectric layer 70 surrounds the exposed sidewalls of the first barrier layer 30 and the bonding pad 50. The bonding pad 50 is not in contact with the first dielectric layer 20. In embodiments, the thickness of the second dielectric layer 70 is in the range of 5 μm to 20 μm. In embodiments, the second dielectric layer 70 can be an organic material passivated using liquid or thin film, such as bismaleimide-triazine (BT), Ajinomoto build-up film (ABF), polyimide (PI), solder resist ink, photosensitive and / or photosensitive liquid and / or dry film epoxy resin, etc.; the second dielectric layer 70 can also be a deposited inorganic material, such as oxides (SiOx, SiNx, TaOx), glass, silicon, ceramics, etc.

[0049] See Figure 8 A portion of the second dielectric layer 70 is removed to expose the bonding pad 50, and a second barrier layer 80 is deposited. The sidewalls of the downwardly recessed portion of the second barrier layer 80 contact the bonding pad 50 and the second dielectric layer 70. In an embodiment, the second barrier layer 80 has a thickness between 0.2 μm and 0.5 μm.

[0050] See Figure 9 A second photoresist (PR) layer 90 is deposited over the second barrier layer 80, and a third exposure process 301 is performed to cure the second photoresist (PR) layer 90.

[0051] See Figure 10The second photoresist (PR) layer 90 is etched to expose a portion of the second barrier layer 80. A metal layer 100 is deposited on the exposed portion of the second barrier layer 80; in this embodiment, the metal layer 100 may be a Cu layer. The second barrier layer 80 prevents Cu diffusion in the metal layer 100. In this embodiment, the linewidth / spacing of the metal layer 100 is in the range of 2 μm / 2 μm to 3 μm / 3 μm, and the metal layer 100 has a thickness between 2 μm and 3 μm. The metal layer 100 and the bonding pad 50 together constitute a via structure. The first barrier layer 30 and the second barrier layer 80 prevent the formation of intermetallic compounds, avoiding damage to the strength and stability of the via structure and improving product reliability. The bonding pad 50, the second barrier layer 80, and the metal layer 100 are all convex structures, so that the contact surfaces between them are not planar but rather overlapping surfaces, increasing the adhesion of the structure.

[0052] See Figure 11 The remaining second photoresist (PR) layer 90 is removed, and a portion of the second barrier layer 80 covered by the PR layer 90 is removed, leaving the conformal second barrier layer 80 and the metal layer 100.

[0053] See Figure 12 The chip 120 is bonded to the metal layer 100 via microbumps 122, and capillary bottom filler (CUF) 124 fills the space between the chip 120 and the metal layer 100. The capillary bottom filler (CUF) 124 surrounds the microbumps 122.

[0054] See Figure 13 The chip 120 is encapsulated using a molding material 130, which in this embodiment may be a compound dielectric (CPD). The molding material 130 is bonded to the second dielectric layer 70.

[0055] See Figure 14 The carrier 10 is separated from the Ti seed layer 12 to remove the carrier 10.

[0056] See Figure 15 The Ti seed layer 12 is etched using a first chemical etching process 401. Due to the etching anisotropy between the Ti seed layer 12 and the Cu seed layer 14, the etchant used in the first chemical etching process 401 etches the Ti seed layer 12 while retaining the Cu seed layer 14.

[0057] See Figure 16 The second chemical etching process 501 is performed to remove the Cu seed layer 14.

[0058] See Figure 17 The first dielectric layer 20 is etched by the third chemical etching process 601.

[0059] See Figure 18The third chemical etching process 601 thins the first dielectric layer 20, causing the first barrier layer 30 and the bonding pad 50 to protrude relative to the first dielectric layer 20. After thinning the first dielectric layer 20, a fourth chemical etching process 701 is performed to etch portions of the first barrier layer 30.

[0060] See Figure 19 The fourth chemical etching process 701 causes the first barrier layer 30 to be recessed relative to the first dielectric layer 20, thereby exposing the protrusion 502 of the bonding pad 50. The recessed first barrier layer 30 forms a void 192 surrounding the bonding pad 50. The bonding pad 50 protrudes relative to the first dielectric layer 20. The redistribution layer 190 includes the first dielectric layer 20, the second dielectric layer 70, the bonding pad 50, the first barrier layer 30, the metal layer 100, and the second barrier layer 80, and the maximum thickness of the redistribution layer 190 is less than 20 μm. No additional reinforcement / support elements are required in the redistribution layer 190. Exposing the bonding pad 50 only partially relative to the first dielectric layer 20 facilitates the thinning of the redistribution layer 190.

[0061] See Figure 20 Solder bumps 200 engage exposed bonding pads 50. A dicing process 801 is performed to form a semiconductor package 2000. Solder bumps 200 only contact bonding pads 50, and gaps 192 are located between solder bumps 200 and the first barrier layer 30. In an embodiment, solder bumps 200 are solder balls, and multiple solder bumps 200 form a ball grid array (BGA).

[0062] Figure 21 It shows Figure 20 The dashed line portion representing the engagement between the solder bump 200 and the bonding pad 50 is an enlarged view in one embodiment. The first barrier layer 30 is recessed relative to the first dielectric layer 20, and the bonding pad 50 protrudes relative to the first dielectric layer 20. The bonding pad 50 is embedded in the solder bump 200 such that the interface between the bonding pad 50 and the solder bump 200 is not planar. In this embodiment, the diameter d of the lowest bottom surface of the bonding pad 50 is between 10 μm and 80 μm. The solder bump 200 does not contact the first dielectric layer 20 or the second dielectric layer 70, preventing the formation of an intermetallic compound (IMC) between the solder bump 200 and the dielectric layers, thus enhancing the strength and reliability of the structure. In this embodiment, the entire solder bump 200 is lower than the bottom surface of the first dielectric layer 20; therefore, the interface between the bonding pad 50 and the solder bump 200 is lower than the bottom surface of the first dielectric layer 20.

[0063] Combination Figure 20 and Figure 21The semiconductor package structure 2000 of this application embodiment includes a first dielectric layer 20 and a bonding pad 50, the bonding pad 50 having a protrusion 502 protruding from the first dielectric layer 20. The semiconductor package structure 2000 also includes solder bumps 200, with the protrusion 502 embedded in the solder bumps 200. The semiconductor package structure 2000 also includes a first barrier layer 30 sandwiched between the bonding pad 50 and the first dielectric layer 20, with a gap 192 between the first barrier layer 30 and the solder bumps 200, and the bonding pad 50 and the first dielectric layer 20 being separated by the gap 192. In this embodiment, a second dielectric layer 70 is also included, located on the side of the first dielectric layer 20 facing away from the solder bumps 200, and the portion 702 of the second dielectric layer 70 exposed between the bonding pad 50 and the first dielectric layer 20 is covered by the first barrier layer 30. In one embodiment, the first dielectric layer 20 has a first surface 202 and a second surface 204 opposite to the first surface 202. Solder bumps are located on one side of the first surface 202. The first barrier layer 30 includes: a lateral portion 302 covering the second surface 204 of the first dielectric layer; and an inclined portion 304 extending from the lateral portion 302 and covering the peripheral sidewall of the opening for the protruding bonding pad 50 of the first dielectric layer 20. The lateral portion 302 is in direct contact with the second dielectric layer 70, and the gap 192 is located at the extended end of the inclined portion 304. In another embodiment, the protrusion direction of the protrusion 502 is downward relative to the first dielectric layer 20, i.e., it protrudes sequentially beyond the second surface 204 and the first surface 202 toward the solder bump 200. The entire solder bump 200 is located below the first dielectric layer 20. In one embodiment, the surface of the first barrier layer 30 facing the solder bump 200 is concave 306, which forms part of the boundary surface of the gap 192. In another embodiment, the gap 192 is arranged in a continuous ring around the solder bump 200. In another embodiment, the bonding pad 50 is a Cu layer, the first barrier layer 30 is a Ti layer, and the first dielectric layer 20 is a PI layer. In yet another embodiment, the solder bump 200 is a solder ball.

[0064] The semiconductor package 2000 of this application embodiment includes a redistribution layer 190. The redistribution layer 190 includes a dielectric layer 75 (including a first dielectric layer 20 and a second dielectric layer 70) and a bonding pad 50. The bonding pad 50 has a peripheral edge 504 located in the dielectric layer 75 and a central portion 502 (i.e., a protrusion 502) surrounded by the peripheral edge 504, the central portion 502 protruding downward beyond the bottom surface 202 of the dielectric layer 75 (i.e., the first surface 202 of the first dielectric layer 20). The semiconductor package 2000 also includes a chip 120 located above the redistribution layer 190 and electrically connected to the bonding pad 50. The semiconductor package 2000 also includes solder bumps 200, with the central portion 502 of the bonding pad 50 partially embedded in the solder bumps 200. The semiconductor package 2000 further includes a first barrier layer 30, wherein the lower surface of the bonding pad 50 is spaced from the dielectric layer 75 by the first barrier layer 30 and a gap 192, wherein the gap 192 is adjacent to the first barrier layer 30 and spaces the solder bump 200 from the dielectric layer 75. In an embodiment, the semiconductor package 2000 further includes a molding material 130 located above the dielectric layer 75 and covering the chip 120. In an embodiment, a second barrier layer 80 and a metal layer 100 are sequentially stacked on the bonding pad 50 from bottom to top, the chip 120 is electrically connected to the metal layer 100, a portion of the second barrier layer 80 conformally contacts the middle portion 502 of the bonding pad 50, and another portion of the second barrier layer 80 contacts the dielectric layer 75, the second barrier layer 80 and the metal layer 100 being conformally connected. In one embodiment, the semiconductor package 2000 further includes a filler material 124 and microbumps 122. The filler material 124 is located between the chip 120 and the metal layer 100, and the microbumps 122 are embedded in the filler material 124. The chip 120 and the metal layer 100 are electrically connected through the microbumps 122. In another embodiment, the dielectric layer 75 includes a first dielectric layer 20 and a second dielectric layer 70 located on the first dielectric layer 20. A first barrier layer 30 is located between the bonding pad 50 and the first dielectric layer 20. The first barrier layer 30 has an exposed portion that is exposed relative to the bonding pad 50 and the first dielectric layer 20. One end 308 of the exposed portion is in direct contact with the second dielectric layer 70, and the other end 306 (i.e., a concave surface) is adjacent to the gap 192. In another embodiment, the first dielectric layer 20 is a passivation layer, and the maximum thickness of the redistribution layer 190 is less than 20 μm.

[0065] Figure 22 A schematic diagram of a semiconductor package structure 2200 according to another embodiment of this application is shown, wherein a plurality of solder bumps 220 form a platform grid array (LGA).

[0066] Figure 23 A schematic diagram of a semiconductor package structure 2300 according to another embodiment of this application is shown, wherein the solder bumps 230 are formed as solder pillars.

[0067] Figure 24 A schematic diagram of a semiconductor package structure 2400 according to another embodiment of this application is shown, wherein a planarization process is used to form a molding material 130 flush with the top surface of the chip 120.

[0068] Figure 25 A schematic diagram of a semiconductor packaging structure 2500 according to another embodiment of this application is shown, wherein the molding material 130 is formed to encapsulate the chip 120 and is not in contact with the second dielectric layer 70.

[0069] Figure 26 A schematic diagram of a semiconductor package structure 2600 according to another embodiment of this application is shown, wherein a redistribution layer 260 with multiple layers is used. Compared to the redistribution layer 190, the redistribution layer 260 includes more dielectric layers and interconnect structures.

[0070] Figure 27 A schematic diagram of a semiconductor package structure 2700 according to another embodiment of this application is shown, wherein a lead 270 is used to connect the chip 120 and the metal layer 100.

[0071] Figure 28 A schematic diagram of a semiconductor package structure 2800 according to another embodiment of this application is shown, wherein the bonding pad 50 is embedded more deeply into the solder bump 200 than in other embodiments.

[0072] Figure 29 A flowchart illustrating a method for forming a semiconductor package structure in an embodiment is shown. In step 2901, specifically as follows... Figures 1 to 6 As shown, in the first dielectric layer 20 above the carrier 10, a conformal first barrier layer 30 and a bonding pad 50 are formed sequentially from bottom to top. In step 2902, specifically as follows... Figures 7 to 13 As shown, chip 120 is bonded and electrically connected above bonding pad 50. In step 2903, specifically as follows... Figures 14 to 18 As shown, after removing the carrier 10, a portion of the first dielectric layer 20 is thinned so that the first barrier layer 30 and the bonding pad 50 protrude from the first dielectric layer 20. In step 2904, specifically as follows... Figure 19 As shown, a portion of the first barrier layer 30 is removed to expose the bonding pad 50 and to recess the first barrier layer 30 into the first dielectric layer 20, thereby forming a gap 192 between the bonding pad 50 and the first dielectric layer 20. In step 2905, specifically as follows... Figure 20As shown, solder bumps 200 are formed, and the solder bumps 200 are in contact with exposed bonding pads 50. In an embodiment, the solder bumps 200 and the first barrier layer 30, as well as the solder bumps 200 and the first dielectric layer 20, are spaced apart by gaps 192. In an embodiment, the step of bonding and electrically connecting the chip 120 to the bonding pads 50 includes: see [link to previous section] Figure 7 and Figure 8 A second dielectric layer 70 is formed above the first dielectric layer 20 and patterned. The patterned second dielectric layer 70 has openings that expose the bonding pads 50. See also Figures 9 to 11 A conformal second barrier layer 80 and a metal layer 100 are sequentially formed in the opening; see also Figure 12 The chip 120 is bonded and electrically connected to the metal layer 100. In an embodiment, see [link to embodiment]. Figure 13 Before removing the carrier 10, and after bonding and electrically connecting the chip 120 to the metal layer 100, a molding material 130 covering the chip 120 is formed over the second dielectric layer 70. In an embodiment, see [reference needed]. Figure 12 Microbumps 122 are used to electrically connect chip 120 and metal layer 100, wherein microbumps 122 are surrounded by filler material 124 between chip 120 and metal layer 100. In an embodiment, the entire solder bump 200 is located below the bottom surface 202 (i.e., the first surface 202) of the first dielectric layer 20. In an embodiment, during the step of forming solder bump 200, the interface between the formed solder bump 200 and the bonding pad 50 is a discontinuous plane, and the interface is a concave surface.

[0073] The embodiments of this application use bump technology, avoiding the high costs and small tolerances associated with thinning processes such as grinding, and achieving finer pitches than conventional designs. The use of the first barrier layer 30 and the design of the gap 192 prevent the solder bumps 200 from contacting the dielectric layer 75, enhancing the strength and reliability of the structure.

[0074] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor package structure, comprising: comprises: a first dielectric layer; a bonding pad having a protruding portion protruding from the first dielectric layer; a solder bump into which the protruding portion is embedded; and a first barrier layer interposed between the bonding pad and the first dielectric layer, wherein a gap is present between the first barrier layer and the solder bump, and the bonding pad is spaced apart from the first dielectric layer by the gap. Further comprising:

2. The semiconductor package structure of claim 1, wherein, a second dielectric layer on a side of the first dielectric layer facing away from the solder bump, wherein a portion of the second dielectric layer exposed between the bonding pad and the first dielectric layer is covered by the first barrier layer.

3. The semiconductor package structure according to claim 2, wherein the first dielectric layer has a first surface and a second surface opposite to the first surface, and the solder bump is located on a side of the first surface, the first barrier layer comprises: a lateral portion covering the second surface of the first dielectric layer; and an inclined portion extending from the lateral portion and covering a circumferential wall of an opening of the first dielectric layer for the protruding portion of the bonding pad to protrude, wherein the lateral portion is in direct contact with the second dielectric layer, and the gap is present at an extending end of the inclined portion.

4. The semiconductor package structure according to claim 1, wherein the protruding portion protrudes downward relative to the first dielectric layer, and the entire solder bump is located below the first dielectric layer.

5. The semiconductor package structure according to claim 1, wherein a surface of the first barrier layer facing the solder bump is concave, and the concave surface constitutes a part of a boundary surface of the gap.

6. The semiconductor package structure according to any one of claims 1-5, wherein the gap is arranged in a continuous ring around the solder bump. Further comprising:

7. The semiconductor package structure of claim 2, wherein, a redistribution layer including the first dielectric layer, the second dielectric layer, and the bonding pad, the bonding pad having a peripheral edge located in the first dielectric layer, and a middle portion surrounded by the peripheral edge, the middle portion protruding downward beyond a bottom surface of the second dielectric layer; a chip located above the redistribution layer and electrically connected to the bonding pad, wherein the middle portion of the bonding pad is partially embedded into the solder bump, the gap and the first barrier layer are in abutment with each other, and the gap separates the solder bump from the first dielectric layer.

8. The semiconductor package structure according to claim 7, wherein a second barrier layer and a metal layer are sequentially stacked on the bonding pad from bottom to top, and the chip is electrically connected to the metal layer, a portion of the second barrier layer is conformally in contact with the middle portion of the bonding pad, and another portion of the second barrier layer is in contact with the second dielectric layer, and the second barrier layer and the metal layer are conformal. Further comprising:

9. The semiconductor package structure of claim 8, wherein, a filling material located between the chip and the metal layer, a micro bump embedded in the filling material, and the chip and the metal layer are electrically connected through the micro bump.

10. The semiconductor package structure according to claim 7, wherein ​ The first barrier layer has an exposed portion exposed compared to the bonding pad and the first dielectric layer, Wherein, one end of the exposed portion is in direct contact with the second dielectric layer, and the other end is in abutment with the gap together.

Images