Systems and methods for warp detection in a cmos bonded array

Abstract

A system and method for warp detection in a CMOS bonded array includes a conductor positioned between bonding contact pads of a first wafer and a second wafer. The conductor is connected to a continuity check circuit. If the continuity check circuit detects a break in the electrical conductivity of the conductor, the break indicates the presence of warp in the first wafer and / or the second wafer. In one embodiment, the conductor is a serpentine structure.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 082,051, filed September 23, 2020, which is incorporated herein by reference. Background Technology

[0003] Memory wafers and complementary metal-oxide-semiconductor (CMOS) wafers containing control circuitry for the memory can be fabricated separately and then bonded together. The resulting structure is called a CMOS bonding array. Warping in any one or both of the wafers can cause the bonding between the opposing contact pads to break, rendering the die unusable. Attached Figure Description

[0004] Figure 1 The diagram shows an integrated circuit used in an embodiment.

[0005] Figure 2A A diagram illustrating an embodiment of an integrated circuit with recessed warping in a wafer.

[0006] Figure 2B A diagram illustrating an embodiment of a protruding warp in a chip.

[0007] Figure 3 A diagram of an integrated circuit including a continuity check circuit and a serpentine conductor.

[0008] Figure 4 The diagram illustrates the first and second portions of the serpentine conductor in the embodiment.

[0009] Figure 5 A flowchart illustrating an embodiment of a method for manufacturing a first portion of a conductor in a first wafer.

[0010] Figure 6 A flowchart illustrating an embodiment of a method for manufacturing a second portion of a conductor in a second wafer.

[0011] Figure 7 The diagram illustrates the unbroken conductor of the embodiment, indicating no warping.

[0012] Figure 8 The diagram illustrates the broken conductor of the embodiment, indicating warping.

[0013] Figure 9A The diagram illustrates an embodiment in which a serpentine conductor extends across multiple regions in the first and second wafers.

[0014] Figure 9B The diagram illustrates an embodiment in which multiple serpentine conductors extend across multiple regions in the first and second wafers.

[0015] Figure 10 A diagram illustrating an embodiment of a serpentine conductor extending through an array die and a CMOS die.

[0016] Figure 11 A diagram illustrating an embodiment of a serpentine conductor extending through an array wafer and a CMOS wafer. Detailed Implementation

[0017] By way of introduction, the following embodiments provide a design-for-test (DFT) structure for detecting die / wafer warpage in a complementary metal-oxide-semiconductor (CMOS) junction array (CBA). In one example, the DFT structure is configured as a serpentine structure extending adjacent to a critical signal or group of critical signals. The serpentine structure spans the CMOS wafer and the array wafer and connects to continuity inspection circuitry. In the event of warpage, one or more junctions in the serpentine structure do not conduct, which facilitates the detection of die / wafer warpage. The serpentine structure can be embodied as a single large conductor spanning the entire die / wafer or multiple separate conductors spanning various regions of the die / wafer.

[0018] Now turn to diagrams, Figure 1 A diagram illustrating the integrated circuit 100 of an embodiment. (See diagram for example.) Figure 1 As shown, the integrated circuit 100 includes a first wafer 10 and a second wafer 20, each having a corresponding plurality of contact pads 1, 2, 3, 4, 5. The first wafer 10 and the second wafer 20 can take any suitable form. For example, in this embodiment, the first wafer 10 includes a memory array (here, a NAND memory array), and the second wafer includes peripheral circuitry for the memory array (here, implemented as a complementary metal-oxide-semiconductor (CMOS) wafer). The peripheral circuitry may include, for example, transistors, logic signals, and circuitry for controlling and driving the memory elements to perform functions such as programming and reading. It should be noted that these are merely examples, and other embodiments may be used.

[0019] The first wafer 10 and the second wafer 20 can be manufactured separately and then joined together by bonding a plurality of contact pads 1, 2, 3, 4, 5 of each of the wafers 10, 20 together. When the corresponding plurality of contact pads 1, 2, 3, 4, 5 are joined together, they form a plurality of pillars 30. The resulting integrated circuit can produce a single memory die or multiple memory dies that can be diced to produce individual memory dies. Because a wafer can contain one or more dies, the term “wafer” as used herein is intended to broadly refer to an individual memory die or multiple memory dies.

[0020] Warping of one or both of chips 10 and 20 can result in a faulty or malfunctioning memory die. For example, Figure 2AThis illustrates a concave warping in the first wafer 10, which causes a break in the continuity of the outermost contact pad, and Figure 2B The diagram shows a protruding warp in the first wafer 10, which breaks the continuity of the innermost contact pad. Although not shown, a second wafer 20 may have warping in addition to or in place of the first wafer 10. Disadvantageously, it may be difficult or impossible to detect warping in one or both of the wafers 10 and 20.

[0021] The following examples can be used to solve this problem. For example... Figure 3 As shown, in one embodiment, integrated circuit 100 includes a conductor 40 positioned within a first wafer 10 and a second wafer 20 and positioned between at least some of a plurality of pillars 30. In this example, the conductor 40 extends in a serpentine shape through the first wafer 10 and the second wafer 20 and extends between the plurality of pillars 30 (e.g., adjacent to important signals or groups of important signals). In other examples, the conductor 40 has different shapes.

[0022] like Figure 4 As shown, in this embodiment, conductor 40 includes a first portion 42 formed in the first wafer 10 and a second portion 46 formed in the second wafer 20. Here, the first portion 42 and the second portion 46 include corresponding horizontal components 43, 47 and vertical components 44, 48. In this embodiment, the ends of the vertical components 44, 48 are at the same height as the contact pads 1, 2, 3, 4, 5. Therefore, the ends of the vertical components 44, 48 are engaged together at the same time as the contact pads 1, 2, 3, 4, 5 are engaged together.

[0023] In this embodiment, the horizontal components 43 and 47 are metal-filled trenches, and the vertical components 44 and 48 are metal-filled vertical interconnect channel structures (through holes). Figure 5 A flowchart 500 illustrates an embodiment of a method for manufacturing a horizontal component 43 and a vertical component 44 in a first portion 42 of a conductor 40 in a first wafer 10. Figure 5 As shown, firstly, an array of serpentine trenches is formed (Action 510). Next, the trenches are filled with a metal such as copper (Cu), tungsten (W), or aluminum (Al) (Action 520). Next, an array of metal contact patterns is formed (Action 530). Then, an array of vertical serpentine vias is formed (Action 540), and the vias are filled with metal (Action 550). Next, the first wafer 10 is prepared for bonding with the second wafer 20 (Action 560).

[0024] Figure 6 A flowchart 600 illustrates an embodiment of a method for manufacturing horizontal components 47 and vertical components 48 in a second portion 46 of a conductor 40 in a second wafer 20. Figure 6As shown, firstly, a CMOS serpentine trench is formed (Action 610). Next, the trench is filled with metal (Action 620). Next, a CMOS metal contact pattern is formed (Action 630). Then, a CMOS vertical serpentine via is formed (Action 640), and the via is filled with metal (Action 650). Next, the second wafer 20 is prepared to be bonded to the first wafer 10 (Action 660).

[0025] Return to Figure 3 In this embodiment, the integrated circuit 100 further includes a continuity check circuit 50 electrically coupled to the conductor 40 and configured to detect warping in the first wafer 10 and / or the second wafer 20 by detecting a break in the conductivity of the conductor 40. In this embodiment, the continuity check circuit 50 is located in the second wafer 20; however, the continuity check circuit 50 may be located elsewhere in other embodiments.

[0026] like Figure 7 As shown, when the ends of all the vertical components of the first portion 42 and the second portion 46 of conductor 40 are joined together, a complete circuit with a continuity check circuit 50 is formed. That is, the absence of any interruption in conductor 40 allows current to flow between the positive and negative contacts of the continuity check circuit 50. However, as... Figure 8 As shown, when warping occurs in one of the wafers (here, the first wafer 10, but warping can occur in the second wafer 20 instead of the first wafer 10 or in addition to the first wafer), the connection between at least one of contacts 1, 2, 3, 4, 5 and the vertical portion of conductor 40 near those contacts breaks, meaning that at least one of the joints of conductor 40 will not be conductive. This results in one or more discontinuities 60 in conductor 40, which prevents current from flowing between the positive and negative contacts of the continuity check circuit 50 due to the break in conductivity of conductor 40. That is, if the bonding pads or wire traces are damaged, which is likely to occur in the case of wafer warping, the broken joint will become more resistive (or open circuit). Therefore, this current interruption, as detected by the continuity check circuit 50, can indicate warping.

[0027] Conductor 40 can be arranged across wafers 10, 20 in any suitable manner. For example, as... Figure 9A As shown, in one embodiment, a single conductor 40 extends across the entire wafer 10, 20 (e.g., in an up-and-down Z-shaped pattern), with the upper half of conductor 40 in the first wafer 10 and the lower half in the second wafer 20. Therefore, if wafers 10, 20 have multiple regions, a single conductor 40 may extend across some or all of those regions. Figure 9BIn another embodiment shown, multiple conductors are used across wafers 10 and 20, each conductor extending across one of multiple regions 72, 74, 76, and 78 in the first wafer 10 and the second wafer 20. In this example, the multiple regions 72, 74, 76, and 78 are a high-voltage region 72, a word line (WL) region 74, a bit line (BL) region 76, and a decoded address region 78. These are merely examples, and other regions may be used. Using multiple conductors avoids routing an excessively long conductor across the entire chip. In yet another alternative, one or more conductors may be positioned close to important / critical signals, such as, but not limited to, Vcc signals, high-voltage programming / erasing signals, and address decoding signals.

[0028] As mentioned above, these embodiments can be used to detect warping within a die or wafer. Figure 10 This diagram illustrates warp detection within array die 80 and / or CMOS die 85. In this example, there are N pillars and N regions. If, for example, pillar 1 breaks, the signal in region 1 will likely also break. Figure 11 This diagram illustrates warp detection within array wafer 90 and / or CMOS wafer 95. In this example, there are N pillars and N regions. If, for example, pillar 8 breaks, the die in region 8 will likely also break.

[0029] In operation, these embodiments can be used to perform continuous testing in the initial stages of the testing process. This allows for early detection of warpage during testing, saving time. Therefore, this DFT structure provides resolution inspection that impacts the reliability of the die in the field. Without this structure, it would be extremely difficult (if not impossible) to test all contacts in wafers 10, 20.

[0030] Many alternatives exist that can be used with these embodiments. For example, the serpentine structure can be used in the channels and alleys (cut areas) between dies so as not to occupy silicon areas (assuming there are test steps to read them out). Moreover, these embodiments can be used for connectivity / resistivity testing instead of or in addition to continuity testing. Poor contacts can be checked for continuity, but they are not very good at carrying high-speed signals. Additionally, if the NAND device supports boundary scan, continuity detection circuitry can be connected to the scan chain of the boundary scan. For example, nodes can be placed at different ends of the serpentine structure. A node at one end can be set to "listen," and a node at the other end can be set to force a logic zero or one. If a zero or one is not "heard" at the other end, this indicates a problem. The reverse is also true.

[0031] It is intended that the foregoing detailed description be understood as an illustration of the selected forms that the invention may take, and not as a limitation thereof. For example, it will be understood that the inventive techniques can be used in any wafer-to-wafer bonding application, and not just for bonding a wafer with a CMOS circuit to a wafer with a memory or NAND die. Only the appended claims (including all equivalents) define the scope of the claimed invention. Finally, it should be noted that any aspect of any of the embodiments described herein may be used alone or in combination with each other.

Claims

1. An integrated circuit, comprising: A first chip, which includes a first plurality of contact pads; The second wafer includes a second plurality of contact pads, wherein at least some of the first plurality of contact pads are engaged with at least some of the second plurality of contact pads to form a plurality of pillars; A conductor positioned in the first and second wafers and parallel to and offset from at least some of the plurality of pillars; as well as A continuity check circuit, electrically coupled to the conductor and configured to detect warping in the first wafer and / or the second wafer by detecting a break in the conductivity of the conductor.

2. The integrated circuit of claim 1, wherein the first wafer includes a memory array, and the second wafer includes peripheral circuitry for the memory array.

3. The integrated circuit of claim 2, wherein the second wafer comprises a complementary metal-oxide-semiconductor (CMOS) wafer.

4. The integrated circuit of claim 1, wherein the continuity check circuit is in the second wafer.

5. The integrated circuit of claim 1, wherein the conductor extends in a serpentine shape through the first wafer and the second wafer, and extends between at least some of the plurality of pillars.

6. The integrated circuit of claim 1, wherein the conductor extends across at least one of a plurality of regions in the first wafer and the second wafer.

7. The integrated circuit of claim 6, wherein the integrated circuit includes at least one additional conductor electrically coupled to the continuity check circuit and extending across at least one other region of the plurality of regions.

8. The integrated circuit of claim 6, wherein the plurality of regions includes one or more of the following: a high-voltage region, a word line region, a bit line region, and a decoded address region.

9. The integrated circuit of claim 1, wherein the conductor comprises a first portion formed in the first wafer and a second portion formed in the second wafer.

10. The integrated circuit of claim 9, wherein the first portion and the second portion comprise respective horizontal and vertical components, and wherein at least some of the vertical components are joined together.

11. The integrated circuit of claim 10, wherein the horizontal component comprises a metal-filled trench, and wherein the vertical component comprises a metal-filled vertical interconnect channel structure (via).

12. A method for detecting warpage in an integrated circuit comprising a first wafer and a second wafer bonded together, the method comprising: An electric current is applied through a conductor that extends in a serpentine shape through the first wafer and the second wafer, and extends between the regions where the first wafer and the second wafer are joined together; as well as Warpage of at least one of the first and second wafers is detected by detecting a break in the conductivity of the conductor; and The first wafer includes a first plurality of contact pads, and the second wafer includes a second plurality of contact pads, wherein at least some of the first plurality of contact pads are bonded to at least some of the second plurality of contact pads to form a plurality of pillars, and The conductor is parallel to and offset from at least some of the plurality of pillars.

13. The method of claim 12, wherein the first wafer comprises a memory array, and the second wafer comprises a complementary metal-oxide-semiconductor (CMOS) wafer, the CMOS wafer including peripheral circuitry for the memory array.

14. The method of claim 12, wherein the conductor extends across at least one of a plurality of regions in the first wafer and the second wafer.

15. An integrated circuit, comprising: The first chip includes a first plurality of electrical contacts; The second wafer includes a second plurality of electrical contacts, wherein at least some of the first plurality of electrical contacts are coupled to at least some of the second plurality of electrical contacts to form a plurality of pillars; as well as A component for detecting warping in at least one of the first wafer and the second wafer, wherein the component for detecting warping includes conductors that are parallel to and offset from at least some of the plurality of pillars.

16. The integrated circuit of claim 15, wherein the component for detecting warpage further includes a continuity check circuit.

17. The integrated circuit of claim 15, wherein the conductor is serpentine.

18. The integrated circuit of claim 15, wherein the conductor comprises a first portion formed in the first wafer and a second portion formed in the second wafer.

19. The integrated circuit of claim 18, wherein the first portion and the second portion comprise respective horizontal and vertical components, wherein the horizontal component comprises a metal-filled trench, and wherein the vertical component comprises a metal-filled vertical interconnect channel structure (via).

20. The integrated circuit of claim 15, wherein the first wafer comprises a NAND memory wafer, and the second wafer comprises a complementary metal-oxide-semiconductor (CMOS) wafer.

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