A control method for a charge pump circuit applicable to a thin gate oxide process

Abstract

The present application discloses a control method for a charge pump circuit applicable to a thin gate oxide process: the charge pump auxiliary circuit outputs a high-level voltage to provide a driving signal for the driving circuit; the charge pump circuit outputs a driving voltage applicable to the thin gate oxide process to drive the N-type power transistor. By adopting the embodiment of the present application, a driving voltage applicable to the thin gate oxide process can be output to drive the N-type power transistor, with relatively low cost and high reliability.

Description

Technical Field

[0001] This application relates to the technical field of charge pump circuits, and particularly to a control method for a charge pump circuit applicable to a thin gate oxide process. Background Art

[0002] Charge pump circuits are often used in power stage analog integrated circuits. In some systems, the source voltage of the N-type power transistor is the highest power supply voltage of the system. When driving the N-type power transistor, a voltage signal higher than the highest power supply voltage of the system is required. However, existing charge pump circuits often use an off-chip large capacitor method, which is costly and consumes an additional pin. Summary of the Invention

[0003] Embodiments of this application provide a charge pump circuit, a control method for a charge pump circuit, a chip, and an electronic device.

[0004] In a first aspect, embodiments of this application provide a charge pump circuit, which includes a charge pump auxiliary module, a driving module, a charge pump module, an N-type power transistor, diode Z2, and diode Z3;

[0005] The charge pump auxiliary module is connected to the driving module, the driving module is connected to the charge pump module, the charge pump module is connected to the gate of the N-type power transistor, the negative electrode of diode Z2 is connected between the charge pump module and the gate of the N-type power transistor, the positive electrode of diode Z2 is connected to the negative electrode of diode Z3, and the positive electrode of diode Z3 is connected to the source of the N-type power transistor;

[0006] The charge pump auxiliary module is configured to output a high-level voltage to provide a driving signal for the driving module;

[0007] The charge pump module is configured to output a driving voltage applicable to the thin gate oxide process to drive the N-type power transistor.

[0008] In one implementation, the charge pump auxiliary module includes field effect transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, diode Z1, resistors R1, R2, R3, inverter I1, diodes D1, D2, and D3;

[0009] The drain of the field effect tube M1 is connected to the signal VM, the drain of the field effect tube M3 is connected to the power supply VCC, the gate of the field effect tube M4 is connected to the signal COMP via the inverter I1, the gates of the field effect tube M8 and the field effect tube M9 are connected between the signal COMP and the inverter I1, the gate of the field effect tube M1 is connected in series with the gate of the field effect tube M2 and then connected to the drain of the field effect tube M11, the gate of the field effect tube M3 is connected to the drain of the field effect tube M4, the source of the field effect tube M4 is connected to one end of the resistor R2, the gate of the field effect tube M6 is connected to the gate of the field effect tube M7, the drain of the field effect tube M7 is connected to the source of the field effect tube M8, and the field effect tube M8 is connected to the gate of the field effect tube M9. The drain of the field effect tube M10 is connected to the drain of the field effect tube M10, the gate of the field effect tube M10 is connected to the gate of the field effect tube M11, the drain of the field effect tube M11 is connected to the drain of the field effect tube M9, the source of the field effect tube M9 is connected to one end of the resistor R2 and the source of the field effect tube M4, the other end of the resistor R2 is connected to the drain of the field effect tube M5, the source of the field effect tube M12 is connected to the node B, the gate and drain of the field effect tube M12 are connected to the drain of the field effect tube M2 and the node A, the resistor R3 is connected in parallel between the source and the drain of the field effect tube M11, one end of the diode Z1 is connected to the node A, and the other end of the diode Z1 is connected to the drain of the field effect tube M6;

[0010] The diode D1 is connected in parallel to the field effect transistor M1, the diode D2 is connected in parallel to the field effect transistor M3, and the diode D3 is connected in parallel to the field effect transistor M2;

[0011] The diode D1, the diode D2, and the diode D3 are all independent diodes, or anti-parallel diodes built into the field effect tube.

[0012] In one implementation, the field effect transistor M6 and the field effect transistor M7 are connected to form a current mirror structure, and the width-to-length ratio is 1:1;

[0013] The field effect transistor M10 and the field effect transistor M11 are connected to form a current mirror structure, and the width-to-length ratio is 1:N.

[0014] In one implementation, when the voltage of the signal VM is lower than the voltage of the power supply VCC, the voltage of the signal COMP is at a low level, the field effect transistor M3 is in an on state, the field effect transistor M1 and the field effect transistor M2 are in a off state, and the voltage of the node B is:

[0015] V B =VCC-V DS3-V GS12 ;

[0016] Wherein, the V B is the voltage of node B, the VCC is the voltage of power supply VCC, and the V DS3 is the voltage difference between the source and drain of field effect transistor M3, and the V GS12 is the voltage difference between the gate and source of field effect transistor M12.

[0017] In one implementation, when the voltage of signal VM is higher than the voltage of power supply VCC, the voltage of signal COMP is high level, field effect transistor M3 is in the off state, field effect transistors M1 and M2 are in the on state, and the voltage of node B is:

[0018] V B = V Z - V GS6 - V GS12 ;

[0019] Wherein, the V B is the voltage of node B, the V Z is the reverse breakdown voltage of the diode, the V GS6 is the voltage difference between the gate and source of field effect transistor M6, and the V GS12 is the voltage difference between the gate and source of field effect transistor M12.

[0020] In one implementation, the driving module includes inverter I2, inverter I3, inverter I4 and inverter I5;

[0021] The input end of inverter I2 is connected to clock signal CLK, the output end of inverter I2 is connected to the input end of inverter I3, the output end of inverter I3 is connected to the input end of inverter I4, the output end of inverter I4 is connected to the input end of inverter I5, and the output end of inverter I5 is connected to node D.

[0022] In one implementation, the charge pump module includes capacitor C1, capacitor C2, field effect transistors M13, M14, M15 and M16, diodes D4, D5, D6 and D7;

[0023] Field effect transistor M13 and field effect transistor M14 are cross-coupled, field effect transistor M15 and field effect transistor M16 are cross-coupled, one end of capacitor C1 is connected to node E, the other end of capacitor C1 is connected to node C, one end of capacitor C2 is connected to node F, and the other end of capacitor C2 is connected to node D;

[0024] The charge pump module further includes diode D4, diode D5, diode D6, and diode D7;

[0025] Diode D4 is connected in parallel with field effect transistor M13, diode D5 is connected in parallel with field effect transistor M14, diode D6 is connected in parallel with field effect transistor M15, and diode D7 is connected in parallel with field effect transistor M16;

[0026] Diode D4, diode D5, diode D6, and diode D7 are all independent diodes or anti-parallel diodes built into the field effect transistor.

[0027] In one implementation, field effect transistors M13, M14, M15, and M16 are all charge pump switching transistors;

[0028] The turning on or off of field effect transistors M13, M14, M15, and M16 is determined by the voltages at node E and node F;

[0029] Field effect transistors M13 and M14 have the same width-to-length ratio, and field effect transistors M15 and M16 have the same width-to-length ratio.

[0030] In one implementation, the driving voltage of the N-type power transistor is:

[0031] V GS17 = V Z + V GS6 - V GS12 - V DS13,14 - V D + V DS17 ;

[0032] Wherein, the V GS17 is the driving voltage of the N-type power transistor, the V Z is the reverse breakdown voltage of the diode, the V GS6 is the voltage difference between the gate and source of field effect transistor M6, the V GS12 is the voltage difference between the gate and source of field effect transistor M12, the V DS13,14 is the voltage difference between the drain and source of field effect transistors M13 and M14, the V D is the voltage at node D, and V DS17 is the voltage difference between the drain and source of the N-type power transistor.

[0033] In a second aspect, an embodiment of the present application provides a control method for a charge pump circuit. The charge pump circuit includes a charge pump auxiliary module, a driving module, a charge pump module, an N-type power transistor, a diode Z2, and a diode Z3;

[0034] The charge pump auxiliary module is connected to the driving module, the driving module is connected to the charge pump module, the charge pump module is connected to the gate of the N-type power transistor, the negative electrode of the diode Z2 is connected between the charge pump module and the gate of the N-type power transistor, the positive electrode of the diode Z2 is connected to the negative electrode of the diode Z3, and the positive electrode of the diode Z3 is connected to the source of the N-type power transistor; The method includes:

[0035] The charge pump auxiliary module outputs a high-level voltage to provide a driving signal for the driving module;

[0036] The charge pump module outputs a driving voltage suitable for a thin gate oxide process to drive the N-type power transistor.

[0037] In one implementation, the method further includes:

[0038] If the voltage of the signal VM is lower than the voltage of the power supply VCC and the voltage of the signal COMP is low level, the charge pump auxiliary module controls the field effect transistor M3 to be in an open state and controls the field effect transistors M1 and M2 to be in a closed state;

[0039] If the voltage of the signal VM is higher than the voltage of the power supply VCC and the voltage of the signal COMP is high level, the charge pump auxiliary module controls the field effect transistor M3 to be in a closed state and the field effect transistors M1 and M2 to be in an open state.

[0040] In a third aspect, an embodiment of the present application provides a chip, and the chip includes the charge pump circuit as described in the first aspect.

[0041] In a fourth aspect, an embodiment of the present application provides an electronic device, and the electronic device includes the charge pump circuit as described in the first aspect.

[0042] It can be seen that in the embodiment of the present application, without using an off-chip large capacitor, a driving voltage suitable for a thin gate oxide process can be output to drive the N-type power transistor, with low cost and high reliability. Description of the Drawings

[0043] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0044] Figure 1 is the circuit schematic diagram of a charge pump circuit provided by an embodiment of the present application;

[0045] Figure 2 is the flow schematic diagram of a control method for a charge pump circuit provided by an embodiment of the present application. Detailed implementation manners

[0046] In order to enable those skilled in the art to better understand the solutions of the present application, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0047] The term "and / or" in the present application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0048] The term "multiple" that appears in the embodiments of the present application refers to two or more. The descriptions such as the first and the second that appear in the embodiments of the present application are only for indicating and distinguishing the described objects, without an order, and do not represent a special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application. The term "connection" that appears in the embodiments of the present application refers to various connection methods such as direct connection or indirect connection to achieve communication between devices, and the present application does not make any limitation on this.

[0049] Please refer to Figure 1 , Figure 1 is the circuit schematic diagram of a charge pump circuit provided by an embodiment of the present application. The charge pump circuit includes a charge pump auxiliary module 10, a driving module 20, a charge pump module 30, an N-type power transistor M17, a diode Z2, and a diode Z3;

[0050] The charge pump auxiliary module 10 is connected to the driving module 20, the driving module 20 is connected to the charge pump module 30, the charge pump module 30 is connected to the gate of the N-type power transistor, the negative electrode of the diode Z2 is connected between the charge pump module and the gate of the N-type power transistor, the positive electrode of the diode Z2 is connected to the negative electrode of the diode Z3, and the positive electrode of the diode Z3 is connected to the source of the N-type power transistor;

[0051] The charge pump auxiliary module is configured to output a high-level voltage to provide a driving signal for the driving module;

[0052] The charge pump module is configured to output a driving voltage suitable for a thin gate oxide process to drive the N-type power transistor M17.

[0053] Among them, both the diode Z2 and the diode Z3 are Zener diodes. The diode Z3 and the diode Z3 are connected in a back-to-back form, which can limit the voltage difference between the gate and the source of the N-type power transistor M17 to avoid gate-source breakdown of the N-type power transistor M17.

[0054] Among them, the charge pump circuit further includes a diode D8, the diode D8 is connected in parallel with the N-type power transistor M17, and after the positive electrode of the diode Z3 intersects with the source of the N-type power transistor, the output signal OUT is obtained.

[0055] In an implementation manner of the present application, the charge pump auxiliary module includes a field effect transistor M1, a field effect transistor M2, a field effect transistor M3, a field effect transistor M4, a field effect transistor M5, a field effect transistor M6, a field effect transistor M7, a field effect transistor M8, a field effect transistor M9, a field effect transistor M10, a field effect transistor M11, a field effect transistor M12, a diode Z1, a resistor R1, a resistor R2, a resistor R3, and an inverter I1;

[0056] The drain of the field effect transistor M1 is connected to the signal VM, the drain of the field effect transistor M3 is connected to the power supply VCC, the gate of the field effect transistor M4 is connected to the signal COMP via the inverter I1, the gates of the field effect transistor M8 and the field effect transistor M9 are connected between the signal COMP and the inverter I1, the gates of the field effect transistor M1 and the field effect transistor M2 are connected in series and then connected to the drain of the field effect transistor M11, the gate of the field effect transistor M3 is connected to the drain of the field effect transistor M4, the source of the field effect transistor M4 is connected to one end of the resistor R2, the gates of the field effect transistor M6 and the field effect transistor M7 are connected, the drain of the field effect transistor M7 is connected to the source of the field effect transistor M8, the drain of the field effect transistor M8 is connected to the drain of the field effect transistor M10, the gate of the field effect transistor M10 is connected to the gate of the field effect transistor M11, the drain of the field effect transistor M11 is connected to the drain of the field effect transistor M9, the source of the field effect transistor M9 is connected to one end of the resistor R2 and the source of the field effect transistor M4, the other end of the resistor R2 is connected to the drain of the field effect transistor M5, the source of the field effect transistor M12 is connected to the node B, the gate and the drain of the field effect transistor M12 are connected and then connected to the drain of the field effect transistor M2 and the node A, the resistor R3 is connected in parallel between the source and the drain of the field effect transistor M11, one end of the diode Z1 is connected to the node A, and the other end of the diode Z1 is connected to the drain of the field effect transistor M6.

[0057] In an implementation manner of the present application, the charge pump auxiliary module further includes a diode D1, a diode D2, and a diode D3;

[0058] The diode D1 is connected in parallel with the field effect transistor M1, the diode D2 is connected in parallel with the field effect transistor M3, and the diode D3 is connected in parallel with the field effect transistor M2;

[0059] The diode D1, the diode D2, and the diode D3 are all independent diodes or anti-parallel diodes built into the field effect transistor.

[0060] Among them, the diode D1 and the diode D3 are two series-connected reverse diodes to prevent the signal VM from being transmitted to the node A through the diode.

[0061] Among them, the signal COMP is a voltage comparison signal of the signal VM and the power supply VCC. When the voltage of the signal VM is greater than the voltage of the voltage VCC, the voltage of the signal COMP is high level. When the voltage of the signal VM is less than the voltage of the voltage VCC, the voltage of the signal COMP is low level. The field effect transistors M4, M8, and M9 are switching transistors related to the signal COMP.

[0062] Among them, the gate of the field effect transistor M5 is connected to the signal EN. The signal EN is an enable signal, and the field effect transistor M5 is a switching transistor related to the signal EN.

[0063] Among them, the resistor R2 is a voltage dividing resistor.

[0064] Among them, the diode Z1 is a Zener diode, which is used for voltage stabilization at node A.

[0065] Among them, the field effect transistor M12 is a transistor with its gate and drain shorted, which is used to adjust the voltage drop between node A and node B.

[0066] In an implementation manner of the present application, the field effect transistor M6 and the field effect transistor M7 are connected to form a current mirror structure, and the aspect ratio is 1:1;

[0067] The field effect transistor M10 and the field effect transistor M11 are connected to form a current mirror structure, and the aspect ratio is 1:N.

[0068] Among them, the N is, for example, 1 or other values.

[0069] In an implementation manner of the present application, when the voltage of the signal VM is lower than the voltage of the power supply VCC, the voltage of the signal COMP is low level, the field effect transistor M3 is in an open state, the field effect transistors M1 and M2 are in a closed state, and the voltage of node B is:

[0070] V B = VCC - V DS3 - V GS12 ;

[0071] Among them, the V B is the voltage of node B, the VCC is the voltage of the power supply VCC, the V DS3 is the voltage difference between the source and drain of the field effect transistor M3, and the V GS12 is the voltage difference between the gate and source of the field effect transistor M12.

[0072] In an implementation manner of the present application, when the voltage of the signal VM is higher than the voltage of the power supply VCC, the voltage of the signal COMP is high level, the field effect transistor M3 is in a closed state, the field effect transistors M1 and M2 are in an open state (at this time, the voltage of node A is clamped by the diode Z1 and the voltage of the signal VM is greater than the Zener voltage of the diode Z1), and the voltage of node B is:

[0073] V B = V Z - V GS6 - V GS12 ;

[0074] Among them, the V B is the voltage of node B, the V Z is the reverse breakdown voltage of the Zener diode, the V GS6 is the voltage difference between the gate and source of the field effect transistor M6, and the V GS12 is the voltage difference between the gate and source of the field effect transistor M12.

[0075] It can be seen that the selection of the voltage of node B is related to the voltage of the signal VM and the voltage of the power supply VCC, and supplies the driving module 20 as the high-level voltage. At this time, the voltages of node C and node D are two inverted voltages with an amplitude of V B . From the voltage of V B , for Zener diodes with different reverse breakdown voltages, the voltage amplitude of node B can be adjusted by changing the aspect ratio of the field effect transistor M12.

[0076] In an implementation manner of the present application, the driving module includes an inverter I2, an inverter I3, an inverter I4, and an inverter I5;

[0077] The input end of the inverter I2 is connected to the clock signal CLK, the output end of the inverter I2 is connected to the input end of the inverter I3, the output end of the inverter I3 is connected to the input end of the inverter I4, the output end of the inverter I4 is connected to the input end of the inverter I5, and the output end of the inverter I5 is connected to node D.

[0078] In an implementation manner of the present application, the charge pump module includes a capacitor C1, a capacitor C2, a field effect transistor M13, a field effect transistor M14, a field effect transistor M15, and a field effect transistor M16, diodes D4, D5, D6, and D7;

[0079] The field effect transistor M13 and the field effect transistor M14 are cross-coupled, the field effect transistor M15 and the field effect transistor M16 are cross-coupled, one end of the capacitor C1 is connected to node E, the other end of the capacitor C1 is connected to node C, one end of the capacitor C2 is connected to node F, and the other end of the capacitor C2 is connected to node D;

[0080] The charge pump module further includes diodes D4, D5, D6, and D7;

[0081] The diode D4 is connected in parallel with the field effect transistor M13, the diode D5 is connected in parallel with the field effect transistor M14, the diode D6 is connected in parallel with the field effect transistor M15, and the diode D7 is connected in parallel with the field effect transistor M16;

[0082] The diode D4, the diode D5, the diode D6, and the diode D7 are all independent diodes or anti-parallel diodes built into the field effect transistor.

[0083] Among them, the capacitor C1 and the capacitor C2 are MIM capacitors of the same type and have equal capacitance values.

[0084] In an implementation manner of the present application, the field effect transistor M13, the field effect transistor M14, the field effect transistor M15, and the field effect transistor M16 are all charge pump switch transistors;

[0085] The turning on or off of the field effect transistor M13, the field effect transistor M14, the field effect transistor M15, and the field effect transistor M16 is determined by the voltages of the node E and the node F;

[0086] The width-to-length ratios of the field effect transistor M13 and the field effect transistor M14 are the same, and the width-to-length ratios of the field effect transistor M15 and the field effect transistor M16 are the same.

[0087] In an implementation manner of the present application, when the charge pump circuit is started, the voltage difference between the two plates of the capacitor C1 and the capacitor C2 is 0. Since the voltage of the signal VM is greater than the voltage of the node B, the signal VM charges the capacitor C1 through the diode D4, and the signal VM charges the capacitor C2 through the diode D5. After several cycles, the voltages between the two plates of the capacitor C1 and the capacitor C2 gradually increase. When the voltages at both ends of the capacitor C1 and the capacitor C2 satisfy Equation 1, the signal VM charges the capacitor C1 and the capacitor C2 through the field effect transistor M13 and the field effect transistor M14;

[0088] V C1,C2 >VM - V B + V TH13,14 (1)

[0089] Among them, the V C1,C2 is the voltage at both ends of the capacitor C1 or the capacitor C2, the VM is the voltage of the access signal VM, and V TH13,14 is the threshold voltage of the field effect transistor M13 or the field effect transistor M14.

[0090] After the capacitor C1 and the capacitor C2 are charged, the voltages at both ends of the capacitor C1 and the capacitor C2 satisfy Equation 2;

[0091] V C1 =V C2 =VM - V DS13,14 (2)

[0092] Among them, the V C1 is the voltage at both ends of the capacitor C1, and the V C2is the voltage across the capacitor C2, and the V DS13,14 is the voltage difference between the drain and source of the field effect transistor M13 or the field effect transistor M14.

[0093] When the voltage across the capacitor gradually increases to the maximum voltage, when the voltage at node C is low level and the voltage at node D is high level, the voltage at node F is:

[0094] V F = V C2 + V B (3)

[0095] wherein, the V F is the voltage at node F.

[0096] When the voltage at node C is high level and the voltage at node D is low level, the voltage at node E is:

[0097] V E = V C1 + V B (4)

[0098] wherein, the VF is the voltage at node F.

[0099] Combining equations 1, 2, and 3, it can be seen that after the charge pump system is stable, the voltage at node G is:

[0100] V G = V B + VM - V DS13,14 - V D (5)

[0101] wherein, V D is the forward voltage drop of the diode. When the charge pump system is working normally, the voltage of the signal VM is greater than the voltage of the power supply VCC. At this time, the driving voltage of the N-type power transistor is:

[0102] V GS17 = V Z + V GS6 - V GS12 - V DS13,14 - V D + V DS17 (6)

[0103] wherein, the V GS17 is the driving voltage of the N-type power transistor, the V GS6 is the voltage difference between the gate and source of the field effect transistor M6, the V GS12 is the voltage difference between the gate and source of the field effect transistor M12, and V DS17 is the voltage difference between the drain and source of the N-type power transistor.

[0104] As can be seen from Equation 6, the driving voltage of the power transistor is independent of the voltage amplitude of the signal VM. When the voltage of the signal VM is relatively large, the charge pump circuit can output a driving voltage suitable for the thin gate oxide process to drive the N-type power transistor.

[0105] It can be seen that in the embodiments of the present application, without using an off-chip large capacitor, a driving voltage suitable for the thin gate oxide process can be output to drive the N-type power transistor, with low cost and high reliability.

[0106] Please refer to Figure 2 , Figure 2 which is a schematic flowchart of a control method for a charge pump circuit provided by an embodiment of the present application. The charge pump circuit is as shown in Figure 1 , and the control method includes the following steps:

[0107] Step 201: The charge pump auxiliary module outputs a high-level voltage to provide a driving signal for the driving module.

[0108] Step 202: The charge pump module outputs a driving voltage suitable for the thin gate oxide process to drive the N-type power transistor.

[0109] In an implementation manner of the present application, the method further includes:

[0110] If the voltage of the signal VM is lower than the voltage of the power supply VCC and the voltage of the signal COMP is low level, the charge pump auxiliary module controls the field effect transistor M3 to be in an open state and controls the field effect transistors M1 and M2 to be in a closed state.

[0111] In this embodiment, the voltage of the node B is:

[0112] V B = VCC - V DS3 - V GS12 ;

[0113] wherein, the V B is the voltage of the node B, the VCC is the voltage of the power supply VCC, the V DS3 is the voltage difference between the source and drain of the field effect transistor M3, and the V GS12 is the voltage difference between the gate and source of the field effect transistor M12.

[0114] Optionally, the method further includes:

[0115] If the voltage of the signal VM is higher than the voltage of the power supply VCC and the voltage of the signal COMP is high, the charge pump auxiliary module controls the field effect transistor M3 to be in the off state, and the field effect transistors M1 and M2 to be in the on state.

[0116] In this embodiment, the voltage of the node B is:

[0117] V B = V Z - V GS6 - V GS12 ;

[0118] Wherein, the V B is the voltage of the node B, the V Z is the reverse breakdown voltage of the Zener diode, the V GS6 is the voltage difference between the gate and the source of the field effect transistor M6, and the V GS12 is the voltage difference between the gate and the source of the field effect transistor M12.

[0119] In an implementation manner of the present application, when the charge pump system is working normally, the voltage of the signal VM is greater than the voltage of the power supply VCC. At this time, the driving voltage of the N-type power transistor is:

[0120] V GS17 = V Z + V GS6 - V GS12 - V DS13,14 - V D + V DS17 (6)

[0121] Wherein, the V GS17 is the driving voltage of the N-type power transistor, the V GS6 is the voltage difference between the gate and the source of the field effect transistor M6, the V DS13,14 is the voltage difference between the drain and the source of the field effect transistor M13 or the field effect transistor M14, the V GS12 is the voltage difference between the gate and the source of the field effect transistor M12, and V DS17 is the voltage difference between the drain and the source of the N-type power transistor.

[0122] It can be seen that in the embodiment of the present application, without using an off-chip large capacitor, a driving voltage suitable for a thin gate oxide process can be output to drive the N-type power transistor, with low cost and high reliability.

[0123] The embodiment of the present application further provides a chip, which includes the aforementioned charge pump circuit. Optionally, the chip can be a fast charging chip.

[0124] An electronic device is further provided in an embodiment of the present application. Among them, the electronic device includes the aforementioned charge pump circuit.

[0125] Among them, the electronic device may be a terminal such as a mobile phone, a tablet computer, a notebook computer, etc., or the electronic device may also be a charging adapter, etc. Optionally, the electronic device further includes other components, which are not limited in the embodiments of the present application.

[0126] It should be noted that the above are only the preferred embodiments of the present application, but the design concept of the invention is not limited thereto. Any non-substantive modifications made to the present application using this concept also fall within the protection scope of the present application.

Claims

1. A control method for a charge pump circuit module, characterized in that wherein, the charge pump circuit module includes: a charge pump auxiliary circuit, a drive circuit, a charge pump circuit, an N-type power transistor, diode Z2, and diode Z3; the charge pump auxiliary circuit is connected to the drive circuit, the drive circuit is connected to the charge pump circuit, and the charge pump circuit is connected to the gate of the N-type power transistor, wherein, the negative electrode of diode Z2 is connected between the charge pump circuit and the gate of the N-type power transistor, the positive electrode of diode Z2 is connected to the positive electrode of diode Z3, and the negative electrode of diode Z3 is connected to the source of the N-type power transistor; wherein, both diode Z2 and diode Z3 are Zener diodes; diode Z2 and diode Z3 are connected in a face-to-face form to limit the voltage difference between the gate and the source of the N-type power transistor to avoid gate-source breakdown of the N-type power transistor; the method includes: the charge pump auxiliary circuit outputs a high-level voltage to provide a drive signal for the drive circuit; the charge pump circuit outputs a drive voltage suitable for a thin gate oxide process to drive the N-type power transistor in the charge pump circuit module; wherein, the charge pump circuit module further includes diode D8, diode D8 is connected in parallel with the N-type power transistor, and after the negative electrode of diode Z3 intersects with the source of the N-type power transistor, an output signal OUT is obtained; wherein, the charge pump auxiliary circuit includes field effect transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, M12, diode Z1, resistors R1, R2, R3, inverter I1, diodes D1, D2, and D3; The drain of the field effect tube M1 is connected to the signal VM, the drain of the field effect tube M3 is connected to the power supply VCC, the gate of the field effect tube M4 is connected to the signal COMP via the inverter I1, the gates of the field effect tube M8 and the field effect tube M9 are connected between the signal COMP and the inverter I1, the gate of the field effect tube M1 is connected in series with the gate of the field effect tube M2 and then connected to the drain of the field effect tube M11, the gate of the field effect tube M3 is connected to the drain of the field effect tube M4, the source of the field effect tube M4 is connected to one end of the resistor R2, the gate of the field effect tube M6 is connected to the gate of the field effect tube M7, the drain of the field effect tube M7 is connected to the source of the field effect tube M8, the drain of the field effect tube M8 is connected to the drain of the field effect tube M10, and the gate of the field effect tube M10 is connected to the gate of the field effect tube M11. The drain of the field effect tube M11 is connected to the drain of the field effect tube M9, the source of the field effect tube M9 is connected to one end of the resistor R2 and the source of the field effect tube M4, the other end of the resistor R2 is connected to the drain of the field effect tube M5, the source of the field effect tube M12 and the driving circuit are both connected to node B, the gate and drain of the field effect tube M12 are connected to the drain of the field effect tube M2 and node A, the resistor R3 is connected in parallel between the source and drain of the field effect tube M11, one end of the diode Z1 is connected to the node A, and the other end of the diode Z1 is connected to the drain of the field effect tube M6; the drain of the N-type power tube is connected between the access signal VM and the positive electrode of the diode D1, the source of the field effect tube M1 is connected to the source of the field effect tube M2, and the source of the field effect tube M3 is connected to the field effect tube M12. The drain of the field effect transistor M5, the source of the field effect transistor M6 and the field effect transistor M7 are all grounded, the gate of the field effect transistor M5 is connected to the signal EN, and the source of the field effect transistor M10 and the source of the field effect transistor M11 are both connected between the source of the field effect transistor M1 and the source of the field effect transistor M2; The diode D1 is connected in parallel to the field effect transistor M1, the diode D2 is connected in parallel to the field effect transistor M3, and the diode D3 is connected in parallel to the field effect transistor M2; The diode D1 is an independent diode or an anti-parallel diode inside a field effect tube; the diode D2 is an independent diode or an anti-parallel diode inside a field effect tube; the diode D3 is an independent diode or an anti-parallel diode inside a field effect tube; The source of the field effect transistor M3 and the drain of the field effect transistor M4 are also connected via a resistor R1.

2. The method according to claim 1, It is characterized in that The method further includes: if the voltage of signal VM is lower than the voltage of power supply VCC and the voltage of signal COMP is at a low level, the charge pump auxiliary circuit controls the field effect transistor M3 to be in an on state and controls the field effect transistors M1 and M2 to be in an off state; If the voltage of the signal VM is higher than the voltage of the power supply VCC and the voltage of the signal COMP is at a high level, the charge pump auxiliary circuit controls the field effect transistor M3 to be in an off state and the field effect transistors M1 and M2 to be in an on state.

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