High-precision pixel circuit and method of operating a high-precision pixel circuit

Abstract

This invention provides a high-precision pixel circuit and a method for operating the high-precision pixel circuit. A first sample-and-hold stage and a second sample-and-hold stage are cascaded between a buffer amplifier and an amplifier circuit. During a first and a second time period, buffered output signals with a first voltage and a second voltage generated by the buffer amplifier are sequentially stored in the first sample-and-hold stage and the second sample-and-hold stage. The amplifier circuit independently senses the first voltage stored in the first sample-and-hold stage and the second voltage stored in the second sample-and-hold stage, respectively, to generate corresponding first and second output signals. Then, a correction signal is generated based on the first and second output signals.

Description

Technical Field

[0001] This invention relates to a pixel circuit, and more particularly to a high-precision pixel circuit. The invention also relates to a method for operating the high-precision pixel circuit. Background Technology

[0002] For prior art patents related to this invention, please refer to US Patent Publication No. 8569671, US Patent Publication No. 8754357, and European Union Patent Publication No. EP2109306B1. These prior art patents address the shortcomings of the prior art in a different manner than this invention.

[0003] Please see Figure 1A This illustrates a prior art pixel circuit (i.e., pixel circuit 101A). Pixel circuit 101A samples and holds a buffered voltage, wherein this buffered voltage is related to the voltage on the floating diffusion node FD. The voltage on the floating diffusion node FD is generated sequentially via sample-and-hold circuits 26 and 36 connected in series. Furthermore, pixel circuit 101A sequentially reads the voltage generated via sample-and-hold circuits 26 and 36 connected in series through a single read buffer 48.

[0004] The disadvantage of this prior art pixel circuit 101A is that when reading the voltage sampled and held by the sample-and-hold circuit 26, the charge in capacitor C26 will be redistributed to capacitor C36. As a result, the reading signal level will drop, thus causing the pixel circuit 101A to have a lower signal-to-noise ratio (SNR).

[0005] Please see Figure 1B This illustrates another prior art pixel circuit (i.e., pixel circuit 101B). Pixel circuit 101B samples and holds a buffered voltage, wherein this buffered voltage is related to the voltage on the floating diffusion node FD. The voltage on the floating diffusion node FD is generated in parallel via sample-and-hold circuits 27 and 37. Furthermore, pixel circuit 101B reads the voltage generated via sample-and-hold circuits 27 and 37, respectively, and in parallel via read buffers 49 and 48.

[0006] The disadvantage of this prior art pixel circuit 101B is that when reading the voltage generated by the sample-and-hold circuit 27 and the sample-and-hold circuit 37, an additional reading error is caused due to the offset between the read buffer 49 and the read buffer 48.

[0007] Compared to the prior art pixel circuit 101A, the advantage of the pixel circuit of the present invention is that the voltages generated by each sample-and-hold circuit are read independently and separately. As a result, the pixel circuit of the present invention can have a higher signal-to-noise ratio.

[0008] Compared to the pixel circuit 101B of the prior art, the pixel circuit of the present invention has the advantage that the offsets between different read buffers can be canceled out. Summary of the Invention

[0009] From one perspective, the present invention provides a pixel circuit comprising: a photosensitive element for generating charge based on incident light; a floating diffusion node; a reset transistor for discharging charge from the floating diffusion node; a transfer switching switch coupled between the photosensitive element and the floating diffusion node for controlling the transfer of charge from the photosensitive element to the floating diffusion node; a buffer amplifier having an input terminal coupled to the floating diffusion node, the buffer amplifier for generating a buffered output signal based on a voltage at the floating diffusion node; an amplifier circuit; a first sample-and-hold stage; and a second sample-and-hold stage, wherein the first sample-and-hold stage and the second sample-and-hold stage are cascaded between the buffer amplifier and the amplifier circuit; wherein the second sample-and-hold stage samples or samples and holds the buffered output signal to generate a second sample-and-hold signal, and the first sample-and-hold stage samples and holds the second sample-and-hold signal to generate a first sample-and-hold signal; wherein the amplifier circuits are independently electrically connected. At an output terminal of the first sample-and-hold stage and an output terminal of the second sample-and-hold stage; wherein, within a first time period of a global exposure cycle, the second sample-and-hold stage samples the buffered output signal having a first voltage to generate the second sample-and-hold signal having the first voltage, and the first sample-and-hold stage samples and holds the second sample-and-hold signal to generate the first sample-and-hold signal having the first voltage, wherein the first voltage is related to a first state of the floating diffusion node; wherein, within a second time period of the global exposure cycle, the second sample-and-hold stage samples and holds the buffered output signal having a second voltage to generate the second sample-and-hold signal having the second voltage, wherein the second voltage is related to a second state of the floating diffusion node; wherein, within a third time period of the global exposure cycle, the first sample-and-hold signal having the first voltage and the second sample-and-hold signal having the second voltage are independently sensed by the amplifier circuit, thereby generating a corresponding first output signal and a corresponding second output signal respectively.

[0010] In a preferred embodiment, the amplifier circuit senses the first sample-and-hold signal without needing to sense the second sample-and-hold signal, and the amplifier circuit senses the second sample-and-hold signal without needing to sense the first sample-and-hold signal.

[0011] In a preferred embodiment, the amplifier circuit includes: a first readout amplifier having an input terminal for receiving the first sample-and-hold signal; and a second readout amplifier having an input terminal for receiving the second sample-and-hold signal; wherein during an equalization period, the first sample-and-hold signal and the second sample-and-hold signal are equalized to each other, such that both the first sample-and-hold signal and the second sample-and-hold signal have an equalized voltage; wherein during a fourth period of the global exposure cycle, the first readout amplifier senses the equalized voltage to generate a first offset signal, and the second readout amplifier senses the equalized voltage to generate a second offset signal.

[0012] In a preferred embodiment, an offset compensation signal is generated based on the first output signal, the second output signal, the first offset signal, and the second offset signal.

[0013] In a preferred embodiment, the first state corresponds to a reset state, wherein a pulse is sent to control the reset transistor so that the charge in the floating diffusion node is completely drained; and wherein the second state corresponds to a sensing state, wherein a pulse is sent after an exposure period to control the transfer switching switch so that the charge in the photosensitive element is completely transferred to the floating diffusion node.

[0014] In a preferred embodiment, the buffer amplifier includes a sensing buffer transistor; wherein a gate of the sensing buffer transistor is connected to the floating diffusion node; wherein a source of the sensing buffer transistor is connected to an output terminal of the buffer amplifier to generate the buffered output signal; and wherein a drain of the sensing buffer transistor is connected to a buffer supply signal.

[0015] In a preferred embodiment, a low-level quasi-pulse is generated in the buffer supply signal before the sensing buffer transistor senses the first state or the second state of the floating diffusion node, in order to reset the buffered output signal.

[0016] In a preferred embodiment, the buffer amplifier further includes a current source connected to the source of the sensing buffer transistor.

[0017] In a preferred embodiment, the first read amplifier includes: a first read buffer transistor having a gate connected to the output terminal of the first sample-and-hold stage; and a first read switch connected to a source of the first read buffer transistor and an output terminal of the first read amplifier; wherein the second read amplifier includes: a second read buffer transistor having a gate connected to the output terminal of the second sample-and-hold stage; and a second read switch connected to a source of the second read buffer transistor and an output terminal of the second read amplifier.

[0018] In a preferred embodiment, the sensing buffer transistor and the first read buffer transistor have complementary conductivity types, and / or the sensing buffer transistor and the second read buffer transistor have complementary conductivity types, such that an offset level of the sensing buffer transistor cancels out an offset level of the first read buffer transistor, and / or an offset level of the sensing buffer transistor cancels out an offset level of the second read buffer transistor.

[0019] In a preferred embodiment, an output terminal of the first read amplifier and an output terminal of the second read amplifier are short-circuited and connected to a pixel line.

[0020] In a preferred embodiment, an output terminal of the first read amplifier is connected to a first pixel line, and an output terminal of the second read amplifier is connected to a second pixel line.

[0021] In a preferred embodiment, a capacitance value of the floating diffusion node is adjusted by an adjustment signal, such that the pixel circuit operates in at least one of the following modes: (1) a low conversion gain mode, wherein the floating diffusion node has a first equivalent capacitance value; (2) a high conversion gain mode, wherein the floating diffusion node has a second equivalent capacitance value, wherein the second equivalent capacitance value is less than the first equivalent capacitance value; and / or (3) a high dynamic range (HDR) mode, wherein the capacitance value of the floating diffusion node switches between the first equivalent capacitance value and the second equivalent capacitance value.

[0022] In a preferred embodiment, the pixel circuit further includes: an adjustment switch connected between the reset transistor and the floating diffusion node and controlled by the adjustment signal; and an adjustment capacitor connected to a junction node where the reset transistor and the adjustment switch are connected to each other; wherein the floating diffusion node has the first equivalent capacitance value when the adjustment switch is on, and the floating diffusion node has the second equivalent capacitance value when the adjustment switch is off.

[0023] In a preferred embodiment, when the pixel circuit operates in the low conversion gain mode, the adjustment switch is turned on; wherein the first state corresponds to a reset state, wherein in the reset state, a pulse is sent to control the reset transistor so that the charge of the floating diffusion node is completely discharged; wherein the second state corresponds to a sensing state, wherein in the sensing state, after an exposure period, a pulse is sent to control the transfer switching switch so that the charge in the photosensitive element is completely transferred to the floating diffusion node; wherein a low-gain correction signal is generated based on the first output signal and the second output signal.

[0024] In a preferred embodiment, when the pixel circuit operates in the high conversion gain mode, the adjustment switch is not turned on; wherein the first state corresponds to a reset state, wherein in the reset state, a pulse is sent to control the reset transistor so that the charge of the floating diffusion node is completely discharged; wherein the second state corresponds to a sensing state, wherein in the sensing state, after an exposure period, a pulse is sent to control the transfer switching switch so that the charge in the photosensitive element is completely transferred to the floating diffusion node; wherein a high-gain correction signal is generated based on the first output signal and the second output signal.

[0025] In a preferred embodiment, when the pixel circuit operates in the high dynamic range mode: wherein, in a high conversion gain sub-mode, the first state corresponds to a sensing state, wherein when the pixel circuit operates in the sensing state of the high conversion gain sub-mode, the adjustment switch is not turned on, and at this time, after an exposure period, a pulse is sent to control the transfer switching switch, such that the charge in the photosensitive element is completely transferred to the floating diffusion node having the second equivalent capacitance value; wherein, in a low conversion gain sub-mode, the second state corresponds to a sensing state, wherein when the pixel circuit operates in the sensing state of the low conversion gain sub-mode, the adjustment switch is turned on, and the charge in the floating diffusion node is redistributed according to the first equivalent capacitance value; wherein a high dynamic range signal is generated based on the first output signal and the second output signal.

[0026] In a preferred embodiment, the amplifier circuit includes: a readout amplifier for sensing a first sample-and-hold signal having the first voltage or a second sample-and-hold signal having the second voltage to generate a corresponding first output signal or a corresponding second output signal; and a selector circuit for selecting one of the first sample-and-hold signal or the second sample-and-hold signal, so that it is electrically connected to an input terminal of the readout amplifier, thereby generating the corresponding first output signal or the corresponding second output signal during the third time period.

[0027] In a preferred embodiment, the buffer amplifier includes a sensing buffer transistor; wherein a gate of the sensing buffer transistor is connected to the floating diffusion node; wherein a source of the sensing buffer transistor is connected to an output terminal of the buffer amplifier to generate the buffered output signal; and wherein a drain of the sensing buffer transistor is connected to a buffer supply signal.

[0028] In a preferred embodiment, a low-level quasi-pulse is generated in the buffer supply signal before the sensing buffer transistor senses the first state or the second state of the floating diffusion node, in order to reset the buffered output signal.

[0029] In a preferred embodiment, the buffer amplifier further includes a current source connected to the source of the sensing buffer transistor.

[0030] In a preferred embodiment, the pixel circuit further includes: a third sample-and-hold stage and a fourth sample-and-hold stage, wherein the third sample-and-hold stage and the fourth sample-and-hold stage are cascaded between the buffer amplifier and the amplifier circuit; wherein the fourth sample-and-hold stage is used to sample or sample and hold the buffered output signal to generate a fourth sample-and-hold signal, and the third sample-and-hold stage is used to sample and hold the fourth sample-and-hold signal to generate a third sample-and-hold signal; wherein the pixel circuit operates in the high dynamic range mode; wherein during the first time period and the second time period, the adjustment The switch is not turned on, causing the floating diffusion node to have the second equivalent capacitance value; wherein, during a fifth time period of a global exposure cycle, the fourth sample-and-hold stage samples the buffered output signal having a third voltage to generate the fourth sample-and-hold signal having the third voltage, and the third sample-and-hold stage samples and holds the fourth sample-and-hold signal to generate the third sample-and-hold signal having the third voltage, wherein the third voltage is related to a third state of the floating diffusion node; wherein, during a sixth time period of the global exposure cycle, the fourth sample-and-hold stage samples and holds a fourth voltage. The buffered output signal is used to generate the fourth sample-and-hold signal having the fourth voltage, wherein the fourth voltage is related to a fourth state of the floating diffusion node; wherein during the fifth and sixth time periods, the adjustment switch is turned on, such that the floating diffusion node has the first equivalent capacitance value; wherein the first state, the second state, the third state, and the fourth state each correspond to a reset state of a low conversion gain submode, a sensing state of a high conversion gain submode, the reset state of the high conversion gain submode, and the sensing state of the low conversion gain submode; wherein in the global During a seventh time period of the exposure cycle, the first sample-and-hold signal with the first voltage, the second sample-and-hold signal with the second voltage, the third sample-and-hold signal with the third voltage, and the fourth sample-and-hold signal with the fourth voltage are independently sensed by the amplifier circuit, thereby generating a corresponding first output signal, a corresponding second output signal, a corresponding third output signal, and a corresponding fourth output signal, respectively; wherein a high dynamic range offset compensation signal is generated based on the first output signal, the second output signal, the third output signal, and the fourth output signal.

[0031] In a preferred embodiment, the pixel circuit operates according to the following timing sequence: the first time period, the fifth time period, the second time period, the sixth time period, the third time period, and the seventh time period in sequence.

[0032] In a preferred embodiment, each of the first sample-and-hold stage and the second sample-and-hold stage includes: a holding capacitor connected to the output terminal of the corresponding sample-and-hold stage; and a sampling switch connected between an input terminal and the output terminal of the corresponding sample-and-hold stage.

[0033] In a preferred embodiment, each of the first sample-and-hold stage, the second sample-and-hold stage, the third sample-and-hold stage, and the fourth sample-and-hold stage includes: a holding capacitor connected to the output terminal of the corresponding sample-and-hold stage; and a sampling switch connected between an input terminal and the output terminal of the corresponding sample-and-hold stage.

[0034] From another perspective, the present invention provides a method for operating a pixel circuit, wherein the pixel circuit includes: a photosensitive element for generating charge according to incident light; a floating diffusion node; a reset transistor for discharging charge from the floating diffusion node; a transfer switching switch coupled between the photosensitive element and the floating diffusion node for controlling the transfer of charge from the photosensitive element to the floating diffusion node; a buffer amplifier having an input terminal coupled to the floating diffusion node, the buffer amplifier for generating a buffered output signal according to a voltage on the floating diffusion node; an amplifier circuit; a first sample-and-hold stage; and a second sample-and-hold stage, wherein the first sample-and-hold stage and the second sample-and-hold stage are cascaded between the buffer amplifier and the amplifier circuit; wherein the second sample-and-hold stage is used to sample or sample and hold the buffered output signal to generate a second sample-and-hold signal, and the first sample-and-hold stage is used to sample... The method includes: (S10): during a first time period of a global exposure cycle, storing the buffered output signal having a first voltage in the second sample-and-hold stage, wherein the first voltage is related to a first state of the floating diffusion node; (S20): during a second time period of the global exposure cycle, storing the buffered output signal having a second voltage in the second sample-and-hold stage, wherein the second voltage is related to a second state of the floating diffusion node; (S30): during a third time period of the global exposure cycle, the first voltage and the second voltage are independently sensed by the amplifier circuit, thereby generating a corresponding first output signal and a corresponding second output signal.

[0035] In a preferred embodiment, the amplifier circuit includes: a first readout amplifier having an input terminal for sensing the first sample-and-hold signal; and a second readout amplifier having an input terminal for sensing the second sample-and-hold signal; wherein the method further includes: (S35): during an equalization period, equalizing the first sample-and-hold stage and the second sample-and-hold stage to store an equalized voltage in the first sample-and-hold stage and the second sample-and-hold stage; (S40): during a fourth period of the global exposure cycle, the first readout amplifier senses the equalized voltage in the first sample-and-hold stage to generate a first offset signal, and the second readout amplifier senses the equalized voltage in the second sample-and-hold stage to generate a second offset signal.

[0036] In a preferred embodiment, the method further includes: (S100) generating an offset compensation signal based on the first output signal, the second output signal, the first offset signal, and the second offset signal.

[0037] In a preferred embodiment, the method further includes: (S05): prior to step (S10), in the first state, sending a pulse to control the reset transistor to completely drain the charge from the floating diffusion node; and (S15): prior to step (S20), in a transition period of the second state, sending a pulse to control the transfer switching switch to completely transfer the charge in the photosensitive element to the floating diffusion node.

[0038] In a preferred embodiment, the method further includes: adjusting a capacitance value of the floating diffusion node such that the pixel circuit selectively operates in at least one of the following modes: (1) a low conversion gain mode, wherein the floating diffusion node has a first equivalent capacitance value; (2) a high conversion gain mode, wherein the floating diffusion node has a second equivalent capacitance value, wherein the second equivalent capacitance value is less than the first equivalent capacitance value; and / or (3) a high dynamic range (HDR) mode, wherein the capacitance value of the floating diffusion node switches between the first equivalent capacitance value and the second equivalent capacitance value.

[0039] In a preferred embodiment, in the high dynamic range mode, the steps of operating the pixel circuit include: in the first state, adjusting the capacitance value of the floating diffusion node to the second equivalent capacitance value, and controlling the transfer switching switch by a pulse to completely transfer the charge in the photosensitive element to the floating diffusion node within a transfer period; in the second state, adjusting the capacitance value of the floating diffusion node to the first equivalent capacitance value; and generating a high dynamic range signal based on the first output signal and the second output signal.

[0040] The following detailed description through specific embodiments will make it easier to understand the purpose, technical content, features, and effects achieved by the present invention. Attached Figure Description

[0041] Figure 1A This illustrates a pixel circuit of the prior art.

[0042] Figure 1B This shows a pixel circuit of another existing technology.

[0043] Figure 2 A schematic diagram of an embodiment of the pixel circuit according to the present invention is shown.

[0044] Figure 3 The diagram shows operation waveforms corresponding to various embodiments of the present invention.

[0045] Figure 4 This illustrates an embodiment of an amplifier circuit for a pixel circuit according to the present invention.

[0046] Figure 5 A schematic diagram showing a more specific embodiment of the pixel circuit according to the present invention is shown.

[0047] Figure 6 This diagram shows a more specific embodiment of the pixel circuit according to the present invention.

[0048] Figure 7 The display corresponds to Figure 6 The operation waveform diagram of the embodiment is shown below.

[0049] Figure 8 A schematic diagram of an embodiment of the pixel circuit according to the present invention is shown.

[0050] Figure 9 The display corresponds to Figure 8 The operation waveform diagram of the embodiment is shown below.

[0051] Figure 10 A schematic diagram of an embodiment of the pixel circuit according to the present invention is shown.

[0052] Figure 11 The display corresponds to Figure 10 The operation waveform diagram of the embodiment is shown below.

[0053] Figure 12 A schematic diagram of an embodiment of the pixel circuit according to the present invention is shown.

[0054] Figure 13 The display corresponds to Figure 12 The operation waveform diagram of the embodiment is shown below.

[0055] Figure 14 A schematic diagram of an embodiment of the pixel circuit according to the present invention is shown.

[0056] Figures 15-17 The display corresponds to Figure 14 The operation waveform diagram of the embodiment is shown below.

[0057] Figure 18 A schematic diagram showing a more specific embodiment of the pixel circuit according to the present invention is shown.

[0058] Figure 19 A schematic diagram showing a more specific embodiment of the pixel circuit according to the present invention is shown.

[0059] Figure 20 A schematic diagram showing a more specific embodiment of the pixel circuit according to the present invention is shown.

[0060] Figure 21 The display corresponds to Figure 20 The operation waveform diagram of the embodiment is shown below.

[0061] Figure 22 A schematic diagram of an embodiment of the pixel circuit according to the present invention is shown.

[0062] Figure 23 The display corresponds to Figure 22 The operation waveform diagram of the embodiment is shown below.

[0063] Figure 24 A schematic diagram of an embodiment of the pixel circuit according to the present invention is shown.

[0064] Figure 25 The display corresponds to Figure 24 The specific operation waveform diagram of the embodiment is shown below. Detailed Implementation

[0065] The accompanying drawings in this invention are all schematic and are mainly intended to show the coupling relationship between various circuits and the relationship between various signal waveforms. The circuits, signal waveforms and frequencies are not drawn to scale.

[0066] Please see Figure 2 The diagram shows a schematic representation of an embodiment of the pixel circuit (i.e., pixel circuit 102) according to the present invention. The pixel circuit 102 of the present invention includes: a photosensitive element 10, a floating diffusion node FD, a reset transistor MR, a transfer switching switch MTG, a buffer amplifier 50, a first sample-and-hold stage SH1, a second sample-and-hold stage SH2, and an amplifier circuit 40.

[0067] The photosensitive element 10 is used to generate an electric charge in response to incident light (e.g., illumination). The photosensitive element 10 may be, for example, but not limited to, as follows: Figure 2The image shows a photodiode (PD). During an exposure period, the photosensitive element 10 is exposed to incident light through the control of a shutter, thereby accumulating charge in the photodiode (PD). The total amount of charge accumulated in the photodiode (PD) is proportional to the light intensity.

[0068] An array formed by pixel circuits 102 can constitute an image sensor. Furthermore, the array of pixel circuits 102 can be exposed using a global shutter scheme. In this case, all pixel circuits 102 in the array can be simultaneously exposed using a global shutter within the same exposure cycle. And, in this case, after simultaneous exposure, the charge of each pixel circuit 102 in the array can be read in a specific order.

[0069] The floating diffusion node FD can be connected to a capacitor Cfd. This capacitor Cfd can be formed, for example, through a PN junction adjacent to a floating diffusion region of the transfer switching switch MTG.

[0070] The transfer switching switch MTG is electrically connected between the photosensitive element 10 and the floating diffusion node FD. The transfer switching switch MTG controls the transfer of charge from the photosensitive element 10 to the floating diffusion node FD by controlling the voltage level of a transfer switching signal TG.

[0071] The reset transistor MR is used to discharge the charge from the floating diffusion node FD in a reset state. When the reset transistor MR is turned on, a voltage Vfd on the floating diffusion node FD is reset to a reset voltage Vrst (e.g., a low level), thus putting the pixel circuit 102 in a reset state. The reset transistor MR is controlled by a reset signal RST.

[0072] One input of buffer amplifier 50 is coupled to the floating diffusion node FD. Buffer amplifier 50 generates a buffered output signal SA based on the voltage Vfd on the floating diffusion node FD.

[0073] The first sample-and-hold stage SH1 and the second sample-and-hold stage SH2 are cascaded between the buffer amplifier 50 and the amplifier circuit 40. The second sample-and-hold stage SH2 is used to sample or sample and hold the buffered output signal SA, and generates a second sample-and-hold signal SN2 at a node N2. The first sample-and-hold stage SH1 is used to sample and hold the second sample-and-hold signal SN2, and generates a first sample-and-hold signal SN1 at a node N1.

[0074] Amplifier circuit 40 is independently connected to the output terminals (i.e., node N1) of the first sample-and-hold stage SH1 and the second sample-and-hold stage SH2 (i.e., node N2). Specifically, on the one hand, amplifier circuit 40 can directly sense the first sample-and-hold signal SN1, regardless of the amount of charge stored in the second sample-and-hold stage SH2 (charge can also be equivalently considered as related to voltage). On the other hand, amplifier circuit 40 can directly sense the second sample-and-hold signal SN2, regardless of the amount of charge stored in the first sample-and-hold stage SH1.

[0075] Please continue reading Figure 2 In one embodiment, the first sample-and-hold stage SH1 includes a sampling switch S1 and a holding capacitor C1. The sampling switch S1 is coupled between the input and output terminals of the first sample-and-hold stage SH1, and the sampling switch S1 and the holding capacitor C1 are connected to the output terminal of the first sample-and-hold stage SH1. The sampling switch S1 is controlled by a sample-and-hold control signal SC1. In one embodiment, the second sample-and-hold stage SH2 includes a sampling switch S2 and a holding capacitor C2. The sampling switch S2 is coupled between the input and output terminals of the second sample-and-hold stage SH2, and the sampling switch S2 and the holding capacitor C2 are connected to the output terminal of the second sample-and-hold stage SH2. The sampling switch S2 is controlled by a sample-and-hold control signal SC2.

[0076] Please see Figure 3 It displays schematic diagrams of operating waveforms corresponding to various embodiments of the present invention. Please refer to... Figure 3 And compare Figure 2 In one embodiment, during a global exposure cycle (e.g.: Figure 3 The first time period shown in Tgec) (e.g.: Figure 3 Within the first time period T1, the second sample-and-hold stage SH2 samples the buffered output signal SA with a first voltage V1 to generate a second sample-and-hold signal SN2 with the first voltage V1 at node N2. It is worth noting that the sampling switch S2 is on during the first time period T1.

[0077] During the first time period T1, simultaneously, the first sample-and-hold stage SH1 samples and holds the second sample-and-hold signal SN2, which has a first voltage V1, so that the output of the first sample-and-hold stage SH1 (i.e., the first sample-and-hold signal SN1) also has the first voltage V1. It is worth noting that during the first time period T1, a pulse is transmitted via the control signal SC1 to control the sampling switch S1 to be in a conducting state, and before the end of the first time period T1, the sampling switch S1 is controlled to be non-conducting (i.e., the first voltage V1 is stored in the first sample-and-hold stage SH1). In one embodiment, before the first sample-and-hold stage SH1 and the second sample-and-hold stage SH2 begin sampling, the reset transistor MR switches to a non-conducting state (meaning the reset signal RST switches from a high level previously within period T0 to a low level).

[0078] In one embodiment, the first voltage V1 is related to a first state of the floating diffusion node FD. In one embodiment, the first state of the floating diffusion node FD may correspond to, for example, the aforementioned reset state. Specifically, the first time period may correspond to, for example... Figure 3 The first time period T1 is shown. Before the start of the first time period T1, the reset transistor MR is turned on (i.e., the reset signal RST is at a high level), thereby resetting the voltage on the floating diffusion node FD to the reset voltage Vrst (e.g., a low level; meaning that at this time, within period T0, the charge on the floating diffusion node FD is completely drained). In one embodiment, simultaneously, the transfer switching signal TG also transmits a high-level pulse, thereby resetting the photosensitive element 10 to the reset voltage Vrst (i.e., at this time, within period T0, the charge on the photosensitive element 10 is also completely drained). In one embodiment, in the reset state, the voltage level of the buffered output signal SA corresponds to the first voltage V1.

[0079] It is worth noting that, since the second sample-and-hold stage SH2 samples the buffered output signal SA with the first voltage V1 during the first time period T1, the voltage level of the second sample-and-hold signal SN2 is also equal to the first voltage V1. Furthermore, since the first sample-and-hold stage SH1 samples and holds the second sample-and-hold signal SN2 with the first voltage V1 during the first time period T1, the voltage level of the output terminal of the first sample-and-hold stage SH1 (i.e., the first sample-and-hold signal SN1) is also equal to the first voltage V1.

[0080] Please continue reading Figure 3 And compare Figure 2Within a second time period (e.g., T2), the second sample-and-hold stage SH2 samples and holds a buffered output signal SA having a second voltage V2 to generate a second sample-and-hold signal SN2 having the second voltage V2. In one embodiment, the second voltage V2 is related to a second state of the floating diffusion node FD. In one embodiment, the second state of the floating diffusion node FD may correspond to, for example, a sensing state. Specifically, in one embodiment, as... Figure 3 As shown, in the second state (i.e., the sensing state), during the transfer period Ttr, a pulse controls the transfer switching switch MTG (by controlling the transfer switching signal TG during the transfer period Ttr), thereby completely transferring the charge accumulated by the photosensitive element 10 during the exposure period Texp to the floating diffusion node FD. Thus, the voltage Vfd on the floating diffusion node FD represents the amount of charge sensed by the photosensitive element 10 during the exposure period Texp. After the charge is transferred from the photosensitive element to the floating diffusion node FD, the voltage level of the buffered output signal SA becomes the second voltage V2 (e.g., ...). Figure 3 (As shown). It is worth noting that the second voltage V2 of the buffered output signal SA also represents the amount of charge sensed by the photodiode PD within the exposure period Texp, and can be regarded as a version amplified or buffered by the amplifier circuit 40. The relationship between its voltage level and charge is related to the configuration of the amplifier circuit 40.

[0081] Please continue reading Figure 3 And compare Figure 2 In one embodiment, during a third time period (e.g., T3), a first sample-and-hold signal SN1 having a first voltage V1 and a second sample-and-hold signal SN2 having a second voltage V2 are independently sensed by amplifier circuit 40, thereby generating a corresponding first output signal and a corresponding second output signal respectively and independently.

[0082] From one perspective, when the first state corresponds to the reset state and the second state corresponds to the sensing state, on the one hand, in the reset state, the first output signal corresponds to a reference signal (corresponding to...). Figure 3 (Ref. shown below), where this reference signal reflects that the floating diffusion node FD is in a reset state. On the other hand, in the sensing state, the second output signal corresponds to a sensing signal (corresponding to...). Figure 3 As shown in sig. (hereinafter the same), this sensing signal can reflect the voltage Vfd of the floating diffusion node FD when the photosensitive element 10 has been exposed and the charge has been transferred to the floating diffusion node FD.

[0083] In one embodiment, a noise correction signal is generated based on a first output signal and a second output signal. In one embodiment, when the first output signal corresponds to the aforementioned reset state and the second output signal corresponds to the aforementioned sensing state, the noise correction signal can be obtained, for example, by subtracting the first output signal (i.e., the reset signal) from the second output signal (i.e., the sensing signal). The noise of the photodiode (PD) present in the second output signal can be canceled by subtracting the first output signal, which represents the noise, from the second output signal.

[0084] In one embodiment, the first output signal and the second output signal may correspond to, as follows: Figure 2 The pixel line PXO is shown.

[0085] like Figure 2 As shown, in one embodiment, multiple pixel circuits (e.g., 102) can be arranged in at least one column, wherein these multiple pixel circuits share the same pixel line PXO. In this embodiment, an analog-to-digital converter (ADC) 80 can be used to convert the voltage level on the pixel line PXO. In this embodiment, the first output signal and the second output signal can correspond to the corresponding output code converted by the ADC 80 (e.g., ...). Figure 2 (DO shown).

[0086] Please continue reading Figure 2 From one perspective, the statement that "the first sample-and-hold signal SN1 having a first voltage V1 and the second sample-and-hold signal SN2 having a second voltage V2 are independently sensed by the amplifier circuit 40" means that the first output signal is generated by directly sensing the first sample-and-hold signal SN1, and the second output signal is generated by directly sensing the second sample-and-hold signal SN2.

[0087] Please continue reading Figure 2 From another perspective, the term "independently" in this embodiment means that the amplifier circuit 40 can directly sense the first sample-and-hold signal SN1 without needing to sense the second sample-and-hold signal SN2, and the amplifier circuit 40 can directly sense the second sample-and-hold signal SN2 without needing to sense the first sample-and-hold signal SN1.

[0088] Please continue reading Figure 3 In this embodiment, within an equalization period Teq, the first sample-and-hold signal SN1 having a first voltage V1 and the second sample-and-hold signal SN2 having a second voltage V2 are equalized to each other, such that after the equalization period Teq, both the first sample-and-hold signal SN1 and the second sample-and-hold signal SN2 have an equalized voltage Veq.

[0089] Please see Figure 4 This illustrates one embodiment of the amplifier circuit (i.e., amplifier circuit 40) of the pixel circuit according to the present invention. Figure 4 As shown, in one embodiment, the amplifier circuit 40 includes a first readout amplifier 41 and a second readout amplifier 42. The input terminal of the first readout amplifier 41 is connected to the output terminal (i.e., node N1) of the first sample-and-hold stage SH1. The input terminal of the second readout amplifier 42 is connected to the output terminal (i.e., node N2) of the second sample-and-hold stage SH2.

[0090] Please see Figure 4 And compare Figure 3 In this embodiment, within a fourth time period T4, the first read amplifier 41 senses a first sample-and-hold signal SN1 with an equalized voltage Viq to generate a first offset signal Sos1, and the second read amplifier 42 senses a second sample-and-hold signal SN2 with an equalized voltage Viq to generate a second offset signal Sos2. The first offset signal Sos1 and the second offset signal Sos2 represent the offset between the first read amplifier 41 and the second read amplifier 42 when both sense the same signal (e.g., the equalized voltage Viq). This offset can be further canceled out in subsequent signal sensing steps.

[0091] It is worth noting that, in one embodiment, during the equalization period Teq, switch S1 can be turned on and off again (i.e., the solid line portion of SC1), thereby performing the equalization function. In another embodiment, switch S1 can be continuously turned on until the sensing of both the first sample-and-hold signal SN1 and the second sample-and-hold signal SN2 has ended (i.e., the dashed line portion of SC1).

[0092] In one embodiment, an offset compensation signal Sosc is generated based on a first output signal, a second output signal, the aforementioned first offset signal Sos1, and the aforementioned second offset signal Sos2. In a non-limiting example, the offset compensation signal Sosc can be obtained, for example, but not limited to, the following:

[0093] Sosc = (Second output signal – Sos2) – (First output signal – Sos1).

[0094] In this embodiment, the noise and offset of the aforementioned sensing signal (i.e., the second output signal) are canceled out.

[0095] Please see Figure 5 This illustrates a more specific embodiment of the pixel circuit according to the present invention. Figure 5 As shown, in one embodiment, the buffer amplifier 50 includes a sensing buffer transistor M51, wherein a gate of the sensing buffer transistor 51 is connected to a floating diffusion node FD; a source of the sensing buffer transistor 51 is connected to an input terminal of a second sample-and-hold stage SH2; and a drain of the sensing buffer transistor 51 is connected to a buffer supply signal VSF. From one perspective, in this embodiment, the buffer amplifier 50 employs a sensing buffer transistor M51 configured as a source follower to generate a buffered output signal SA.

[0096] Please see Figure 5 And compare Figure 3 In one embodiment, before the sensing buffer transistor M51 senses the first or second state of the floating diffusion node FD (e.g.: Figure 3 As shown in T1), a low-order quasi-pulse is generated in the buffer supply signal VSF to reset the buffered output signal SA. Figure 5 As shown, in this embodiment, the buffer amplifier 50 uses only the sensing buffer transistor M51 configured as a source follower stage, without any pull-down components. In this situation, the sensing buffer transistor M51 can reflect the rising change of the voltage Vfd of the floating diffusion node FD at its source (i.e., the buffered output signal SA); however, the sensing buffer transistor M51 cannot reflect the falling change of the voltage Vfd of the floating diffusion node FD at its source (i.e., the buffered output signal SA). In one embodiment, before the sensing buffer transistor M51 begins sensing the voltage Vfd of the floating diffusion node FD, a low-level quasi-pulse needs to be generated in the buffer supply signal VSF (e.g., in...). Figure 3 Within T1 and T2 (as shown), in order to reset the buffered output signal SA to a low level, thereby in subsequent time periods (e.g., during...). Figure 3 The voltage Vfd of the floating diffusion node FD can be effectively sensed during the time period after T2 (as shown).

[0097] Please continue reading Figure 3 In another embodiment, before the second sample-and-hold stage SH2 is held (e.g., before SC2 transitions to a low level), the buffer supply signal VSF generates a low-level pulse to reset the buffered output signal SA, thereby pre-discharging the second sample-and-hold stage SH2 (i.e., VSF, as shown in the image). Figure 3 (The dashed line shown is inside Ttr).

[0098] Please continue reading Figure 5 And compare Figure 3In one embodiment, the first readout amplifier 41 includes a first readout buffer transistor MR1 and a first readout switch MS1. A gate of the first readout buffer transistor MR1 is connected to the output of a first sample-and-hold stage SH1 to sense a first sample-and-hold signal SN1. The first readout switch MS1 is connected to a source of the first readout buffer transistor MR1 and an output of the first readout amplifier 41 to control the connection between the first readout buffer transistor MR1 and the pixel line PXO. The second readout amplifier 42 includes a second readout buffer transistor MR2 and a second readout switch MS2. A gate of the second readout buffer transistor MR2 is connected to the output of a second sample-and-hold stage SH2 to sense a second sample-and-hold signal SN2. The second readout switch MS2 is connected to a source of the second readout buffer transistor MR2 and an output of the second readout amplifier 42 to control the connection between the second readout buffer transistor MR2 and the pixel line PXO.

[0099] Please continue reading Figure 5 And compare Figure 3 The first read switch MS1 is controlled by a control signal RS1, while the second read switch MS2 is controlled by a control signal RS2. For example... Figure 3 As shown, when the first sample-and-hold signal SN1 or the second sample-and-hold signal SN2 is sensed independently through the corresponding first readout amplifier 41 or second readout amplifier 42 (e.g.: Figure 3 As shown in T3 and T4, control signal RS1 or control signal RS2 will correspondingly generate high-level pulses.

[0100] It is worth noting that, in this embodiment, as Figure 3 As shown, within time period T3 or T4, the time point at which the second sample-and-hold signal SN2 is sensed is earlier than the time point at which the first sample-and-hold signal SN1 is sensed. However, this arrangement of sensing time points is not intended to limit the scope of the invention; that is, conversely, in another embodiment, the time point at which the first sample-and-hold signal SN1 is sensed may also be earlier than the time point at which the second sample-and-hold signal SN2 is sensed.

[0101] Please see Figure 6 This shows a schematic diagram of another, more specific embodiment of the pixel circuit (i.e., pixel circuit 106) according to the present invention. Please refer to... Figure 7 Its display corresponds to Figure 6 A schematic diagram of the operating waveforms of an embodiment. For example... Figure 6As shown, in one embodiment, the buffer amplifier 50 further includes a current source 52. The current source 52 is connected to the source of the sensing buffer transistor M51. In this embodiment, since the current source 52 can pull down the source of the sensing buffer transistor M51, when the voltage Vfd on the floating diffusion node FD (i.e., the gate of the sensing buffer transistor M51) becomes low, the buffered output signal SA (i.e., the source of the sensing buffer transistor M51) can still effectively reflect the change in the voltage Vfd on the floating diffusion node FD. As described above... Figure 3 and Figure 5 The difference between the aforementioned embodiments is that: Figure 3 and Figure 5 The described embodiment requires pulling down the drain of the sensing buffer transistor M51 (i.e., the buffer supply signal VSF) to a low level; however, this embodiment does not require this step. Figure 6 and Figure 7 As shown, in this embodiment, a fixed supply voltage VDD can be provided to the drain of the sensing buffer transistor M51 (i.e., buffer supply signal VSF).

[0102] Please continue reading Figure 6 And compare Figure 7 In one embodiment, the current source 52 includes a bias transistor MB, wherein the bias transistor MB can be biased by a bias voltage VB. The bias transistor MB is used to provide a bias current to the sensing buffer transistor M51. In one embodiment, the current source 52 further includes a bias control switch SB, wherein the bias control switch SB can, for example, Figure 7 The time periods outside of T1, Ttr, and T2 are used to cut off the bias current, thereby saving power. The bias control switch SB is controlled by the control signal SBC.

[0103] Please see Figure 8 This shows a schematic diagram of an embodiment of the pixel circuit (i.e., pixel circuit 108) according to the present invention. Please refer to... Figure 9 Its display corresponds to Figure 8 The schematic diagram shows the operation waveforms of an embodiment. Pixel circuit 108 is similar to... Figure 6 The pixel circuit 108 shown differs from pixel circuit 106 in that it omits the bias control switch SB. In this embodiment, during time periods T1, Ttr, and T2, the bias current is provided only when the bias voltage VB is controlled at a level equal to Vbias. This embodiment can control the bias voltage VB to a level equal to Vbias during time periods outside of T1, Ttr, and T2. Figure 9 The low level shown shuts off the bias current to save power.

[0104] Please see Figure 10This shows a schematic diagram of an embodiment of the pixel circuit (i.e., pixel circuit 110) according to the present invention. Please refer to... Figure 11 Its display corresponds to Figure 10 The operation waveform diagram of the embodiment is shown below. Figure 10 The pixel circuit 110 shown is similar to Figure 5 The pixel circuit 105 shown differs in that: the sensing buffer transistor M51 and the first read buffer transistor MR1' have complementary conductivity types, and the sensing buffer transistor M51 and the second read buffer transistor MR2' have complementary conductivity types. This causes an offset level of the sensing buffer transistor M51 to cancel out an offset level of the first read buffer transistor MR1', and vice versa. In a non-limiting example, such as... Figure 10 As shown, in this embodiment, the sensing buffer transistor M51 is an NMOS transistor, while both the first read buffer transistor MR1' and the second read buffer transistor MR2' are PMOS transistors. The gate-to-source voltage (VGS) of the sensing buffer transistor M51 cancels out the gate-to-source voltages of the first read buffer transistor MR1' and the second read buffer transistor MR2'. Furthermore, it is worth noting that in this embodiment, the aforementioned offset levels correspond to the gate-to-source voltages of the sensing buffer transistor M51, the first read buffer transistor MR1', and the second read buffer transistor MR2', respectively.

[0105] It is worth noting that, in Figure 10 In the illustrated embodiment, although the conductivity types of both the first read buffer transistor MR1' and the second read buffer transistor MR2' are complementary to those of the sensing buffer transistor M51, this is not intended to limit the scope of the invention. In another embodiment, the conductivity types of at least one of the first read buffer transistor MR1' and the second read buffer transistor MR2' being complementary to those of the sensing buffer transistor M51 also fall within the scope of the invention.

[0106] Furthermore, it is worth noting that, such as Figure 10 As shown, read switches MS1' and MS2' can also be implemented as PMOS transistors. In this embodiment, as... Figure 11 As shown, when the first sample-and-hold signal SN1 or the second sample-and-hold signal SN2 is independently sensed through the corresponding first readout amplifier 41' or second readout amplifier 42', the corresponding control signals RS1' and RS2' can, for example, generate a low-level quasi-pulse within time periods T3 and T4. Compared to Figure 3 , Figure 11 The control signals RS1' and RS2' shown are... Figure 3 The control signals RS1 and RS2 shown are out of phase with each other.

[0107] like Figure 5 , Figure 6 , Figure 8 or Figure 10 As shown, in one embodiment, an output terminal of the first read amplifier 41 (or the first read amplifier 41') and an output terminal of the second read amplifier 42 (or the corresponding second read amplifier 42') are short-circuited to a pixel line PXO. That is, in this embodiment, the first read amplifier 41 (or the first read amplifier 41') and the second read amplifier 42 (or the corresponding second read amplifier 42') share the same pixel line PXO.

[0108] Please see Figure 12 This shows a schematic diagram of an embodiment of the pixel circuit (i.e., pixel circuit 112) according to the present invention. Please refer to... Figure 13 Its display corresponds to Figure 12 The operation waveform diagram of the embodiment is shown below. Figure 12 The pixel circuit 112 shown is similar to Figure 5 The pixel circuit 105 shown differs in that: an output terminal of the first readout amplifier 41 is connected to a first pixel line PXO1, and an output terminal of the second readout amplifier 42 is connected to a second pixel line PXO2. That is, in this embodiment, the first readout amplifier 41 and the second readout amplifier 42 are read through different pixel lines PXO.

[0109] like Figure 12 and Figure 13 As shown, in one embodiment, the read switches MS1 and MS2 of the amplifier circuit 40” are both controlled by a single control signal RSS, wherein the control signal RSS may generate a high-level pulse, for example, within time periods T3 and T4.

[0110] Please see Figure 14 It shows a schematic diagram of an embodiment of the pixel circuit (i.e., pixel circuit 114) according to the present invention. Figure 14 The pixel circuit 114 shown is similar to Figure 2 The pixel circuit 102 shown differs in that: pixel circuit 114 can adjust the capacitance value of the floating diffusion node FD via an adjustment signal SG, causing pixel circuit 114 to operate in at least one of the following modes:

[0111] (1) a low conversion gain mode, wherein the floating diffusion node FD is adjusted to have a first equivalent capacitance value; (2) a high conversion gain mode, wherein the floating diffusion node FD is adjusted to have a second equivalent capacitance value, wherein the second equivalent capacitance value is less than the first equivalent capacitance value; and / or (3) a high dynamic range (HDR) mode, wherein the capacitance value of the floating diffusion node FD switches between the first equivalent capacitance value and the second equivalent capacitance value.

[0112] Since the first equivalent capacitance value is greater than the second equivalent capacitance value, when the amount of charge transferred from the photodiode PD to the floating diffusion node FD is fixed, the voltage Vfd of the floating diffusion node FD with the first equivalent capacitance value (i.e., low conversion gain) changes less with the change of charge than the voltage Vfd of the floating diffusion node FD with the second equivalent capacitance value (i.e., high conversion gain).

[0113] It is worth noting that when the pixel circuit 114 operates in High Dynamic Range (HDR) mode, a non-linear conversion gain curve can be established by switching different equivalent capacitance values ​​to achieve the effect of high dynamic range. Those skilled in the art can deduce the relevant operating details by analogy from the teachings of this invention.

[0114] Please continue reading Figure 14 In one specific embodiment, Figure 14 The pixel circuit 114 shown is Figure 2 The difference in the pixel circuit 102 shown is: Figure 14 The pixel circuit 114 shown also includes an adjustment switch MSG and an adjustment capacitor Cp, so that the floating diffusion node FD can selectively have a first equivalent capacitance value (i.e., Cfd+Cp) or a second equivalent capacitance value (i.e., Cfd), thereby achieving the different operating modes mentioned above.

[0115] Specifically, such as Figure 14As shown, the adjustment switch MSG is connected between the reset transistor MR and the floating diffusion node FD. The adjustment switch MSG is controlled by the adjustment signal SG, and the adjustment capacitor Cp is connected to a junction node Nadj where the reset transistor MR and the adjustment switch MSG are connected. When the adjustment switch MSG is on, the floating diffusion node FD has an equivalent capacitance value, which is equal to the sum of the floating diffusion capacitance value Cfd and the adjustment capacitor Cp. This equivalent capacitance value corresponds to the first equivalent capacitance value. When the adjustment switch MSG is off, the equivalent capacitance value of the floating diffusion node FD is only equal to the floating diffusion capacitance value Cfd. This equivalent capacitance value corresponds to the second equivalent capacitance value. As mentioned earlier, the second equivalent capacitance value is less than the first equivalent capacitance value.

[0116] Please see Figure 15 Its display corresponds to Figure 14 A schematic diagram of the operating waveforms of an embodiment. For example... Figure 15 As shown, in low conversion gain mode, the adjustment switch MSG is always on (i.e., the floating diffusion node FD has a high equivalent capacitance value), and a low-gain correction signal is generated based on the first output signal and the second output signal (e.g., within or after time period T3). It is worth noting that in low conversion gain mode, the first and second output signals are obtained in a manner similar to that described in the foregoing embodiments. Specifically, in the first state (i.e., the reset state), by within time period T0, such as... Figure 15 As shown, by controlling the reset of transistor MR with a pulse, the charge of the floating diffusion node FD is completely drained. Furthermore, in the second state (i.e., the sensing state), within the time period Ttr, as... Figure 15 As shown, by controlling the transfer switching switch MTG with a pulse, the charge accumulated by the photosensitive element 10 during the exposure period Texp is completely transferred to the floating diffusion node FD. From one perspective, in the reset state, the first output signal corresponds to a reference signal that reflects that the floating diffusion node FD is in the reset state. On the other hand, in the sensing state, the second output signal corresponds to a sensing signal that reflects the voltage Vfd of the floating diffusion node FD in the low conversion gain mode, after the photosensitive element 10 has undergone exposure and the charge has been transferred to the floating diffusion node FD. It is worth noting that the low conversion gain mode can also be considered a highly saturated mode.

[0117] Please see Figure 16 Its display corresponds to Figure 14A schematic diagram of the operating waveforms of an embodiment. When the pixel circuit 114 operates in high conversion gain mode, and when the first sample-and-hold stage SH1 and the second sample-and-hold stage SH2 sample and hold the first voltage V1 corresponding to the first state and the second voltage V2 corresponding to the second state, respectively, the adjustment switch MSG is not turned on (i.e., within time periods T1, Ttr, and T2, the floating diffusion node FD has a low equivalent capacitance value). A high-gain correction signal is generated based on the first output signal and the second output signal (e.g., within or after time period T3). It is worth noting that in high conversion gain mode, the first output signal and the second output signal are obtained in a manner similar to that described in the foregoing embodiment. Specifically, in the first state (i.e., the reset state), by within time period T0, such as Figure 16 As shown, by controlling the reset of transistor MR with a pulse, the charge of the floating diffusion node FD is completely drained. Furthermore, in the second state (i.e., the sensing state), within the time period Ttr, as... Figure 16 As shown, by controlling the transfer switching switch MTG with a pulse, the charge accumulated by the photosensitive element 10 during the exposure period Texp is completely transferred to the floating diffusion node FD. From one perspective, in the reset state, the first output signal corresponds to a reference signal that reflects that the floating diffusion node FD is in the reset state. On the other hand, in the sensing state, the second output signal corresponds to a sensing signal that reflects the voltage Vfd of the floating diffusion node FD in the high conversion gain mode, after the photosensitive element 10 has undergone exposure and the charge has been transferred to the floating diffusion node FD. It is worth noting that the high conversion gain mode can also be considered a high sensitivity mode.

[0118] Please see Figure 17 Its display corresponds to Figure 14 A schematic diagram of the operating waveforms of an embodiment. Please refer to... Figure 17 and Figure 14 As previously mentioned, when the pixel circuit 114 operates in High Dynamic Range (HDR) mode, the high dynamic range effect is achieved by switching the capacitance value of the floating diffusion node FD between a first equivalent capacitance value and a second equivalent capacitance value. Specifically, in High Dynamic Range (HDR) mode, after the reset state of time period T0, the pixel circuit 114 first operates in a sensing state in a high conversion gain sub-mode, at which time the adjustment switch MSG is not turned on. Under this condition, within time period Ttr, such as Figure 17As shown, by controlling the transfer switching switch MTG with a pulse, the charge accumulated by the photosensitive element 10 during the exposure period Texp is completely transferred to the floating diffusion node FD with a second equivalent capacitance value (lower equivalent capacitance value), thereby generating a first output signal, which corresponds to a sensing signal in the high conversion gain submode.

[0119] Next, when the pixel circuit 114 operates in the sensing state of the low conversion gain submode, the adjustment switch MSG is turned on, and the charge in the floating diffusion node FD (after time periods Texp and T1) is within the time period Tshr, such as Figure 17 As shown, the charge is redistributed (i.e., the charge is shared or equalized) according to the first equivalent capacitance value (i.e., from Cfd to Cfd+Cp), thereby generating a second output signal, which corresponds to a sensing signal in the low conversion gain submode. In the high dynamic range mode, the high dynamic range signal is generated based on the first output signal and the second output signal.

[0120] exist Figure 17 In the illustrated embodiment, the first output signal and the second output signal correspond to a sensing signal generated under the same exposure in the high conversion gain submode and the low conversion gain submode, respectively.

[0121] Please see Figure 18 The diagram shows a more specific embodiment of the pixel circuit (i.e., pixel circuit 118) according to the present invention. In one embodiment, the amplifier circuit 43 includes a readout amplifier 45 and a selector circuit 46. The readout amplifier 45 is used to sense a first sample-and-hold signal SN1 or a second sample-and-hold signal SN2 to generate a corresponding first output signal or a corresponding second output signal.

[0122] Selector circuit 46 is used to select either the output terminal of the first sample-and-hold stage SH1 (i.e., the first sample-and-hold signal SN1) or the output terminal of the second sample-and-hold stage SH2 (i.e., the second sample-and-hold signal SN2), so that it is electrically connected to an input terminal of read amplifier 45, thereby enabling the read amplifier to read the signal during the third time period (e.g.: Figures 15-17 The corresponding first output signal or the corresponding second output signal is generated within T3 as shown.

[0123] Please see Figure 19This diagram illustrates a more specific embodiment of the pixel circuit (i.e., pixel circuit 119) according to the present invention. In one embodiment, the readout amplifier 45 includes a readout buffer transistor MR5 and a readout switch MS5. The selector circuit 46 includes a selector switch SL1 and a selector switch SL2. The selector switches SL1 and SL2 are used to select either a first sample-and-hold signal SN1 or a second sample-and-hold signal SN2, so that it is electrically connected to the gate of the readout buffer transistor MR5. The readout switch MS5 is used to control the coupling between the readout buffer transistor MR5 and the pixel line PXO. The selector switches SL1 and SL2 are controlled by the selector control signals SLC1 and SLC2, respectively. The readout switch MS5 is controlled by the control signal RS5.

[0124] Please see Figure 19 And compare Figures 15-17 In one embodiment, in such... Figures 15-17 During the time period T3 shown, the first sample-and-hold signal SN1 and the second sample-and-hold signal SN2 are sensed one after another by the readout amplifier 45.

[0125] Please see Figure 20 This shows a schematic diagram of an embodiment of the pixel circuit (i.e., pixel circuit 120) according to the present invention. Please refer to... Figure 21 Its display corresponds to Figure 20 The operation waveform diagram of the embodiment is shown below. Figure 20 The pixel circuit 120 shown is similar to Figure 19 The pixel circuit 119 shown differs in that the buffer amplifier 50 further includes a current source 52. The current source 52 is connected to the source of the sensing buffer transistor M51. Since the structure and operation mechanism of the buffer amplifier 50 with the current source 52 are similar to... Figure 6 The pixel circuit 106 shown is not described in detail here.

[0126] Please see Figure 22 This shows a schematic diagram of an embodiment of the pixel circuit (i.e., pixel circuit 122) according to the present invention. Please refer to... Figure 23 Its display corresponds to Figure 22 The operation waveform diagram of the embodiment is shown below. Figure 22 The pixel circuit 122 shown is similar to Figure 20 The pixel circuit 120 shown differs in that: compared to Figure 20 The pixel circuit 120 shown is in Figure 22 In the pixel circuit 122 shown, the bias control switch is omitted. In this embodiment, the bias voltage VB can be controlled to a certain value during time periods, for example, outside of time periods T1, Ttr, and T2. Figure 23The low level shown shuts off the bias current to save power.

[0127] Please see Figure 24 It shows a schematic diagram of an embodiment of the pixel circuit (i.e., pixel circuit 124) according to the present invention. Figure 24 The pixel circuit 124 shown is similar to Figure 19 The pixel circuit 119 shown differs in that the pixel circuit 124 further includes a third sample-and-hold stage SH3 and a fourth sample-and-hold stage SH4. The third sample-and-hold stage SH3 and the fourth sample-and-hold stage SH4 are cascaded between the buffer amplifier 50 and the amplifier circuit 43'. The fourth sample-and-hold stage SH4 is used to sample or sample and hold the buffered output signal SA, thereby generating a fourth sample-and-hold signal SN4. The third sample-and-hold stage SH3 is used to sample and hold the fourth sample-and-hold signal SN4, thereby generating a third sample-and-hold signal SN3.

[0128] In addition to having a similar configuration to the amplifier circuits in the other embodiments described above, in this embodiment, the amplifier circuit 43' is further electrically connected independently to the output terminal (i.e., node N3) of the third sample-and-hold stage SH3 and the output terminal (i.e., node N4) of the fourth sample-and-hold stage SH4. Specifically, on the one hand, the amplifier circuit 43' can directly sense the third sample-and-hold signal SN3, regardless of the amount of charge (which can also be equivalently regarded as a voltage) stored in the fourth sample-and-hold stage SH4. On the other hand, the amplifier circuit 43' can directly sense the fourth sample-and-hold signal SN4, regardless of the amount of charge stored in the third sample-and-hold stage SH3.

[0129] In one embodiment, the selector circuit 46' of the amplifier circuit 43' includes: selection switch SL1, selection switch SL2, selection switch SL3, and selection switch SL4. Selection switches SL1, SL2, SL3, and SL4 are respectively controlled by selection control signals SLC1, SLC2, SLC3, and SLC4, thereby selecting one of the four sample-and-hold signals SN1, SN2, SN3, or SN4, and electrically connecting it to the gate of the read buffer transistor MR5.

[0130] Please continue reading Figure 24 And compare Figure 25In one embodiment, the pixel circuit 124 operates in a High Dynamic Range (HDR) mode, wherein the capacitance value of the floating diffusion node FD of the pixel circuit 124 switches between a first equivalent capacitance value (corresponding to a low conversion gain submode) and a second equivalent capacitance value (corresponding to a high conversion gain submode). In this embodiment, the four sample-and-hold stages (i.e., the first sample-and-hold stage SH1, the second sample-and-hold stage SH2, the third sample-and-hold stage SH3, and the fourth sample-and-hold stage SH4) can respectively sample and hold the reset state and sensing state corresponding to the high conversion gain submode and the low conversion gain submode, for a total of four voltages. Furthermore, the amplifier circuit 43' can sense the four voltages of the four sample-and-hold stages (i.e., the first sample-and-hold stage SH1, the second sample-and-hold stage SH2, the third sample-and-hold stage SH3, and the fourth sample-and-hold stage SH4) respectively and independently to generate corresponding first output signals, second output signals, third output signals, and fourth output signals respectively and independently. In one embodiment, the first output signal, the second output signal, the third output signal, and the fourth output signal may, for example, correspond to a reference signal in a low conversion gain submode, a sensing signal in a high conversion gain submode, and a reference signal in a high conversion gain submode, and a sensing signal in a low conversion gain submode, respectively. A high dynamic range offset compensation signal is generated based on the first output signal, the second output signal, the third output signal, and the fourth output signal. It is worth noting that, in this embodiment, the high dynamic range offset compensation signal can simultaneously achieve the effects of high dynamic range and dark noise (i.e., corresponding to the reset state) correction.

[0131] In a non-limiting example, one of the first sample-and-hold stage SH1 and the third sample-and-hold stage SH3 may sample and hold the reference signal in a high conversion gain submode, while the other of the first sample-and-hold stage SH1 and the third sample-and-hold stage SH3 may sample and hold the reference signal in a low conversion gain submode. Furthermore, in a non-limiting example, one of the second sample-and-hold stage SH2 and the fourth sample-and-hold stage SH4 may sample and hold the sense signal in a high conversion gain submode, while the other of the second sample-and-hold stage SH2 and the fourth sample-and-hold stage SH4 may sample and hold the sense signal in a low conversion gain submode.

[0132] Please see Figure 25 Its display corresponds to Figure 24 A detailed operational waveform diagram of the embodiment is provided. Please refer to [link / reference]. Figure 24 And compare Figure 25In one embodiment, the pixel circuit 124 operates according to the following timing sequence: a first time period T1, a fifth time period T5, a second time period T2, a sixth time period T6, a third time period T3, and a seventh time period T7, in that order. The specific details of the operation of the pixel circuit 124 according to the above timing sequence will be described in detail later.

[0133] Please continue reading Figure 24 And compare Figure 25 .like Figure 25 As shown, within the first time period T1, the second sample-and-hold stage SH2 samples the buffered output signal SA to generate a second sample-and-hold signal SN2 with a first voltage V1 at node N2. Within the first time period T1, the first sample-and-hold stage SH1 samples and holds the second sample-and-hold signal SN2 with the first voltage V1 to generate a first sample-and-hold signal SN1 with the first voltage V1.

[0134] It is worth noting that in this embodiment, during the first time period T1, the adjustment signal SG is at a high level, thereby turning on the adjustment switch MSG, causing the pixel circuit 124 to be in a low conversion gain sub-mode. The first voltage V1 is related to a first state of the floating diffusion node FD. In one embodiment, the first state of the floating diffusion node FD may correspond to the reset state of the low conversion gain sub-mode.

[0135] Next, as Figure 25 As shown, within the fifth time period T5 of the global exposure cycle Tgec, the fourth sample-and-hold stage SH4 samples the buffered output signal SA to generate a fourth sample-and-hold signal SN4 with a third voltage V3. Also, within the fifth time period T5 of the global exposure cycle Tgec, the third sample-and-hold stage SH3 samples and holds the fourth sample-and-hold signal SN4 to generate a third sample-and-hold signal SN3 with a third voltage V3.

[0136] It is worth noting that in this embodiment, during the fifth time period T5, the adjustment signal SG is at a low level, causing the adjustment switch MSG to be de-energized, and the pixel circuit 124 is in a high conversion gain sub-mode. The third voltage V3 is related to a third state of the floating diffusion node FD. In one embodiment, the third state of the floating diffusion node FD may correspond to the reset state of the high conversion gain sub-mode.

[0137] Next, in this embodiment, within the second time period T2, the buffered output signal SA of the second sample-and-hold stage SH2 is sampled and held to generate a second sample-and-hold signal SN2 having a second voltage V2. Wherein, as... Figure 25As shown, the second voltage V2 of the buffered output signal SA (and the second sample-and-hold signal SN2) represents the charge sensed by the photodiode PD during the exposure period Texp, and in the high conversion gain submode, the amount of charge transferred from the photodiode PD to the floating diffusion node FD during the transfer period Ttr (corresponding to the voltage level).

[0138] It is worth noting that in this embodiment, during the transition period Ttr and the second period T2, the adjustment signal SG is at a low level, thereby not turning on the adjustment switch MSG, so that the pixel circuit 124 is in a high conversion gain sub-mode. The second voltage V2 is related to a second state of the floating diffusion node FD. In one embodiment, the second state of the floating diffusion node FD may correspond to the sensing state of the high conversion gain sub-mode.

[0139] Furthermore, it is worth noting that in this embodiment, before the second time period T2 and within the transition time period Ttr, such as Figure 25 As shown, by controlling the transfer switching switch MTG with a pulse, the charge accumulated by the photosensitive element 10 during the exposure period Texp is completely transferred to the floating diffusion node FD with a second equivalent capacitance value (lower equivalent capacitance value), thereby generating a second sample-and-hold signal SN2 with a second voltage V2 (and subsequently generating a second output signal).

[0140] Please continue reading Figure 25 Next, in this embodiment, within the sixth time period T6, the buffered output signal SA of the fourth sample-and-hold stage SH4 is sampled and held to generate a fourth sample-and-hold signal SN4 with a fourth voltage V4. Wherein, as... Figure 25 As shown, the fourth voltage V4 of the buffered output signal SA (and the fourth sample-and-hold signal SN4) represents the charge sensed by the photodiode PD during the exposure period Texp, and the voltage level corresponding to the redistribution of charge in the low conversion gain submode during the period Tshr.

[0141] It is worth noting that in this embodiment, during the sixth time period T6, the adjustment signal SG is at a high level, thereby turning on the adjustment switch MSG, causing the pixel circuit 124 to be in a low conversion gain sub-mode. The fourth voltage V4 is related to a fourth state of the floating diffusion node FD. In one embodiment, the fourth state of the floating diffusion node FD may correspond to the sensing state of the low conversion gain sub-mode.

[0142] Furthermore, it is worth noting that in this embodiment, before the sixth time period T6 and within the time period Tshr, the charge within the floating diffusion node FD (after time periods Texp and T2) within the time period Tshr is adjusted by turning on the control switch MSG so as to... Figure 25As shown, the capacitance is redistributed according to the first equivalent capacitance value (i.e., from Cfd to Cfd+Cp), thereby generating a fourth sample-and-hold signal SN4 with a fourth voltage V4 (and subsequently generating a fourth output signal).

[0143] Please continue reading Figure 25 Next, in one embodiment, as... Figure 25 As shown, during the third time period T3 and the seventh time period T7, the first voltage V1, the second voltage V2, the third voltage V3 and the fourth voltage V4 are independently sensed by the amplifier circuit 43', thereby generating the corresponding first output signal, the corresponding second output signal, the corresponding third output signal and the corresponding fourth output signal, respectively.

[0144] It is worth noting that the first output signal, the second output signal, the third output signal, and the fourth output signal may correspond to signals read through the pixel line PXO or signals read through an analog-to-digital converter (see [link]). Figure 2 The analog-to-digital converter 80 shown converts the signal into digital form for reading. A high dynamic range offset compensation signal is generated based on the first output signal, the second output signal, the third output signal, and the fourth output signal.

[0145] like Figure 24 As shown, in one embodiment, each of the first sample-and-hold stage SH1, the second sample-and-hold stage SH2, the third sample-and-hold stage SH3, and the fourth sample-and-hold stage SH4 includes: a holding capacitor (i.e., holding capacitors C1, C2, C3, and C4 respectively), wherein the holding capacitors C1, C2, C3, and C4 are respectively connected to the output terminal of the corresponding sample-and-hold stage (i.e., the first sample-and-hold stage SH1, the second sample-and-hold stage SH2, the third sample-and-hold stage SH3, and the fourth sample-and-hold stage SH4); and a sampling switch (i.e., sampling switches S1, S2, S3, and S4 respectively), wherein the sampling switches S1, S2, S3, and S4 are respectively connected between the input terminal and the output terminal of the corresponding sample-and-hold stage (i.e., the first sample-and-hold stage SH1, the second sample-and-hold stage SH2, the third sample-and-hold stage SH3, and the fourth sample-and-hold stage SH4). Sampling switches S1, S2, S3 and S4 are controlled by control signals SC1, SC2, SC3 and SC4 respectively.

[0146] This invention provides a pixel circuit with two sample-and-hold stages, wherein these two sample-and-hold stages are cascaded together. Furthermore, these two sample-and-hold stages of the pixel circuit of this invention are used to sequentially sample and hold signals corresponding to different states, modes, and sub-modes. Notably, each sample-and-hold signal is sensed separately and independently. The pixel circuit of this invention can further be used to cancel noise and can sense corresponding signals in high conversion gain mode, low conversion gain mode, or high dynamic range (HDR) mode. An array formed by multiple pixel circuits 102 as units can form a global shutter image sensor, wherein this global shutter image sensor can achieve the effects of fast, high accuracy, and flexible sensitivity.

[0147] The present invention has been described above with reference to preferred embodiments. However, the above description is only intended to facilitate understanding of the invention by those skilled in the art and is not intended to limit the broadest scope of the invention. The described embodiments are not limited to individual application and can also be used in combination. For example, two or more embodiments can be used in combination, and some components of one embodiment can be used to replace corresponding components in another embodiment. Furthermore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations. For example, the phrase "processing or calculating based on a signal or generating an output result" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-to-current conversion, current-to-voltage conversion, and / or proportional conversion on the signal, and then processing or calculating based on the converted signal to generate an output result. Therefore, within the same spirit of the invention, those skilled in the art can conceive of various equivalent changes and combinations, and there are many combinations, which will not be listed here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A pixel circuit, characterized in that, Include: A photosensitive element used to generate an electric charge based on incident light; A floating diffusion node; A reset transistor is used to discharge the charge from the floating diffusion node; A transfer switching switch is coupled between the photosensitive element and the floating diffusion node to control the transfer of charge from the photosensitive element to the floating diffusion node; A buffer amplifier having an input terminal coupled to the floating diffusion node, the buffer amplifier being used to generate a buffered output signal based on a voltage at the floating diffusion node; An amplifier circuit; First sampling hold level; and A second sample-and-hold stage, wherein the first sample-and-hold stage and the second sample-and-hold stage are cascaded between the buffer amplifier and the amplifier circuit; The second sample-and-hold stage is used to sample or sample and hold the buffered output signal to generate a second sample-and-hold signal, and the first sample-and-hold stage is used to sample and hold the second sample-and-hold signal to generate a first sample-and-hold signal. The amplifier circuit is independently electrically connected to an output terminal of the first sample-and-hold stage and an output terminal of the second sample-and-hold stage; During a first time period of a global exposure cycle, the second sample-and-hold stage samples the buffered output signal having a first voltage to generate the second sample-and-hold signal having the first voltage, and the first sample-and-hold stage samples and holds the second sample-and-hold signal to generate the first sample-and-hold signal having the first voltage, wherein the first voltage is related to a first state of the floating diffusion node. During a second time period of the global exposure cycle, the second sample-and-hold stage samples and holds the buffered output signal having a second voltage to generate the second sample-and-hold signal having the second voltage, wherein the second voltage is related to a second state of the floating diffusion node. During a third time period of the global exposure cycle, the first sample-and-hold signal with the first voltage and the second sample-and-hold signal with the second voltage are independently sensed by the amplifier circuit, thereby generating a corresponding first output signal and a corresponding second output signal.

2. The pixel circuit as described in claim 1, wherein, The amplifier circuit is used to sense the first sample-and-hold signal when there is no need to sense the second sample-and-hold signal, and the amplifier circuit is used to sense the second sample-and-hold signal when there is no need to sense the first sample-and-hold signal.

3. The pixel circuit as described in claim 1, wherein, The amplifier circuit includes: A first readout amplifier having an input terminal for receiving the first sample-and-hold signal; and A second readout amplifier having an input terminal for receiving the second sample-and-hold signal; During an equalization period, the first sample-and-hold signal and the second sample-and-hold signal are equalized to each other, such that both the first sample-and-hold signal and the second sample-and-hold signal have an equalized voltage. During a fourth time period of the global exposure cycle, the first readout amplifier senses the equalized voltage to generate a first offset signal, and the second readout amplifier senses the equalized voltage to generate a second offset signal.

4. The pixel circuit as described in claim 3, wherein, An offset compensation signal is generated based on the first output signal, the second output signal, the first offset signal, and the second offset signal.

5. The pixel circuit as described in claim 4, wherein, The first state corresponds to a reset state, in which a pulse is sent to control the reset transistor, causing the charge of the floating diffusion node to be completely drained; and The second state corresponds to a sensing state, in which, after an exposure period, a pulse is sent to control the transfer switching switch, so that the charge in the photosensitive element is completely transferred to the floating diffusion node.

6. The pixel circuit as described in claim 5, wherein, The buffer amplifier includes a sensing buffer transistor; The gate of the sensing buffer transistor is connected to the floating diffusion node; The source of the sensing buffer transistor is connected to an output terminal of the buffer amplifier to generate the buffered output signal; and The drain of the sensing buffer transistor is connected to a buffer supply signal.

7. The pixel circuit as described in claim 6, wherein, Before the sensing buffer transistor senses the first state or the second state of the floating diffusion node, a low-level quasi-pulse is generated in the buffer supply signal to reset the buffered output signal.

8. The pixel circuit as described in claim 6, wherein, The buffer amplifier also includes a current source connected to the source of the sensing buffer transistor.

9. The pixel circuit as described in claim 6, wherein, The first read amplifier includes: A first read buffer transistor having a gate connected to the output of the first sample-and-hold stage; and A first read switch is connected to a source of the first read buffer transistor and an output terminal of the first read amplifier, wherein the gate of the first read switch is controlled by a first control signal; The second read amplifier includes: A second read buffer transistor having a gate connected to the output terminal of the second sample-and-hold stage; and A second read switch is connected to a source of the second read buffer transistor and an output of the second read amplifier, wherein the gate of the second read switch is controlled by a second control signal.

10. The pixel circuit as claimed in claim 9, wherein, The sensing buffer transistor and the first read buffer transistor have complementary conductivity types, and / or the sensing buffer transistor and the second read buffer transistor have complementary conductivity types, such that an offset level of the sensing buffer transistor cancels out an offset level of the first read buffer transistor, and / or an offset level of the sensing buffer transistor cancels out an offset level of the second read buffer transistor.

11. The pixel circuit as claimed in claim 3, wherein, An output terminal of the first read amplifier and an output terminal of the second read amplifier are short-circuited and connected to a pixel line.

12. The pixel circuit as claimed in claim 3, wherein, An output terminal of the first read amplifier is connected to a first pixel line, and an output terminal of the second read amplifier is connected to a second pixel line.

13. The pixel circuit as claimed in claim 1, wherein, The capacitance value of the floating diffusion node is adjusted by an adjustment signal, causing the pixel circuit to operate in at least one of the following modes: A low conversion gain mode, wherein the floating diffusion node has a first equivalent capacitance value; A high conversion gain mode, wherein the floating diffusion node has a second equivalent capacitance value, wherein the second equivalent capacitance value is smaller than the first equivalent capacitance value; and A high dynamic range mode in which the capacitance value of the floating diffusion node switches between the first equivalent capacitance value and the second equivalent capacitance value.

14. The pixel circuit as claimed in claim 13, wherein, Also includes: An adjustment switch, connected between the reset transistor and the floating diffusion node and controlled by the adjustment signal; and An adjustment capacitor is connected to a junction node where the reset transistor and the adjustment switch are connected to each other; When the adjustment switch is on, the floating diffusion node has the first equivalent capacitance value; when the adjustment switch is off, the floating diffusion node has the second equivalent capacitance value.

15. The pixel circuit as claimed in claim 14, wherein, When the pixel circuit operates in the low conversion gain mode, the adjustment switch is turned on; The first state corresponds to a reset state, in which the reset transistor is controlled by a pulse to completely drain the charge from the floating diffusion node. The second state corresponds to a sensing state, in which, after an exposure period, a pulse controls the transfer switching switch so that the charge in the photosensitive element is completely transferred to the floating diffusion node. One of the low-gain correction signals is generated based on the first output signal and the second output signal.

16. The pixel circuit as claimed in claim 14, wherein, When the pixel circuit operates in the high conversion gain mode, the adjustment switch is not turned on; The first state corresponds to a reset state, in which the reset transistor is controlled by a pulse to completely drain the charge from the floating diffusion node. The second state corresponds to a sensing state, in which, after an exposure period, a pulse controls the transfer switching switch so that the charge in the photosensitive element is completely transferred to the floating diffusion node. One of the high-gain correction signals is generated based on the first output signal and the second output signal.

17. The pixel circuit of claim 14, wherein, When the pixel circuit operates in this high dynamic range mode: In a high conversion gain sub-mode, the first state corresponds to a sensing state. When the pixel circuit operates in the sensing state of the high conversion gain sub-mode, the adjustment switch is not turned on. At this time, after an exposure period, the transfer switching switch is controlled by a pulse so that the charge in the photosensitive element is completely transferred to the floating diffusion node having the second equivalent capacitance value. In a low conversion gain sub-mode, the second state corresponds to a sensing state, wherein when the pixel circuit operates in the sensing state of the low conversion gain sub-mode, the adjustment switch is turned on, and the charge in the floating diffusion node is redistributed according to the first equivalent capacitance value. One of the high dynamic range signals is generated based on the first output signal and the second output signal.

18. The pixel circuit as claimed in claim 14, wherein, The amplifier circuit includes: A readout amplifier is configured to sense a first sample-and-hold signal having the first voltage or a second sample-and-hold signal having the second voltage, to generate a corresponding first output signal or a corresponding second output signal; and A selector circuit is used to select either the first sample-and-hold signal or the second sample-and-hold signal, and electrically connect it to an input terminal of the read amplifier, thereby generating the corresponding first output signal or the corresponding second output signal during the third time period.

19. The pixel circuit as claimed in claim 14, wherein, The buffer amplifier includes a sensing buffer transistor; The gate of the sensing buffer transistor is connected to the floating diffusion node; The source of the sensing buffer transistor is connected to an output terminal of the buffer amplifier to generate the buffered output signal; and The drain of the sensing buffer transistor is connected to a buffer supply signal.

20. The pixel circuit as claimed in claim 19, wherein, Before the sensing buffer transistor senses the first state or the second state of the floating diffusion node, a low-level quasi-pulse is generated in the buffer supply signal to reset the buffered output signal.

21. The pixel circuit as claimed in claim 19, wherein, The buffer amplifier also includes a current source connected to the source of the sensing buffer transistor.

22. The pixel circuit as claimed in claim 14, wherein, Also includes: A third sampling hold level; and A fourth sample-and-hold stage, wherein the third sample-and-hold stage and the fourth sample-and-hold stage are cascaded between the buffer amplifier and the amplifier circuit; The fourth sample-and-hold stage is used to sample or sample and hold the buffered output signal to generate a fourth sample-and-hold signal, and the third sample-and-hold stage is used to sample and hold the fourth sample-and-hold signal to generate a third sample-and-hold signal. The pixel circuit operates in the high dynamic range mode; During the first time period and the second time period, the adjustment switch is not turned on, so that the floating diffusion node has the second equivalent capacitance value; During a fifth time period of the global exposure cycle, the fourth sample-and-hold stage samples the buffered output signal having a third voltage to generate the fourth sample-and-hold signal having the third voltage, and the third sample-and-hold stage samples and holds the fourth sample-and-hold signal to generate the third sample-and-hold signal having the third voltage, wherein the third voltage is related to a third state of the floating diffusion node. During a sixth time period of the global exposure cycle, the fourth sample-and-hold stage samples and holds the buffered output signal having a fourth voltage to generate the fourth sample-and-hold signal having the fourth voltage, wherein the fourth voltage is related to a fourth state of the floating diffusion node. During the fifth and sixth time periods, the adjustment switch is turned on, so that the floating diffusion node has the first equivalent capacitance value. The first state, the second state, the third state, and the fourth state each correspond to a reset state of a low conversion gain submode, a sensing state of a high conversion gain submode, the reset state of the high conversion gain submode, and the sensing state of the low conversion gain submode. During a seventh time period of the global exposure cycle, the first sample-and-hold signal with the first voltage, the second sample-and-hold signal with the second voltage, the third sample-and-hold signal with the third voltage, and the fourth sample-and-hold signal with the fourth voltage are independently sensed by the amplifier circuit, thereby generating a corresponding first output signal, a corresponding second output signal, a corresponding third output signal, and a corresponding fourth output signal, respectively. One of the high dynamic range offset compensation signals is generated based on the first output signal, the second output signal, the third output signal, and the fourth output signal.

23. The pixel circuit as claimed in claim 22, wherein, The pixel circuit operates according to the following timing sequence: In order, they are the first time period, the fifth time period, the second time period, the sixth time period, the third time period, and the seventh time period.

24. The pixel circuit as claimed in claim 1, wherein, Each of the first sample-and-hold stage and the second sample-and-hold stage includes: A holding capacitor is connected to the corresponding output terminal of the sample-and-hold stage; and A sampling switch is connected between an input terminal and the output terminal of the corresponding sample-and-hold stage.

25. The pixel circuit as claimed in claim 22, wherein, Each of the first sampling hold stage, the second sampling hold stage, the third sampling hold stage, and the fourth sampling hold stage includes: A holding capacitor is connected to the corresponding output terminal of the sample-and-hold stage; and A sampling switch is connected between an input terminal and the output terminal of the corresponding sample-and-hold stage.

26. A method for operating a one-pixel circuit, characterized in that, The pixel circuit includes: A photosensitive element used to generate an electric charge based on incident light; A floating diffusion node; A reset transistor is used to discharge the charge from the floating diffusion node; A transfer switching switch is coupled between the photosensitive element and the floating diffusion node to control the transfer of charge from the photosensitive element to the floating diffusion node; A buffer amplifier having an input terminal coupled to the floating diffusion node, the buffer amplifier being used to generate a buffered output signal based on a voltage at the floating diffusion node; An amplifier circuit; First sampling hold level; and A second sample-and-hold stage, wherein the first sample-and-hold stage and the second sample-and-hold stage are cascaded between the buffer amplifier and the amplifier circuit; The second sample-and-hold stage is used to sample or sample and hold the buffered output signal to generate a second sample-and-hold signal, and the first sample-and-hold stage is used to sample and hold the second sample-and-hold signal to generate a first sample-and-hold signal. The amplifier circuit is independently electrically connected to an output terminal of the first sample-and-hold stage and an output terminal of the second sample-and-hold stage; The method includes: S10: During a first time period of a global exposure cycle, the buffered output signal having a first voltage is stored in the first sample-and-hold stage through the second sample-and-hold stage, wherein the first voltage is related to a first state of the floating diffusion node; S20: During a second time period of the global exposure cycle, the buffered output signal having a second voltage is stored in the second sample-and-hold stage, wherein the second voltage is related to a second state of the floating diffusion node; S30: During a third time period of the global exposure cycle, the first voltage and the second voltage are independently sensed by the amplifier circuit, thereby generating a corresponding first output signal and a corresponding second output signal.

27. The method of claim 26, wherein, The amplifier circuit includes: A first readout amplifier having an input terminal for sensing the first sample-and-hold signal; and A second readout amplifier having an input terminal for sensing the second sample-and-hold signal; The method also includes: S35: During an equalization period, the first sample-and-hold stage and the second sample-and-hold stage are equalized to each other so as to store an equalized voltage in the first sample-and-hold stage and the second sample-and-hold stage; S40: During a fourth time period of the global exposure cycle, the first readout amplifier senses the equalization voltage in the first sample-and-hold stage to generate a first offset signal, and the second readout amplifier senses the equalization voltage in the second sample-and-hold stage to generate a second offset signal.

28. The method of claim 27, wherein, Also includes: S100: Generate an offset compensation signal based on the first output signal, the second output signal, the first offset signal, and the second offset signal.

29. The method of claim 26, wherein, Also includes: S05: Before step S10, in this first state, the reset transistor is controlled by a pulse to completely drain the charge from the floating diffusion node; and S15: Before step S20, during a transition period in the second state, the transfer switching switch is controlled by a pulse to completely transfer the charge in the photosensitive element to the floating diffusion node.

30. The method of claim 26, wherein, Also includes: Adjust the capacitance value of the floating diffusion node so that the pixel circuit selectively operates in at least one of the following modes: A low conversion gain mode, wherein the floating diffusion node has a first equivalent capacitance value, and wherein a low gain correction signal is generated based on the first output signal and the second output signal; A high conversion gain mode, wherein the floating diffusion node has a second equivalent capacitance value, wherein the second equivalent capacitance value is smaller than the first equivalent capacitance value, wherein a high gain correction signal is generated based on the first output signal and the second output signal; and A high dynamic range mode, wherein the capacitance value of the floating diffusion node switches between a first equivalent capacitance value and a second equivalent capacitance value, wherein a high dynamic range signal is generated based on the first output signal and the second output signal.

31. The method of claim 30, wherein, In this high dynamic range mode, the steps for operating the pixel circuit include: In the first state, the capacitance value of the floating diffusion node is adjusted to the second equivalent capacitance value, and the transfer switching switch is controlled by a pulse to completely transfer the charge in the photosensitive element to the floating diffusion node within a transfer period. In this second state, the capacitance value of the floating diffusion node is adjusted to the first equivalent capacitance value; and A high dynamic range signal is generated based on the first output signal and the second output signal.

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