Voltage generation circuit, semiconductor device including the same, and voltage offset calibration system

Abstract

The present application relates to a voltage generation circuit, a semiconductor device including the same, and a voltage offset calibration system. A voltage generation circuit includes: a plurality of rectifier circuits that are selectively activated according to a plurality of first control signals and generate internal voltages based on respective reference voltages that can be independently adjusted according to a plurality of second control signals; a detection circuit that generates a detection signal by comparing a pre-detection signal generated in each of the plurality of rectifier circuits with a reference signal; and a storage circuit that stores a pre-selected signal provided from an external system and outputs the stored signal to each of the plurality of rectifier circuits as a plurality of second control signals.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor circuits, and particularly to a voltage generating circuit, a semiconductor device including the same, and a voltage offset calibration system. Background Art

[0002] The semiconductor device includes a plurality of rectifying circuits for generating an internal voltage for use within the semiconductor device by trimming a voltage level of a power source supplied from outside the semiconductor device (ie, an external power source).

[0003] The internal voltage can be used in memory cores, peripheral circuits, input / output circuits for signal processing, etc.

[0004] A plurality of rectification circuits may be provided in a distributed manner in consideration of the locations of loads (ie, a memory core, peripheral circuits, input / output circuits for signal processing, etc.) that use the corresponding internal voltages.

[0005] In the event of an offset (i.e., voltage level offset) between rectifier circuits generating the same internal voltage, some rectifier circuits may not operate in a typical manner and therefore may not be able to maintain the internal voltage level at a target level, which may degrade the operational performance of the entire system. Summary of the Invention

[0006] Various embodiments relate to a voltage generating circuit capable of detecting and compensating for a voltage offset of a rectifier circuit, a semiconductor device including the same, and a voltage offset calibration system.

[0007] In an embodiment, a voltage generating circuit may include: a plurality of rectifier circuits that are selectively activated according to a plurality of first control signals and generate internal voltages according to corresponding reference voltages that can be independently adjusted according to a plurality of second control signals; a detection circuit that generates a detection signal by comparing a pre-detection signal generated in each of the plurality of rectifier circuits with a reference signal; and a storage circuit that stores a pre-selected signal provided from an external system and outputs the stored signal to each of the plurality of rectifier circuits as a plurality of second control signals.

[0008] In an embodiment, a semiconductor device may include: a plurality of rectifier circuits that are selectively activated according to a plurality of first control signals and generate internal voltages according to corresponding reference voltages that can be independently adjusted according to a plurality of second control signals; a detection circuit that generates a detection signal by comparing a pre-detection signal generated in each of the plurality of rectifier circuits with a reference signal; and a state machine that selectively activates the plurality of first control signals and adjusts values of the plurality of second control signals, and stores the values of the plurality of second control signals when output offset calibration of the plurality of rectifier circuits is completed by monitoring the resulting detection signals.

[0009] In an embodiment, a voltage offset calibration system may include: a semiconductor device that outputs a detection signal generated by operating a plurality of rectifier circuits configured within the semiconductor device to the outside of the semiconductor device in accordance with a control signal; and an external system that generates a control signal and calibrates an offset of an output voltage of each of the plurality of rectifier circuits by monitoring the detection signal according to adjusting a reference voltage of each of the plurality of rectifier circuits by using the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a diagram illustrating a representation of a configuration example of a voltage offset calibration system according to an embodiment of the present disclosure.

[0011] Figure 2 This is an example Figure 1 The diagram shows an example of the configuration of a voltage generating circuit.

[0012] Figure 3 This is an example Figure 2 FIG. 1 is a diagram showing a configuration example of a first rectifier circuit.

[0013] Figure 4 This is an example Figure 2 A diagram showing an example configuration of a detection circuit is shown.

[0014] Figure 5 This is an example Figure 2 The diagram shows an example of the configuration of a reference voltage generating circuit.

[0015] Figure 6 This is an example Figure 2 A diagram showing an example configuration of a switching circuit is shown.

[0016] Figure 7 is a diagram illustrating a representation of a configuration example of a voltage offset calibration system according to another embodiment of the present disclosure.

[0017] Figure 8 This is an example Figure 7 The diagram shows an example of the configuration of a voltage generating circuit. DETAILED DESCRIPTION

[0018] Hereinafter, a voltage generation circuit, a semiconductor device including the same, and a voltage offset calibration system will be described below with reference to the accompanying drawings through various examples of embodiments.

[0019] Figure 1 is a diagram illustrating a representation of a configuration example of a voltage offset calibration system 1 according to an embodiment of the present disclosure.

[0020] Reference Figure 1 , a voltage offset calibration system 1 according to an embodiment of the present disclosure may include a semiconductor device 10 and an external system 20 .

[0021] The semiconductor device 10 may provide the external system 20 with a detection signal VGCMP generated by operating a rectifier circuit configured within the semiconductor device 10 in accordance with a control signal provided from the external system 20 .

[0022] The semiconductor device 10 may include a memory region 11 , an input / output circuit region 12 , and a voltage generating circuit 100 .

[0023] The voltage generating circuit 100 may be provided in the functional circuit region 13 .

[0024] The functional circuit region 13 may include circuits for performing various functions related to the operation of the semiconductor device 10 .

[0025] The voltage generation circuit 100 can generate internal voltages for use in the functional circuit region 13 , the memory region 11 , and the input / output circuit region 12 by adjusting the voltage level of the external power supply.

[0026] The voltage generating circuit 100 may include a rectifying circuit for generating an internal voltage, and the rectifying circuit may be provided in the functional circuit region 13 in a distributed manner.

[0027] The voltage generating circuit 100 may generate the detection signal VGCMP by operating a rectifier circuit configured in the voltage generating circuit 100 according to a control signal provided from the external system 20 .

[0028] The input / output circuit region 12 may perform data transmission / reception operations with respect to the memory region 11 and the external system 20 .

[0029] The input / output circuit region 12 may include a plurality of pads, for example, a data pad, a command / address pad, a power pad, and an additional pad.

[0030] The input / output circuit region 12 may provide a detection signal VGCMP to the external system 20 through at least one of the plurality of pads.

[0031] Some of the plurality of pads may be any one or more of a data pad, a command / address pad, a power pad, and an additional pad.

[0032] The external system 20 may include, for example, test equipment or a memory controller.

[0033] The external system 20 may perform a voltage forcing operation, ie, an operation of applying a voltage to the semiconductor device 10 so that a level of an output terminal of a rectifier circuit of the semiconductor device 10 is the same as a target level of an internal voltage.

[0034] The external system 20 may calibrate the offset of the output voltage of each rectifier circuit of the semiconductor device 10 by adjusting the reference voltage of each rectifier circuit and monitoring the resulting detection signal VGCMP provided from the semiconductor device 10 .

[0035] The external system 20 may generate a control signal for controlling the semiconductor device 10 so as to generate the detection signal VGCMP.

[0036] Figure 2 This is an example Figure 1 FIG. 1 is a diagram showing an example configuration of the voltage generating circuit 100 .

[0037] Reference Figure 2 The voltage generating circuit 100 may include a plurality of rectifier circuits (eg, a first rectifier circuit 110 to a fourth rectifier circuit 140 ), a detection circuit 150 , a reference voltage generating circuit 160 , a storage circuit 170 , and a switch circuit 180 .

[0038] The first to fourth rectifier circuits 110 to 140 may be configured to generate an internal voltage VCCI.

[0039] Output lines of the first to fourth rectifier circuits 110 to 140 may be commonly coupled, and a plurality of loads LD may be coupled to the commonly coupled output lines.

[0040] Multiple loads LD may be included in the above reference Figure 1 The functional circuit area 13 is described.

[0041] The plurality of loads LD may be provided in a distributed manner over the entire area of the functional circuit region 13 .

[0042] Taking into account the positions and distances of the plurality of loads LD, the first to fourth rectifier circuits 110 to 140 may be disposed in a distributed manner in the functional circuit region 13 .

[0043] The first to fourth rectifier circuits 110 to 140 may be activated according to a plurality of first control signals VGEN<1:4> and an internal voltage enable signal VCCIEN.

[0044] The plurality of first control signals VGEN<1:4> may be selectively activated in a test mode for an offset calibration operation of the semiconductor device 10 .

[0045] The internal voltage enable signal VCCIEN may be activated in typical operation of the semiconductor device 10 and may be deactivated in a state where operation of the first to fourth rectifier circuits 110 to 140 is not required (eg, in a power-down mode).

[0046] The first to fourth rectifier circuits 110 to 140 can independently adjust corresponding reference voltages according to a plurality of second control signals VSEL<1:4><0:1>.

[0047] The first to fourth rectifier circuits 110 to 140 may each select one of the plurality of pre-reference voltages VREF<0:2> according to the plurality of second control signals VSEL<1:4><0:1>, and may use the selected pre-reference voltage as a reference voltage.

[0048] The first to fourth rectifier circuits 110 to 140 may be collectively activated or deactivated according to the internal voltage enable signal VCCIEN.

[0049] The first to fourth rectifier circuits 110 to 140 may be selectively activated or deactivated according to a plurality of first control signals VGEN<1:4>, respectively.

[0050] The first control signal VGEN<1:4> may be used according to any one of the plurality of first control signals VGEN<1:4> (eg, the first control signal VGEN <1> ) to activate the first rectifier circuit 110.

[0051] The first rectifier circuit 110 can be configured to output a current according to any one of a plurality of second control signals VSEL<1:4><0:1> (eg, the second control signal VSEL <1> <0:1>) to select one of a plurality of pre-reference voltages VREF<0:2>, and the selected pre-reference voltage may be used as a reference voltage.

[0052] The control signal VGEN<1:4> may be controlled according to another one of the plurality of first control signals VGEN<1:4> (eg, the first control signal VGEN<1:4>). <2> ) to activate the second rectifier circuit 120.

[0053] The second rectifier circuit 120 may be configured to output a current according to another one of the plurality of second control signals VSEL<1:4><0:1> (eg, the second control signal VSEL <2> <0:1>) to select one of a plurality of pre-reference voltages VREF<0:2>, and the selected pre-reference voltage may be used as a reference voltage.

[0054] The control signal VGEN<1:4> may be controlled according to another one of the plurality of first control signals VGEN<1:4> (eg, the first control signal VGEN<1:4>). <3> ) to activate the third rectifier circuit 130.

[0055] The third rectifier circuit 130 may be configured to output a current according to another one of the plurality of second control signals VSEL<1:4><0:1> (eg, the second control signal VSEL <3> <0:1>) to select one of a plurality of pre-reference voltages VREF<0:2>, and the selected pre-reference voltage may be used as a reference voltage.

[0056] The control signal VGEN<1:4> may be controlled according to another one of the plurality of first control signals VGEN<1:4> (eg, the first control signal VGEN<1:4>). <4> ) to activate the fourth rectifier circuit 140.

[0057] The fourth rectifier circuit 140 may be configured to output a current according to another one of the plurality of second control signals VSEL<1:4><0:1> (eg, the second control signal VSEL <4> <0:1>) to select one of a plurality of pre-reference voltages VREF<0:2>, and the selected pre-reference voltage may be used as a reference voltage.

[0058] The first to fourth rectifier circuits 110 to 140 may have the same circuit configuration.

[0059] The detection circuit 150 may generate the detection signal VGCMP according to the pre-detection signal VGOUT generated in each of the first to fourth rectifier circuits 110 to 140 .

[0060] The detection circuit 150 may generate the detection signal VGCMP by comparing the pre-detection signal VGOUT with a reference signal, that is, by comparing the current of the pre-detection signal VGOUT with a reference current.

[0061] The reference voltage generating circuit 160 may generate a plurality of pre-reference voltages VREF<0:2> having different voltages.

[0062] The storage circuit 170 may store the pre-selection signal VSELEXT<1:4><0:1> provided from the outside of the semiconductor device 10 and may output the stored signal as the plurality of second control signals VSEL<1:4><0:1>.

[0063] The switch circuit 180 may couple the first node NA and the pad 12 - 1 according to a plurality of first control signals VGEN<1:4>.

[0064] Output lines of the first to fourth rectifier circuits 110 to 140 may be commonly coupled to a first node NA.

[0065] The pad 12-1 may be Figure 1 Any one of the plurality of pads of the input / output circuit region 12 shown.

[0066] The external system 20 may perform a voltage forcing operation, ie, an operation of applying a voltage to the pad 12 - 1 so that levels of the output terminals of the first to fourth rectifier circuits 110 to 140 are the same as a target level of the internal voltage VCCI.

[0067] Figure 3 This is an example Figure 2 FIG. 1 is a diagram showing a configuration example of the first rectifier circuit 110 .

[0068] Reference Figure 3 The first rectifier circuit 110 may include a differential amplifier 111 , a driver 112 , a voltage-dividing resistor 113 , a multiplexer (MUX) 114 , a switch 115 , and a logic gate 116 .

[0069] The differential amplifier 111 may output a result of comparing the reference voltage VREF and the feedback voltage VFB1 .

[0070] The differential amplifier 111 may output a result of comparing the reference voltage VREF and the feedback voltage VFB1 by being activated according to the third control signal AMPEN.

[0071] When the third control signal AMPEN is at a high level, the differential amplifier 111 may be activated.

[0072] The driver 112 may generate the internal voltage VCCI by driving the external voltage VCCE according to the output of the differential amplifier 111 .

[0073] The voltage-dividing resistor 113 may output a feedback voltage VFB1 by dividing the internal voltage VCCI.

[0074] The multiplexer 114 can be switched according to the second control signal VSEL. <1> <0:1> selects one of a plurality of pre-reference voltages VREF<0:2> to output the reference voltage VREF.

[0075] The switch 115 can be controlled according to the first control signal VGEN. <1> The output of the differential amplifier 111 is output to the outside of the first rectifier circuit 110 as a preliminary detection signal VGOUT.

[0076] The logic gate 116 can convert the first control signal VGEN <1> The result of an “OR” operation performed on the internal voltage enable signal VCCIEN is output as the third control signal AMPEN.

[0077] Figure 4 This is an example Figure 2 FIG. 1 is a diagram showing an example configuration of the detection circuit 150 .

[0078] Reference Figure 4 , the detection circuit 150 may include a driver 151 , a reference current source 152 and a comparator 153 .

[0079] The driver 151 may drive a current corresponding to the external voltage VCCE according to the pre-detection signal VGOUT.

[0080] The driver 151 may include a PMOS transistor having a source terminal to which the external voltage VCCE is applied, a gate to which the pre-detection signal VGOUT is input, and a drain terminal coupled to the comparator 153 .

[0081] The comparator 153 may generate the detection signal VGCMP by comparing the current IREF according to the reference current source 152 and the current driven by the driver 151 .

[0082] In a case where, for example, the current driven by the driver 151 is greater than the current IREF according to the reference current source 152 , the comparator 153 may output the detection signal VGCMP at a high level.

[0083] In a case where, for example, the current driven by the driver 151 is less than the current IREF according to the reference current source 152 , the comparator 153 may output the detection signal VGCMP at a low level.

[0084] Figure 5 This is an example Figure 2 FIG. 1 is a diagram showing an example of a configuration of the reference voltage generating circuit 160 .

[0085] Reference Figure 5 , the reference voltage generating circuit 160 may include a bandgap reference circuit 161 , a differential amplifier 162 , a driver 163 , a voltage dividing resistor 164 , and a plurality of multiplexers (MUX) 165 to 167 .

[0086] The bandgap reference circuit 161 may generate a bandgap voltage BGOUT having a constant level regardless of temperature variation by using a bipolar junction transistor.

[0087] The differential amplifier 162 may output a result of comparing the band gap voltage BGOUT and the feedback voltage VFB2 .

[0088] The driver 163 may drive a current corresponding to the external voltage VCCE according to the output of the differential amplifier 162 .

[0089] The driver 163 may include a PMOS transistor having a source terminal to which the external voltage VCCE is applied, a gate to which the output of the differential amplifier 162 is input, and a drain terminal coupled to the voltage dividing resistor 164 .

[0090] The voltage-dividing resistor 164 may generate a plurality of node voltages R<0:63> by dividing a voltage according to a current driven by the driver 163 .

[0091] The voltage-dividing resistor 164 may include a plurality of resistors coupled in series between the drain terminal of the driver 163 and a ground terminal.

[0092] A voltage of a node having a voltage division ratio of, for example, 1 / 2 among nodes coupled to the plurality of resistors may be output as the feedback voltage VFB2 , and a plurality of node voltages R<0:63> may be output from the remaining nodes.

[0093] The plurality of multiplexers 165 to 167 may generate a plurality of pre-reference voltages VREF<0:2> by using a ground voltage, a plurality of node voltages R<0:63>, and an external voltage VCCE according to the trimming signal TRIM<0:63>.

[0094] The number of the multiplexers 165 to 167 may vary depending on the number of required pre-reference voltages.

[0095] The embodiment of the present disclosure illustrates an example in which the first to third multiplexers 165 to 167 are configured to generate a plurality of pre-reference voltages VREF<0:2>.

[0096] The first multiplexer 165 may generate the pre-reference voltage VREF0 by selecting one of the ground voltage and the plurality of node voltages R<0:62> according to the trimming signal TRIM<0:63>.

[0097] The second multiplexer 166 may generate the pre-reference voltage VREF1 by selecting one of a plurality of node voltages R<0:63> according to the trimming signal TRIM<0:63>.

[0098] The third multiplexer 167 may generate the pre-reference voltage VREF2 by selecting one of the plurality of node voltages R<1:63> and the external voltage VCCE according to the trimming signal TRIM<0:63>.

[0099] Figure 6 This is an example Figure 2FIG. 1 is a diagram showing an example configuration of the switching circuit 180 .

[0100] Reference Figure 6 , the switching circuit 180 may include a switch 181 and a logic gate 182 .

[0101] The switch 181 may be coupled between the first node NA and the pad 12 - 1 .

[0102] When any one of the plurality of first control signals VGEN<1:4> is at a first logic level (eg, a high level), the logic gate 182 may turn on the switch 181 .

[0103] When all of the plurality of first control signals VGEN<1:4> are at the second logic level (ie, a low level), the logic gate 182 may turn off the switch 181 .

[0104] That is, in the embodiment of the present disclosure, the first node NA and the pad 12-1 may be coupled by using the switch circuit 180 only during a test period in which output offset calibration of the first to fourth rectifier circuits 110 to 140 is performed, so that voltage forcing of the external system 20 can be performed. In the embodiment of the present disclosure, the first node NA and the pad 12-1 may be electrically decoupled by using the switch circuit 180 during typical operation, so that the outputs of the first to fourth rectifier circuits 110 to 140 are not affected by elements external to the semiconductor device 10.

[0105] An offset calibration operation of the voltage offset calibration system 1 according to the above-described embodiment of the present disclosure will be described.

[0106] Reference Figure 2 , the external system 20 may sequentially perform the offset calibration operation on the first to fourth rectifier circuits 110 to 140 regardless of the order of the first to fourth rectifier circuits 110 to 140 .

[0107] In the embodiment of the present disclosure, an example in which the offset calibration operation is performed in the order of the first rectifier circuit 110 , the second rectifier circuit 120 , the third rectifier circuit 130 , and the fourth rectifier circuit 140 will be described.

[0108] The external system 20 may activate only the first control signal VGEN among the plurality of first control signals VGEN<1:4> by using a test mode. <1> Hereinafter, activation of a signal may mean that the corresponding signal is at a high level.

[0109] Since the first control signal VGEN <1> is at a high level, so the switch circuit 180 can connect the first node NA and the pad 12 - 1 .

[0110] The external system 20 may make the level of the output terminal of the first rectifier circuit 110 the same as the target level of the internal voltage VCCI by performing voltage forcing via the pad 12 - 1 .

[0111] During the offset calibration process, the levels of the output terminals of the first to fourth rectifier circuits 110 to 140 are not generated within the semiconductor device 10, but are determined by voltage forcing (i.e., forced voltage application) from outside the semiconductor device 10. Therefore, regardless of the operation of the semiconductor device 10, the levels of the output terminals of the first to fourth rectifier circuits 110 to 140 can be stably maintained to be the same as the target level of the internal voltage VCCI.

[0112] Reference Figure 3 , since the first control signal VGEN <1> is at a high level, the third control signal AMPEN can be generated to be at a high level.

[0113] Since the first control signal VGEN <1> When the third control signal AMPEN is at a high level, the differential amplifier 111 and the switch 115 of the first rectifier circuit 110 among the first to fourth rectifier circuits 110 to 140 can be activated, thereby providing the pre-detection signal VGOUT to the detection circuit 150 .

[0114] The detection circuit 150 may output a detection signal VGCMP at a high level or a low level according to the pre-detection signal VGOUT.

[0115] Reference Figure 1 , the detection signal VGCMP can be provided to the external system 20 through the input / output circuit region 12.

[0116] The detection signal VGCMP may be provided to the external system 20 through any one pad or a plurality of pads among the data pad, the command / address pad, and the additional pad of the input / output circuit region 12 .

[0117] Even under the condition that the levels of the output terminals of the first to fourth rectifier circuits 110 to 140 are kept constant by voltage forcing and the reference voltage VREF is the same, the detection signal VGCMP of each of the first to fourth rectifier circuits 110 to 140 may have different logic levels due to offset.

[0118] During typical operation, the rectifier circuit without offset should control the driving of the driver 112 by outputting the pre-detection signal VGOUT at a low level before the level of the internal voltage VCCI rises to the target level and by outputting the pre-detection signal VGOUT at a high level when the level of the internal voltage VCCI rises to be equal to or higher than the target level.

[0119] However, the rectification circuit generating the internal voltage VCCI higher than the target level outputs the pre-detection signal VGOUT at a low level even when the level of the internal voltage VCCI rises to be equal to or higher than the target level.

[0120] The rectifier circuit generating the internal voltage VCCI lower than the target level outputs the pre-detection signal VGOUT at a high level before the level of the internal voltage VCCI reaches the target level.

[0121] A rectifier circuit (eg, the first rectifier circuit 110 ) that generates an output (ie, the internal voltage VCCI) higher than a target level in typical operation should lower the level of the internal voltage VCCI generated thereby by lowering the level of the reference voltage VREF.

[0122] On the other hand, a rectifier circuit (eg, the second rectifier circuit 120 ) generating an output (ie, internal voltage VCCI) lower than a target level in typical operation should increase the level of the internal voltage VCCI generated thereby by increasing the level of the reference voltage VREF.

[0123] The external system 20 may adjust the pre-selection signal VSELEXT corresponding to the first rectifier circuit 110 among the pre-selection signals VSELEXT<1:4><0:1> by using the test mode. <1> The value of <0:1>.

[0124] With the preselection signal VSELEXT <1> The value of <0:1> is adjusted, and the second control signal VSEL corresponding to the first rectifier circuit 110 among the plurality of second control signals VSEL<1:4><0:1> can be adjusted. <1> The value of <0:1> can thus adjust the level of the reference voltage VREF of the first rectifier circuit 110.

[0125] The external system 20 may monitor the transition of the logic level of the detection signal VGCMP while adjusting the level of the reference voltage VREF of the first rectifier circuit 110 in the above-described manner.

[0126] When the logic level of the detection signal VGCMP transitions from a high level to a low level or from a low level to a high level, the external system 20 may determine the corresponding time as the time when the offset calibration of the output level of the first rectifier circuit 110 is completed.

[0127] If the logic level transition of the detection signal VGCMP occurs, the second control signal VSEL may be stopped. <1> The output offset calibration for the first rectifier circuit 110 is completed by adjusting <0:1> and storing the corresponding signal value.

[0128] Subsequently, the external system 20 may activate only the first control signal VGEN among the plurality of first control signals VGEN<1:4> by using the test mode. <2> .

[0129] Since the first control signal VGEN <2> is at a high level, so the switch circuit 180 can connect the first node NA and the pad 12 - 1 .

[0130] The external system 20 may make the level of the output terminal of the second rectifier circuit 120 the same as the target level of the internal voltage VCCI by performing voltage forcing through the pad 12 - 1 .

[0131] Reference Figure 3 , since the first control signal VGEN <2> is a high level, the third control signal AMPEN may be generated to be at a high level.

[0132] Since the first control signal VGEN <2> and the third control signal AMPEN are at a high level, the pre-detection signal VGOUT outputted from the second rectifier circuit 120 among the first to fourth rectifier circuits 110 to 140 may be provided to the detection circuit 150 .

[0133] The detection circuit 150 may output a detection signal VGCMP at a high level or a low level according to the pre-detection signal VGOUT.

[0134] Reference Figure 1 , the detection signal VGCMP can be provided to the external system 20 through the input / output circuit region 12.

[0135] The detection signal VGCMP may be provided to the external system 20 through any one pad or a plurality of pads among the data pad, the command / address pad, and the additional pad of the input / output circuit region 12 .

[0136] The external system 20 may adjust the pre-selection signal VSELEXT corresponding to the second rectifier circuit 120 among the pre-selection signals VSELEXT<1:4><0:1> by using the test mode. <2> The value of <0:1>.

[0137] With the preselection signal VSELEXT <2> The value of <0:1> is adjusted, and the second control signal VSEL corresponding to the second rectifier circuit 120 among the plurality of second control signals VSEL<1:4><0:1> can be adjusted. <2> <0:1>, the level of the reference voltage VREF of the second rectifier circuit 120 can be adjusted.

[0138] The external system 20 may monitor the transition of the logic level of the detection signal VGCMP while adjusting the level of the reference voltage VREF of the second rectifier circuit 120 .

[0139] The external system 20 may determine the time when the logic level of the detection signal VGCMP transitions from a high level to a low level or from a low level to a high level as the time when the offset calibration of the output level of the second rectifier circuit 120 is completed.

[0140] If the logic level transition of the detection signal VGCMP occurs, the second control signal VSEL is stopped. <2> The output offset calibration of the second rectifier circuit 120 is completed by adjusting <0:1> and storing the corresponding signal value.

[0141] The output offset calibration for the third and fourth rectifier circuits 130 and 140 may be performed in the same method as the output offset calibration method described above for the first and second rectifier circuits 110 and 120 .

[0142] If the output offset calibration for the first to fourth rectifier circuits 110 to 140 is completed, a plurality of second control signals VSEL<1:4><0:1> for providing a reference voltage VREF capable of calibrating the output level offset of each of the first to fourth rectifier circuits 110 to 140 may be stored in Figure 2 in the storage circuit 170 .

[0143] After completing the output offset calibration for the first to fourth rectifier circuits 110 to 140, in typical operation, all values of the plurality of first control signals VGEN<1:4> may become low levels, so that the first node NA and the pad 12-1 may be electrically disconnected, so that the output of the pre-detection signal VGOUT may be blocked.

[0144] In typical operation, when the internal voltage enable signal VCCIEN goes high, the first to fourth rectifier circuits 110 to 140 may generate the internal voltage VCCI at a target level according to the plurality of second control signals VSEL<1:4><0:1> stored in the storage circuit 170 .

[0145] Figure 7 is a diagram illustrating a representation of a configuration example of a voltage offset calibration system 2 according to another embodiment of the present disclosure.

[0146] Reference Figure 7 A voltage offset calibration system 2 according to another embodiment of the present disclosure may include a semiconductor device 30 and an external system 40 .

[0147] The semiconductor device 30 can calibrate the deviation of the output voltage of each rectifier circuit included therein by adjusting the reference voltage of each rectifier circuit according to a control signal generated therein and monitoring the resulting detection signal.

[0148] The semiconductor device 30 may include a memory region 31 , an input / output circuit region 32 , and a voltage generating circuit 200 .

[0149] The voltage generating circuit 200 can calibrate the offset of the output voltage of each rectifier circuit by adjusting the reference voltage of each rectifier circuit according to the control signal and monitoring the resulting detection signal.

[0150] The voltage generating circuit 200 may be provided in the functional circuit region 33 .

[0151] The functional circuit region 33 may include circuits for performing various functions related to the operation of the semiconductor device 30 .

[0152] The voltage generation circuit 200 may generate internal voltages for use in the functional circuit region 33 , the memory region 31 , and the input / output circuit region 32 by adjusting the voltage level of the external power supply.

[0153] The voltage generating circuit 200 may include a rectifier circuit, and the rectifier circuit may be provided in the functional circuit region 33 in a distributed manner.

[0154] The input / output circuit region 32 may perform data transmission / reception operations with respect to the memory region 31 and the external system 40 .

[0155] The input / output circuit region 32 may include a plurality of pads, for example, a data pad, a command / address pad, a power pad, and an additional pad.

[0156] The external system 40 may perform a voltage forcing operation, ie, an operation of applying a voltage to the semiconductor device 30 so that the level of the output terminal of the rectifier circuit of the semiconductor device 30 is the same as a target level of the internal voltage.

[0157] External system 40 may include, for example, a power supply device capable of performing voltage forcing, test equipment, or a memory controller.

[0158] Figure 8 This is an example Figure 7 FIG. 2 is a diagram showing an example configuration of the voltage generating circuit 200 .

[0159] Reference Figure 8 The voltage generating circuit 200 may include a plurality of rectifier circuits (eg, a first rectifier circuit 210 to a fourth rectifier circuit 240 ), a detection circuit 250 , a reference voltage generating circuit 260 , a state machine 270 , and a switch circuit 280 .

[0160] The first to fourth rectifier circuits 210 to 240 may be configured to generate an internal voltage VCCI.

[0161] Output lines of the first to fourth rectifying circuits 210 to 240 may be commonly coupled, and a plurality of loads LD may be coupled to the commonly coupled output lines.

[0162] Multiple load LDs can be included in Figure 7 in the functional circuit area 33.

[0163] A plurality of loads LD may be provided in a distributed manner over the entire area of the functional circuit region 33 .

[0164] Taking into account the positions and distances of the plurality of loads LD, the first to fourth rectifier circuits 210 to 240 may be disposed in a distributed manner in the functional circuit region 33 .

[0165] The first to fourth rectifier circuits 210 to 240 may be activated according to a plurality of first control signals VGEN<1:4> and an internal voltage enable signal VCCIEN.

[0166] The plurality of first control signals VGEN<1:4> may be internally generated in a test mode for an offset calibration operation of the semiconductor device 30 .

[0167] The internal voltage enable signal VCCIEN may be activated in typical operation of the semiconductor device 30 and may be deactivated in a state where operation of the first to fourth rectifier circuits 210 to 240 is not required (eg, in a power-off mode).

[0168] The first to fourth rectifier circuits 210 to 240 can independently adjust corresponding reference voltages according to a plurality of second control signals VSEL<1:4><0:1>.

[0169] The first to fourth rectifier circuits 210 to 240 may each select one of the plurality of pre-reference voltages VREF<0:2> according to the plurality of second control signals VSEL<1:4><0:1>, and may use the selected pre-reference voltage as a reference voltage.

[0170] The first to fourth rectifier circuits 210 to 240 may be commonly activated or deactivated according to the internal voltage enable signal VCCIEN.

[0171] The first to fourth rectifier circuits 210 to 240 may be selectively activated or deactivated according to a plurality of first control signals VGEN<1:4>, respectively.

[0172] The first control signal VGEN<1:4> may be used according to any one of the plurality of first control signals VGEN<1:4> (eg, the first control signal VGEN <1> ) to activate the first rectifier circuit 210.

[0173] The first rectifier circuit 210 can be configured to output a current according to any one of a plurality of second control signals VSEL<1:4><0:1> (eg, the second control signal VSEL <1> <0:1>) to select one of a plurality of pre-reference voltages VREF<0:2>, and the selected pre-reference voltage may be used as a reference voltage.

[0174] The first rectifier circuit 210 may have Figure 3 The circuit configuration shown is the same circuit configuration.

[0175] The control signal VGEN<1:4> may be controlled according to another one of the plurality of first control signals VGEN<1:4> (eg, the first control signal VGEN<1:4>). <2> ) to activate the second rectifier circuit 220.

[0176] The second rectifier circuit 220 may be configured to output a current according to another one of the plurality of second control signals VSEL<1:4><0:1> (eg, the second control signal VSEL <2> <0:1>) to select one of a plurality of pre-reference voltages VREF<0:2>, and the selected pre-reference voltage may be used as a reference voltage.

[0177] The control signal VGEN<1:4> may be controlled according to another one of the plurality of first control signals VGEN<1:4> (eg, the first control signal VGEN<1:4>). <3> ) to activate the third rectifier circuit 230.

[0178] The third rectifier circuit 230 may be configured to output a current according to another one of the plurality of second control signals VSEL<1:4><0:1> (eg, the second control signal VSEL <3> <0:1>) to select one of a plurality of pre-reference voltages VREF<0:2>, and the selected voltage may be used as a reference voltage.

[0179] The control signal VGEN<1:4> may be controlled according to another one of the plurality of first control signals VGEN<1:4> (eg, the first control signal VGEN<1:4>). <4> ) to activate the fourth rectifier circuit 240.

[0180] The fourth rectifier circuit 240 may be configured to output a current according to another one of the plurality of second control signals VSEL<1:4><0:1> (eg, the second control signal VSEL <4> <0:1>) to select one of a plurality of pre-reference voltages VREF<0:2>, and the selected voltage may be used as a reference voltage.

[0181] The first to fourth rectifier circuits 210 to 240 may have the same circuit configuration.

[0182] The detection circuit 250 may generate the detection signal VGCMP according to the pre-detection signal VGOUT generated in each of the first to fourth rectifier circuits 210 to 240 .

[0183] The detection circuit 250 may generate the detection signal VGCMP by comparing the pre-detection signal VGOUT with a reference signal, that is, by comparing the current of the pre-detection signal VGOUT with a reference current.

[0184] The detection circuit 250 may have Figure 4 The circuit configuration shown is the same circuit configuration.

[0185] The reference voltage generating circuit 260 may generate a plurality of pre-reference voltages VREF<0:2> having different voltages.

[0186] The reference voltage generating circuit 260 may have Figure 5 The circuit configuration shown is the same circuit configuration.

[0187] The state machine 270 can selectively activate multiple first control signals VGEN<1:4> and adjust the values of multiple second control signals VSEL<1:4><0:1> in the output offset calibration operation of the first rectifier circuit 210 to the fourth rectifier circuit 240, and can store the values of the multiple second control signals VSEL<1:4><0:1> when the output offset calibration of the first rectifier circuit 210 to the fourth rectifier circuit 240 is completed by monitoring the resulting detection signal VGCMP.

[0188] The switch circuit 280 may couple the first node NA and the pad 32 - 1 according to a plurality of first control signals VGEN<1:4>.

[0189] The switch circuit 280 may have Figure 6 The circuit configuration shown is the same circuit configuration.

[0190] Output lines of the first to fourth rectifier circuits 210 to 240 may be commonly coupled to a first node NA.

[0191] The pad 32-1 may be Figure 7 Any of the plurality of pads of the input / output circuit region 32 as shown.

[0192] The external system 40 may perform a voltage forcing operation, ie, an operation of applying a voltage to the pad 32 - 1 so that levels of the output terminals of the first to fourth rectifier circuits 210 to 240 are the same as a target level of the internal voltage VCCI.

[0193] An offset calibration operation of the voltage offset calibration system 2 according to the above-described another embodiment of the present disclosure will be described.

[0194] The semiconductor device 30 may sequentially perform the offset calibration operation for the first to fourth rectifier circuits 210 to 240 regardless of the order of the first to fourth rectifier circuits 210 to 240 .

[0195] In the embodiment of the present disclosure, an example in which the offset calibration operation is performed in the order of the first rectifier circuit 210 , the second rectifier circuit 220 , the third rectifier circuit 230 , and the fourth rectifier circuit 240 will be described.

[0196] The semiconductor device 30, that is, the state machine 270 of the semiconductor device 30, may activate only the first control signal VGEN among the plurality of first control signals VGEN<1:4> at an internally set time and / or according to a command of the external system 40. <1> Hereinafter, activation of a signal may mean that the corresponding signal is at a high level.

[0197] Since the first control signal VGEN <1> is at a high level, so the switch circuit 280 can connect the first node NA and the pad 32 - 1 .

[0198] By voltage forcing of the external system 40 via the pad 32 - 1 , the level of the output terminal of the first rectifier circuit 210 may become the same voltage level as the target level of the internal voltage VCCI.

[0199] During the offset calibration process, the levels of the output terminals of the first to fourth rectifier circuits 210 to 240 are not generated within the semiconductor device 30 but are determined by external voltage forcing (i.e., forced voltage application). Therefore, regardless of the operation of the semiconductor device 30, the levels of the output terminals of the first to fourth rectifier circuits 210 to 240 can be stably maintained at the same target level as the internal voltage VCCI.

[0200] Since the first control signal VGEN <1> is a high level, the third control signal AMPEN may be generated to be at a high level.

[0201] Since the first control signal VGEN <1> When the third control signal AMPEN is at a high level, the pre-detection signal VGOUT generated in the first rectifier circuit 210 among the first to fourth rectifier circuits 210 to 240 can be provided to the detection circuit 250 .

[0202] The detection circuit 250 may output a detection signal VGCMP at a high level or a low level according to the pre-detection signal VGOUT.

[0203] The state machine 270 may adjust the pre-selection signal VSELEXT corresponding to the first rectifier circuit 210 among the pre-selection signals VSELEXT<1:4><0:1>. <1> The value of <0:1>.

[0204] With the preselection signal VSELEXT <1> The value of <0:1> is adjusted, and the second control signal VSEL corresponding to the first rectifier circuit 210 among the plurality of second control signals VSEL<1:4><0:1> can be adjusted. <1> <0:1>, so the level of the reference voltage VREF of the first rectifier circuit 210 can be adjusted.

[0205] The state machine 270 may monitor the transition of the logic level of the detection signal VGCMP while adjusting the level of the reference voltage VREF of the first rectifier circuit 210 in the manner described above.

[0206] When the logic level of the detection signal VGCMP transitions from a high level to a low level or from a low level to a high level, the state machine 270 may determine the corresponding time as the time when the offset calibration of the output level of the first rectifier circuit 210 is completed.

[0207] If the logic level transition of the detection signal VGCMP occurs, the second control signal VSEL is stopped. <1> By adjusting <0:1> and storing the corresponding signal value, the state machine 270 can complete the output offset calibration for the first rectifier circuit 210 .

[0208] The output offset calibration for the second to fourth rectifier circuits 220 to 240 may be performed in the same method as the output offset calibration method for the first rectifier circuit 210 described above.

[0209] If the output offset calibration for the first to fourth rectifier circuits 210 to 240 is completed, a plurality of second control signals VSEL<1:4><0:1> for providing a reference voltage VREF capable of calibrating the output level offset of each of the first to fourth rectifier circuits 210 to 240 may be stored in the state machine 270.

[0210] After completing the output offset calibration for the first to fourth rectifier circuits 210 to 240, in typical operation, all values of the plurality of first control signals VGEN<1:4> may become low levels, so that the first node NA and the pad 32-1 may be electrically disconnected, and the output of the pre-detection signal VGOUT may be blocked.

[0211] In typical operation, when the internal voltage enable signal VCCIEN becomes high, the first to fourth rectifier circuits 210 to 240 may generate the internal voltage VCCI at a target level according to the plurality of second control signals VSEL<1:4><0:1> that have been stored.

[0212] Although various embodiments have been described above, those skilled in the art will appreciate that the described embodiments are merely examples and therefore the voltage generating circuit, semiconductor device including the same, and voltage offset calibration system described herein should not be limited based on the described embodiments.

[0213] CROSS-REFERENCE TO RELATED APPLICATIONS

[0214] This application claims the benefit of Korean Application No. 10-2020-0121954 filed on September 22, 2020, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A voltage generating circuit, comprising: a plurality of rectifier circuits that are selectively activated according to a plurality of first control signals and generate internal voltages according to respective reference voltages that can be independently adjusted according to a plurality of second control signals; a detection circuit that generates a detection signal by comparing a pre-detection signal generated in each of the plurality of rectifier circuits with a reference signal; as well as A storage circuit stores preselected signals provided from an external system and outputs the stored signals as the plurality of second control signals.

2. The voltage generating circuit according to claim 1, further comprising: A switch circuit couples first nodes commonly coupled to corresponding output lines of the plurality of rectifier circuits to a pad according to the plurality of first control signals.

3. The voltage generating circuit according to claim 2, wherein: The switching circuit comprises: a switch coupled between the first node and the pad; and A logic gate turns on the switch when any one of the plurality of first control signals is at a first logic level.

4. The voltage generating circuit according to claim 2, wherein: The levels of the output terminals of the plurality of rectifier circuits are set to the same voltage level as the target level of the internal voltage by voltage forcing via the pad.

5. The voltage generating circuit according to claim 1, wherein: Each of the plurality of rectifier circuits comprises: a differential amplifier, the differential amplifier outputting a result of comparing the reference voltage and a feedback voltage; a driver that generates the internal voltage by driving an external voltage according to an output of the differential amplifier; a voltage-dividing resistor configured to output the feedback voltage by dividing the internal voltage; a multiplexer configured to output the reference voltage by selecting one of a plurality of pre-reference voltages according to a portion of the plurality of second control signals; and A switch is configured to output the output of the differential amplifier as the pre-detection signal according to a portion of the plurality of first control signals.

6. The voltage generating circuit according to claim 5, further comprising: A logic gate that activates the differential amplifier based on a result of an OR operation of the portion of the plurality of first control signals and an internal voltage enable signal, the internal voltage enable signal being used to activate the plurality of rectifier circuits in typical operation.

7. The voltage generating circuit according to claim 1, wherein: The detection circuit comprises: a driver configured to drive a current corresponding to an external voltage according to the pre-detection signal; and A comparator generates the detection signal by comparing the reference signal according to a reference current source with the current driven by the driver.

8. A semiconductor device, comprising: a plurality of rectifier circuits that are selectively activated according to a plurality of first control signals and generate internal voltages according to respective reference voltages that can be independently adjusted according to a plurality of second control signals; a detection circuit that generates a detection signal by comparing a pre-detection signal generated in each of the plurality of rectifier circuits with a reference signal; as well as A state machine selectively activates the plurality of first control signals and adjusts values of the plurality of second control signals, and stores the values of the plurality of second control signals when output offset calibration of the plurality of rectifier circuits is completed by monitoring a resultant detection signal.

9. The semiconductor device according to claim 8, further comprising: A switch circuit couples first nodes commonly coupled to corresponding output lines of the plurality of rectifier circuits to a pad according to the plurality of first control signals.

10. The semiconductor device according to claim 9, wherein The switching circuit comprises: a switch coupled between the first node and the pad; and A logic gate turns on the switch when any one of the plurality of first control signals is at a first logic level.

11. The semiconductor device according to claim 9, wherein The levels of the output terminals of the plurality of rectifier circuits are set to the same voltage level as the target level of the internal voltage by voltage forcing of a voltage from a system external to the semiconductor device via the pad.

12. The semiconductor device according to claim 8, wherein Each of the plurality of rectifier circuits comprises: a differential amplifier, the differential amplifier outputting a result of comparing the reference voltage and a feedback voltage; a driver that generates the internal voltage by driving an external voltage according to an output of the differential amplifier; a voltage-dividing resistor configured to output the feedback voltage by dividing the internal voltage; a multiplexer configured to output the reference voltage by selecting one of a plurality of pre-reference voltages according to a portion of the plurality of second control signals; and A switch is configured to output the output of the differential amplifier as the pre-detection signal according to a portion of the plurality of first control signals.

13. The semiconductor device according to claim 12, further comprising: A logic gate that activates the differential amplifier based on a result of an OR operation of the portion of the plurality of first control signals and an internal voltage enable signal, the internal voltage enable signal being used to activate the plurality of rectifier circuits in typical operation.

14. The semiconductor device according to claim 8, wherein The detection circuit comprises: a driver configured to drive a current corresponding to an external voltage according to the pre-detection signal; and A comparator generates the detection signal by comparing the reference signal according to a reference current source with the current driven by the driver.

15. The semiconductor device according to claim 8, wherein The semiconductor device further includes: Memory area; an input / output circuit area that performs data transmission / reception operations with respect to the memory area and an external system; and a functional circuit region including circuits for performing various functions related to the operation of the semiconductor device, The plurality of rectifier circuits are arranged in the functional circuit area in a distributed manner.

16. A voltage offset calibration system, comprising: A semiconductor device, comprising: a plurality of rectifier circuits that are selectively activated according to a plurality of first control signals and generate internal voltages according to respective reference voltages that can be independently adjusted according to a plurality of second control signals; and a detection circuit that generates a detection signal by comparing a pre-detection signal generated in each of the plurality of rectifier circuits with a reference signal; and an external system that calibrates an offset of an output voltage of each of the plurality of rectifying circuits by monitoring the detection signal according to adjusting a reference voltage of each of the plurality of rectifying circuits by using the first control signal and the second control signal, The semiconductor device further includes a storage circuit configured to store preselection signals provided from the external system and output the stored signals as the plurality of second control signals.

17. The voltage offset calibration system according to claim 16, wherein: The external system applies a voltage to the semiconductor device so that levels of the output terminals of the plurality of rectifier circuits become the same as a target level of an internal voltage.

18. The voltage offset calibration system according to claim 16, further comprising: A switch circuit couples first nodes commonly coupled to corresponding output lines of the plurality of rectifier circuits to a pad according to the plurality of first control signals.

19. The voltage offset calibration system according to claim 18, wherein: The switching circuit comprises: a switch coupled between the first node and the pad; and A logic gate is provided for turning on the switch when any one of the plurality of first control signals is at a first logic level.

20. The voltage offset calibration system of claim 16, wherein: Each of the plurality of rectifier circuits comprises: a differential amplifier, the differential amplifier outputting a result of comparing the reference voltage and a feedback voltage; a driver that generates the internal voltage by driving an external voltage according to an output of the differential amplifier; a voltage-dividing resistor configured to output the feedback voltage by dividing the internal voltage; a multiplexer configured to output the reference voltage by selecting one of a plurality of pre-reference voltages according to a portion of the plurality of second control signals; and A switch is configured to output the output of the differential amplifier as the pre-detection signal according to a portion of the plurality of first control signals.

21. The voltage offset calibration system according to claim 20, further comprising: A logic gate that activates the differential amplifier based on a result of an OR operation of the portion of the plurality of first control signals and an internal voltage enable signal, the internal voltage enable signal being used to activate the plurality of rectifier circuits in typical operation.

22. The voltage offset calibration system of claim 16, wherein: The detection circuit comprises: a driver configured to drive a current corresponding to an external voltage according to the pre-detection signal; and A comparator generates the detection signal by comparing the reference signal according to a reference current source with the current driven by the driver.

23. The voltage offset calibration system of claim 16, wherein: The semiconductor device further includes: Memory area; an input / output circuit area that performs data transmission / reception operations with respect to the memory area and an external system; and a functional circuit region including circuits for performing various functions related to the operation of the semiconductor device, The plurality of rectifier circuits are arranged in the functional circuit area in a distributed manner.

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