A common mode cancellation circuit for switched capacitor sampling circuit

Abstract

The present application discloses a common-mode cancellation circuit of a switched capacitor sampling circuit, comprising a first sampling circuit, a second sampling circuit and a common-mode replication circuit; the common-mode replication circuit comprises two common-mode resistors of equal value connected in series between the first input terminal and the second input terminal, and an operational amplifier for replicating the input common-mode signal, the positive input terminal of the operational amplifier is electrically connected to the two common-mode resistors, the reverse input terminal of the operational amplifier is short-circuited to the output terminal, and the output terminal of the operational amplifier is also electrically connected to the first output terminal and the second output terminal respectively through a second switch and a fifth switch controlled by the same timing. The present invention can achieve the cancellation of the input common-mode noise signal, retain the target differential mode signal, and improve the common-mode rejection ratio of the sampling circuit.

Description

Technical Field

[0001] The present invention relates to the field of circuits, in particular to the field of sampling circuit technology, and specifically to a common-mode cancellation circuit of a switched capacitor sampling circuit, which is used to cancel common-mode noise signals in the sampling circuit. Background Art

[0002] In application scenarios of weak signal acquisition such as ECG, EEG, pressure, vibration, etc., the target signal source is usually accompanied by a large common-mode signal (noise). For example, the amplitude of the ECG signal is around tens of uV to 10mV, while its common-mode interference may reach several V or even higher. Therefore, in many cases, the amplitude of the common-mode signal (noise) may be several orders of magnitude larger than the weak signal. Therefore, in order to improve the anti-interference ability of the acquisition system, a high-precision signal acquisition front end requires a higher common-mode rejection ratio (CMRR). Depending on the dynamic range of different systems, the common-mode rejection ratio requirements usually range from 80dB to 120dB. In many designs, this indicator is achieved by adding a front-end instrumentation amplifier. On the one hand, the instrumentation amplifier amplifies the weak differential signal (target signal), while suppressing common-mode interference and preventing the common-mode interference from being converted into a differential signal. In this way, without common-mode interference, the subsequent circuit can more easily process the amplified differential signal. However, instrumentation amplifiers with high common-mode rejection ratio and high input common-mode range have always been difficult to design circuits because instrumentation amplifiers are usually required to provide relatively stable performance over a larger input common-mode range.

[0003] In view of the above objective reality, a new circuit technology is needed to filter out the common mode signal (noise) during the signal acquisition process, so as to obtain a relatively pure target signal. Summary of the invention

[0004] In order to solve the technical problem that the common-mode noise input is inevitably accompanied by the existing signal sampling process, which causes the target signal to be mixed with the common-mode noise during the conversion process, causing the common-mode interference to be converted into a differential-mode signal, and finally causing the collected quantized signal to be seriously distorted, the present application provides a common-mode cancellation circuit of a switched capacitor sampling circuit, which is used to remove the common-mode signal mixed in the target differential-mode signal during the sampling process, so that the differential-mode signal input to the subsequent conversion circuit (such as ADC conversion) is a pure target sampling signal, thereby ensuring the authenticity and accuracy of the sampled signal and laying a foundation for the precise quantization of the subsequent signal.

[0005] In order to achieve the above purpose, the technical solution adopted in this application is:

[0006] A common-mode cancellation circuit for a switched capacitor sampling circuit comprises a first sampling circuit, a second sampling circuit and a common-mode replica circuit;

[0007] The first sampling circuit is used to sample the input signal of the positive input terminal, and includes a first input terminal and a first output terminal; the second sampling circuit is used to sample the input signal of the negative input terminal, and includes a second input terminal and a second output terminal;

[0008] The common-mode replication circuit includes two common-mode resistors of equal value connected in series between the first input terminal and the second input terminal, and an operational amplifier for replicating the input common-mode signal, wherein the positive input terminal of the operational amplifier is electrically connected to the two common-mode resistors, the reverse input terminal of the operational amplifier is short-circuited to the output terminal, and the output terminal of the operational amplifier is also electrically connected to the first output terminal and the second output terminal respectively through a second switch and a fifth switch controlled by the same timing.

[0009] The first sampling circuit further includes a first switch electrically connected to the first input terminal, the first switch electrically connected to the first output terminal through a first sampling capacitor, and a third switch, the third switch connecting the lower plate of the first sampling capacitor and a common-mode VCM, and a first parasitic capacitor is further provided between the common-mode VCM and the first output terminal;

[0010] The second sampling circuit further includes a fourth switch electrically connected to the second input terminal, the fourth switch electrically connected to the second output terminal through a second sampling capacitor, and a sixth switch, the sixth switch connecting the lower plate of the second sampling capacitor and a common-mode VCM, and a second parasitic capacitor is further provided between the common-mode VCM and the second output terminal;

[0011] The first switch and the fourth switch are in the same control sequence, and the third switch and the sixth switch are in the same control sequence.

[0012] Beneficial effects:

[0013] First, it can cancel the input common-mode noise signal and retain the target differential-mode signal;

[0014] Second, improve the common mode rejection ratio of the sampling circuit.

[0015] Third, the common-mode cancellation circuit provided by the present invention can also be applied to the ADC system with single-ended input. Usually, the differential structure needs to maintain common-mode stability. However, after the single-ended input mode is connected, one end is connected to the signal and the other end is connected to the fixed common-mode signal, and the stability of the common-mode signal cannot be guaranteed, thereby affecting the working point of the subsequent circuit, such as noise, bandwidth, harmonics, offset voltage, etc. The present invention can ensure the stability of the common mode of the subsequent circuit, so that when the single-ended connection is realized, good working performance can still be achieved. Avoid performance degradation when the single-ended connection is made.

[0016] Fourthly, the common-mode cancellation circuit provided by the present invention has greatly reduced overhead and power consumption compared to the existing instrument amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 It is the lower plate differential sampling switched capacitor circuit.

[0019] Figure 2 yes Figure 1 Control timing diagram.

[0020] Figure 3 It is a differential sampling switched capacitor circuit with a common-mode replica circuit.

[0021] Figure 4 It is the circuit principle diagram of Example 2.

[0022] Figure 5 This is the equivalent circuit diagram of Example 3.

[0023] In the figure: 100 - first sampling circuit; 101 - first input terminal; 102 - first switch; 103 - first sampling capacitor; 104 - first output terminal; 105 - first parasitic capacitor; 106 - second switch; 107 - third switch;

[0024] 200 - second sampling circuit; 201 - second input terminal; 202 - fourth switch; 203 - second sampling capacitor; 204 - second output terminal; 205 - second parasitic capacitor; 206 - fifth switch; 207 - sixth switch;

[0025] 300 - common-mode replica circuit; 301 - common-mode resistor; 302 - operational amplifier. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0028] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0029] In the description of this application, it should be noted that if the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, or the orientation or position relationship in which the product of the application is usually placed when in use. It is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, if the terms "first", "second", etc. appear in the description of this application, they are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0030] For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0031] Embodiment 1:

[0032] A common-mode cancellation circuit of a switched capacitor sampling circuit includes a first sampling circuit 100, a second sampling circuit 200 and a common-mode replica circuit 300;

[0033] The first sampling circuit 100 is used to sample the input signal of the positive input terminal, and includes a first input terminal 101 and a first output terminal 104; the second sampling circuit 200 is used to sample the input signal of the reverse input terminal, and includes a second input terminal 201 and a second output terminal 204;

[0034] The common-mode replication circuit 300 includes two common-mode resistors 301 of equal value connected in series between the first input terminal 101 and the second input terminal 201, and an operational amplifier 302 for replicating the input common-mode signal. The positive input terminal of the operational amplifier 302 is electrically connected to the two common-mode resistors 301, the reverse input terminal of the operational amplifier 302 is short-circuited with the output terminal, and the output terminal of the operational amplifier 302 is also electrically connected to the first output terminal 104 and the second output terminal 204 respectively through the second switch 106 and the fifth switch 206 controlled by the same timing.

[0035] Working principle description:

[0036] In order to more intuitively illustrate the principle of eliminating common-mode noise signals in the sampling process of this embodiment, this embodiment will first be described for a switched capacitor sampling circuit that does not have the function of eliminating common-mode noise signals, aiming to specifically highlight the precise removal principle and reliability of the common-mode noise signals in the sampling process of the present invention.

[0037] In conjunction with the instruction manual Figure 1 As shown in the figure, when sampling the differential input signal mixed with the common mode noise signal, the differential input is recorded as Vp (Vip + Vicm) and Vn (Vin + Vicm). First, take the sampling circuit where the high level input terminal Vp is located as an example. When the analog signal Vp is connected to the circuit, sampling is performed. The sampling process is as follows:

[0038] See Figure 1 As shown, the switches SW1 and SW2 are closed, the sampling circuit is turned on, and the sampling capacitor CS samples the input analog signal Vp, and the output terminal is connected to the common mode VCM. After completing one sampling,; Figure 2As shown in the control timing diagram, switch SW2 will be disconnected before switch SW1 by time t0, t0>0. After SW2 is disconnected, the sampling capacitor CS is in a charge conservation state, and other charges in the circuit are not allowed to be injected into the sampling capacitor CS, thereby ensuring that the sampling value does not change; finally, the switch SW3 in the disconnected state is closed, wherein there is a time difference t1 from the disconnection of SW1 to the closing of SW3, t1>0. At this time, the lower plate of the sampling capacitor Cs is connected to the common mode VCM, causing the voltage of the output terminal Vop to drop or rise; it is worth noting that the voltage of the output terminal Vop at this time includes the target target signal Vip and the common mode noise signal Vicm. Similarly, the sampling principle of the low-level input terminal Vn is the same as the sampling principle of the high-level input terminal mentioned above. The voltage of the low-level output terminal Von will drop or rise synchronously, so the common-mode voltage Vocm= (Vop+Von) / 2 of the upper plates of the two sampling capacitors Cs will change. Therefore, the common-mode noise will greatly affect the difficulty of suppressing and processing subsequent signals. At the same time, the subsequent processing circuit will require a larger input common-mode range to suppress it. When the common-mode signal input changes, the performance of the general operational amplifier will change. In extreme cases, the possibility of failure of the operational amplifier cannot be ruled out. Therefore, the following is adopted. Figure 1 The sampling circuit shown and Figure 2 The sampled signal obtained by the control timing shown will completely contain the common mode signal as noise, resulting in that the sampled signal is not a pure target signal.

[0039] Specifically, Figure 1 As shown, according to the charge conservation principle, in the sampling phase, after switch SW2 is disconnected before switch SW1, switch SW3 is still in the disconnected state, and the total charge of the sampling capacitor CS and the parasitic capacitor Cp is Q1 = (Vicm-Vcm)·Cs+ (Vcm- Vcm)Cp. When switch SW3 is closed, the lower plate of the sampling capacitor is connected to the common mode Vcm, and the total charge is Q2 = (Vcm- Vocm)·Cs+ Vocm·Cp;

[0040] According to the principle of charge conservation, Q1= Q2, we have:

[0041] (Vicm-Vcm)·Cs+(Vcm- Vcm)Cp=(Vcm- Vocm)·Cs+ Vocm·Cp

[0042] Then, the output common mode voltage Vocm=(Vicm-2Vcm)·Cs / Cp-Cs;

[0043] When the parasitic capacitance Cp in the circuit is 0, the output common-mode voltage Vocm is 2Vcm–Vicm.

[0044] Then △Vocm= Vcm–Vicm; similarly,

[0045] When the parasitic capacitance Cp in the circuit is ≠ 0,

[0046] Output common mode voltage Vocm=(-Vicm+2Vcm)·Cs / (Cs-Cp),

[0047] Then △Vocm=[(Vcm–Vicm)·Cs+Cp·Vcm] / (Cs-Cp);

[0048] It can be seen from the above that, under the premise of not performing common-mode cancellation, no matter whether there is parasitic capacitance Cp in the circuit, the sampled signal will inevitably be affected by the common-mode noise signal.

[0049] To this end, this embodiment particularly Figure 1 A common mode replica circuit 300 is added to the circuit to eliminate Figure 1 The circuit shown introduces common-mode noise signals to solve the problem of inaccurate signal acquisition caused by this.

[0050] The working principle of the common mode replica circuit 300 is as follows:

[0051] Combination Figure 3 and Figure 4 As shown, two equal common-mode resistors 301 are connected in series between the first input terminal 101 and the second input terminal 201. Since the target signal is a differential signal, that is, Vip and Vin are voltages with opposite phases and the same amplitude, after passing through the equal resistors 301, the voltage and current of the differential signal at the same-direction input terminal of the operational amplifier 302 are 0, and there is only the common-mode signal Vicm. Since the reverse input terminal and the output terminal of the operational amplifier 302 are short-circuited, the amplification factor of the positive input terminal and the output terminal of the operational amplifier 302 is 1, that is, the operational amplifier 302 can stably and quickly connect the common-mode signal Vicm to the first output terminal 104 and the second output terminal 204. During the sampling process, the upper plate and the lower plate of the sampling capacitor of the first sampling circuit 100 and the second sampling circuit 200 are both input with the same common-mode signal Vicm, so that the charge stored in the sampling capacitor is only affected by the target signals Vip and Vin, eliminating the influence of the common-mode signal Vicm, thereby achieving the purpose of common-mode signal cancellation.

[0052] Embodiment 2:

[0053] In order to further optimize and refine the common mode cancellation circuit of the present invention, this embodiment is based on the embodiment 1 and further combines the appendix of the specification. Figure 2-Figure 4As shown, the first sampling circuit 100 further includes a first switch 102 electrically connected to the first input terminal 101, the first switch 102 is electrically connected to the first output terminal 104 through a first sampling capacitor 103, and a third switch 107, the third switch 107 is connected to the lower plate of the first sampling capacitor 103 and the common mode VCM, and a first parasitic capacitor 105 is further provided between the common mode VCM and the first output terminal 104;

[0054] The second sampling circuit 200 further includes a fourth switch 202 electrically connected to the second input terminal 201, the fourth switch 202 electrically connected to the second output terminal 204 via a second sampling capacitor 203, and a sixth switch 207, the sixth switch 207 connecting the lower plate of the second sampling capacitor 203 and the common-mode VCM, and a second parasitic capacitor 205 is further provided between the common-mode VCM and the second output terminal 204;

[0055] The first switch 102 and the fourth switch 202 are in the same control sequence, and the third switch 107 and the sixth switch 207 are in the same control sequence.

[0056] In this embodiment, the first input terminal 101 is as shown in the attached Figure 3 The Vip+Vicm input terminal in the embodiment, the second switch 102 is SW1 (a bootstrap switch is used in this embodiment, and the corresponding fourth switch 202 is included at the same time), the linearity of the switch on-resistance is improved, the first sampling capacitor 103 is a Cs sampling capacitor, the first output terminal 104 is Vop, the second switch 106 is SW2, the third switch 107 is SW3, the switch SW2 and the switch SW3 (including the fifth switch 206 and the sixth switch 207) are both CMOS transmission gate switches, mainly for connecting the common mode; the first parasitic capacitor 105 is Cp. It is worth noting that the above-mentioned attached Figure 3 The component names recorded in the specification are intended to make the circuit clearer in this embodiment and do not involve the expression of scientific and technological attributes. They should also be understood as the interpretation of scientific and technological attributes. Figure 4 The accompanying drawings make it clearer and more intuitive for those skilled in the art to understand.

[0057] The working principle of this embodiment is the same as the first sampling circuit 100 and the second sampling circuit 200 described in Embodiment 1. The principle of achieving common mode cancellation is as described in Embodiment 1 above and will not be repeated here. The scheme of copying the input common mode Vicm by the common mode copy circuit 300 and following the common mode change of the input signal replaces the scheme of connecting the upper and lower plates of the sampling capacitor to a fixed common mode signal in the prior art. Figure 3 and 4As shown, the common-mode replication circuit 300 includes two parts: the first part is to add two equal-value Rcm resistors to take the common-mode input common-mode signal Vicm, and then connect an operational amplifier 302 with an amplification factor of 1, that is, a unit-gain closed-loop voltage buffer to achieve voltage following. In order to make the buffer have a larger input common-mode range, its operational amplifier adopts an operational amplifier with input / output rail-to-rail differential input and single-ended output. For the common-mode signal, after the input common-mode following, the common-mode voltages on the upper and lower plates of the two sampling capacitors Cs are consistent because there is no common-mode voltage difference. Therefore, when the switch SW3 is turned on, according to the principle of charge conservation, the output common-mode signal Vocm=(Vop+Von) / 2 will not change, and the output common-mode is kept stable near Vcm. It is worth noting that since it is replicated through the input, there will be no delay in the input common-mode signal, so that the common-mode cancellation circuit has a higher bandwidth. Moreover, because the output of the buffer does not need to charge and discharge the sampling capacitor, but only needs to load a smaller parasitic capacitor Cp, the op amp in the circuit does not need a circuit with a large overhead to meet a larger bandwidth, which is extremely advantageous compared to the existing instrument amplifier. In addition, the op amp can be turned off during the non-sampling period to save power consumption; when sampling occurs, it is turned on in advance for a period of time to meet the establishment requirements. By setting the duty cycle, the power consumption of the op amp can be further reduced. In this way, the common mode of the input signal can be offset by the sampling circuit itself, thereby ensuring that the subsequent circuits (such as ADC, etc.) can more easily implement signal processing. Furthermore, according to the circuit design provided in this embodiment, when there is a significant mismatch between the sampling capacitors and the parasitic capacitors Cp on both sides, the circuit helps to improve the common mode rejection ratio of the sampling circuit.

[0058] Embodiment 3:

[0059] In order to better highlight the beneficial effects of the present invention, this embodiment, based on the embodiment 2, specifically describes the common mode replica circuit 300. The function of the common mode replica circuit 300 is to replicate Vicm to Vocm in real time without delay, which is specifically achieved through the operational amplifier 302. The addition of the operational amplifier 302 is an improvement with outstanding substantial characteristics. Its technical effect is better than that of adding two equal value resistors Rcm and shorting them with Vocm (see Figure 3 In order to compare the data in detail, the equivalent circuit of the short-circuited operational amplifier 302 is shown as follows: Figure 5 As shown, specifically:

[0060] Figure 5 In the figure, Z1 is the equivalent resistance of the sampling capacitor Cs; Z2 is the equivalent resistance of the two Rcm in parallel, and Z3 is the equivalent resistance of the two parasitic capacitors Cp in parallel. Then the single-ended circuit can be simplified as follows: Figure 5 As shown, two Z1 and Z2 are connected in parallel and then connected in series with Z3. According to the voltage division principle of series circuit, we have:

[0061] I 总 =U 总 / Z 总 , Z 总 =Z 并 +Z3,Z 并 = ;

[0062] but, =

[0063] △ = /

[0064] As can be seen from the above △Vocm, the overall circuit working mode composed of the first sampling circuit 100, the second sampling circuit 200 and the common-mode replica circuit 300 is short-circuited, so that after the operational amplifier 302 is removed, the common-mode signal will be attenuated by the impedance network through passive transmission, especially when the input common-mode interference frequency is high, the attenuation is large, resulting in no following function, so that the common-mode signal cannot be offset and is mixed into the target signal for conversion, and finally part of the common-mode interference is converted into a differential signal, reducing the common-mode rejection ratio of the sampling network. As can be seen from the above, the common-mode signal following is achieved by creatively adding the operational amplifier 302 in the present application, which has made significant progress in common-mode cancellation, and has obvious results, greatly reducing the circuit complexity and overhead of realizing common-mode signal suppression, and providing a purer target analog signal for the subsequent conversion circuit.

[0065] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A common mode cancellation circuit for a switched capacitor sampling circuit, characterized in that: The invention comprises a first sampling circuit (100), a second sampling circuit (200) and a common-mode replica circuit (300); the first sampling circuit (100) is used to sample an input signal at a positive input terminal, and comprises a first input terminal (101) and a first output terminal (104); the second sampling circuit (200) is used to sample an input signal at a negative input terminal, and comprises a second input terminal (201) and a second output terminal (204); the common-mode replica circuit (300) comprises a first sampling circuit (101) and a second sampling circuit (204) arranged between the first input terminal (101) and the second output terminal (104); Two common-mode resistors (301) of equal value are connected in series between the input terminals (201), and an operational amplifier (302) for replicating the input common-mode signal, the positive input terminal of the operational amplifier (302) is electrically connected to the two common-mode resistors (301), the negative input terminal of the operational amplifier (302) is short-circuited with the output terminal, and the output terminal of the operational amplifier (302) is also electrically connected to the first output terminal (104) and the second output terminal (204) respectively through a second switch (106) and a fifth switch (206) controlled by the same timing sequence; The first sampling circuit (100) further comprises a first switch (102) electrically connected to the first input terminal (101), the first switch (102) being electrically connected to the first output terminal (104) via a first sampling capacitor (103), and a third switch (107), the third switch (107) being connected to the lower plate of the first sampling capacitor (103) and a common mode VCM, a first parasitic capacitor (105) being further provided between the common mode VCM and the first output terminal (104); the second sampling circuit (200) further comprises a fourth switch (202) electrically connected to the second input terminal (201), the fourth switch (202) being electrically connected to the second output terminal (204) via a second sampling capacitor (203), and a sixth switch (207), the sixth switch (207) being connected to the lower plate of the second sampling capacitor (203) and a common mode VCM, a second parasitic capacitor (205) being further provided between the common mode VCM and the second output terminal (204); The first switch (102) and the fourth switch (202) are located at the same control timing, and the third switch (107) and the sixth switch (207) are located at the same control timing; The operational amplifier (302) is a rail-to-rail input / output operational amplifier, and the operational amplifier (302) of the common-mode replica circuit (300) is in a closed state in a non-sampling phase and is opened before sampling.

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