A method for extracting parasitic resistance of an EDA circuit

Abstract

A method for extracting parasitic resistance of an EDA circuit, comprising the following steps: 1) cutting and dividing a circuit net into a long side part and a non-long side part; 2) calculating the parasitic resistance of each long side part; 3) setting resistance nodes on four sides of the non-long side part, and connecting the resistance nodes in pairs to form six resistors, wherein the resistance between two adjacent resistance nodes is denoted as the first type of resistor; the resistance between two resistance nodes located on the diagonal is the second type of resistor; 4) calculating the resistance values of the first type of resistor and the second type of resistor according to the aspect ratio of the non-long side part. The method of the present invention will not cause loss of resistance extraction accuracy, and can greatly improve the efficiency of circuit designers in analyzing and optimizing designs.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuit automated design, and in particular to a method for extracting parasitic resistance of an EDA circuit. Background Art

[0002] In the design of integrated circuits with high-end processes (such as processes below 12nm), although the circuit network wiring is dense, the geometry of the route itself is simple and mainly straight lines. The intersections of the routes are usually in the shape of "X", "L" and "T" (such as Figure 1 When extracting parasitic resistance, in order to achieve accurate and fast results, the part of the route where the current flows clearly is usually cut out from the circuit geometry, and its parasitic resistance is calculated using the "formula method (wire aspect ratio × block resistance)". The "long side part" is a circuit where the current flows clearly, its length is significantly greater than its width, and the inflow and outflow points of the current are located at the two ends of the length direction (such as Figure 2 ). Most of the "non-long side parts" after cutting off the "long side parts" in the route are rectangular, located at the intersection center of the "X", "L" and "T" shapes (such as Figure 2 As shown in the figure). The current flow direction in the "non-long side part" of the rectangle is unclear. In order to solve the parasitic resistance of this part, the "precise resistance extraction method" is usually used. This method is divided into three steps: grid discretization, integration of resistance network matrix, and solving resistance network matrix. In the design of high-end process integrated circuits, the number of rectangular "non-long sides" is very large. If all of them are processed by the "precise resistance extraction method", the resistance extraction efficiency will be seriously affected. Summary of the invention

[0003] In order to solve the deficiencies in the prior art, the present invention aims to provide a method for extracting parasitic resistance of an EDA circuit.

[0004] To achieve the above object, the present invention provides a method for extracting parasitic resistance of an EDA circuit, comprising the following steps:

[0005] 1) Cut the circuit wire net into long side parts and non-long side parts;

[0006] 2) Calculate the parasitic resistance of each long side;

[0007] 3) resistor nodes are set on the four sides of the non-long side part, and the resistor nodes are connected in pairs to form six resistors, wherein the resistor between two adjacent resistor nodes is recorded as the first type of resistor; the resistor between two resistor nodes located on the diagonal line is the second type of resistor;

[0008] 4) The resistance values of the first type resistor and the second type resistor are calculated based on the aspect ratio of the non-long side portion.

[0009] Further, in step 2), the parasitic resistance of the long side part is calculated using the formula method.

[0010] Further, the number of the first type of resistors is 4, and the number of the second type of resistors is 2.

[0011] Further, the first type of resistor = C1*r + C2; the second type of resistor = C3 / (r - 1.0) + C 4* r 2 + C5*r + C6, where r is the aspect ratio of the non-long side part, and C1 - C5 are constants.

[0012] Further, step 4) further includes the following steps:

[0013] Fabricate n test cases and record the aspect ratio r of each test case;

[0014] Use the accurate resistor extraction method to obtain the resistance values of each parasitic resistor under each test case;

[0015] Use the least squares method to determine the coefficients of each term in the function expressions of the first type of resistor and the second type of resistor.

[0016] Even further, it further includes solving the total parasitic resistance of the non-long side part by using the function expressions of the first type of resistor and the second type of resistor and the aspect ratio of the non-long side part, where the total parasitic resistance of the non-long side part = resistance value of the first type of resistor * 4 + resistance value of the second type of resistor * 2.

[0017] To achieve the above object, the present invention further provides an electronic device, including a memory and a processor. A program is stored on the memory and runs on the processor. When the processor runs the program, it executes the steps of the above-mentioned method for extracting the parasitic resistance of the EDA circuit.

[0018] To achieve the above object, the present invention further provides a computer-readable storage medium, on which computer instructions are stored. When the computer instructions run, they execute the steps of the above-mentioned method for extracting the parasitic resistance of the EDA circuit.

[0019] The method for extracting the parasitic resistance of the EDA circuit of the present invention has the following beneficial effects compared with the prior art: The method proposed by the present invention, which can quickly extract the parasitic resistance of the "non-long side part" of the rectangle in the high-end process, replaces the "accurate resistor extraction" method, and the acceleration effect is obvious. The method of the present invention will not cause the loss of resistor extraction accuracy, and can greatly improve the efficiency of circuit designers in analyzing and optimizing the design.

[0020] Other features and advantages of the present invention will be described in the following specification, and some of them will become obvious from the specification, or can be understood by implementing the present invention. Description of the Drawings

[0021] The accompanying drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation to the present invention. In the accompanying drawings:

[0022] Figure 1 It is a schematic diagram of the shape of the intersection of circuit network wiring in integrated circuit design;

[0023] Figure 2 is Figure 1 A schematic diagram of the cutting of the long side and non-long side of a part of the circuit network wiring shown;

[0024] Figure 3 It is a flowchart of the method for extracting the parasitic resistance of an EDA circuit according to the present invention;

[0025] Figure 4 It is a schematic diagram of setting the resistance nodes of the non-long side part according to the present invention;

[0026] Figure 5 It is a schematic diagram of a specific test example according to the embodiment of the present invention. Detailed Embodiments

[0027] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention and are not used to limit the present invention.

[0028] As described in the background art, for the parasitic resistance of the rectangular non-long side part in circuit partitioning, the "exact resistance extraction method" is usually adopted. This method is divided into three steps: grid discretization -> integrated resistance network matrix -> solving the resistance network matrix. For circuits with fewer rectangular non-long side parts after circuit cutting and partitioning, the exact resistance extraction method can be used for parasitic resistance extraction.

[0029] In the design of high-end process integrated circuits, due to the very large number of rectangular "non-long side parts", if all are processed by the "exact resistance extraction method", the resistance extraction efficiency will be seriously affected.

[0030] After the inventors extracted the parasitic resistance of the rectangular "non-long side part" using a large number of "exact resistance extraction methods", it was found that when the resistivity remains unchanged, the resistance value of the parasitic resistance of the rectangular "non-long side part" only depends on its aspect ratio and has nothing to do with the dimensions of each side. Therefore, the inventors designed a "function method" to solve the parasitic resistance of the non-long side part.

[0031] Embodiment 1

[0032] Figure 3 It is a flowchart of the method for extracting the parasitic resistance of an EDA circuit according to the present invention. The following combinesFigure 3 The extraction method of the parasitic resistance of the EDA circuit of the present invention will be described in detail.

[0033] In step 301, the circuit netlist is cut into a long-side part and a non-long-side part.

[0034] In this step, the circuit netlist is cut according to the geometric characteristics of the circuit netlist into a long-side part and a non-long-side part.

[0035] In step 302, the parasitic resistance of each long-side part is calculated.

[0036] In this part, the long-side part separated from the circuit netlist is used to quickly calculate the parasitic resistance of the "long side" using the "formula method (wire length-width ratio × sheet resistance value)".

[0037] In step 303, resistance nodes are set at the four sides of each non-long-side part to form six resistors.

[0038] In this step, one resistance node is set at each of the four sides of the non-long-side part of the rectangle, and the four resistance nodes are connected to each other, thus forming Figure 4 the six resistors as shown, and the resistor network formed by connecting these six resistors constitutes the parasitic resistance of the wire.

[0039] In step 304, the resistance values of the above six resistors are calculated according to the length-width ratio of the non-long-side part.

[0040] The six resistors can be divided into two categories according to the connection relationship of the resistance nodes: the resistance between two adjacent resistance nodes is the first type of resistor, denoted as R i , and the first type of resistor includes the resistors between a-b, b-c, c-d, and a-d; the resistance between two resistance nodes located on the diagonal is the second type of resistor, denoted as R ii , and the second type of resistor includes the resistors between a-c and b-d.

[0041] Among them, the resistance value of R i can be expressed by the function f1(r), f1(r) = C1*r + C2;

[0042] The resistance value of R ii can be expressed by the function f2(r), f2(r) = C3 / (r - 1.0) + C 4* r 2 + C5*r + C6;

[0043] Among them, r is the length-width ratio of the non-long-side part (the ratio of the length of the long side to the short side of the rectangle of the non-long-side part), and C1, C2, C3, C4, and C5 are constants.

[0044] For the coefficients in f1(r) and f2(r), they can be solved using test cases. A test case refers to the non-long side part of a rectangle with different aspect ratios. First, make several test cases, record the aspect ratio r of each test case respectively, use the "accurate resistance extraction" method to obtain the resistance values of each parasitic resistance, take the aspect ratio r of the "non-long side part" of the rectangle as the fitting independent variable, and the resistance value of the parasitic resistance as the dependent variable, determine the function form with a high fitting degree, and use the least squares method to determine the coefficients of the fitting function.

[0045] After the fitting function is determined, substituting the aspect ratio of the "non-long side" of the rectangle gives the parasitic resistance. This method is simpler and faster than the "accurate resistance extraction" method. Define this extraction method as the "function method".

[0046] To further illustrate the method of the present invention, it will be explained below in combination with Embodiment 2.

[0047] Embodiment 2

[0048] In this embodiment, a "cross-shaped" test case is adopted (for example, the "cross-shaped" circuit layout can be established using the EDA design software Aether), as Figure 5 shown in the schematic diagram of the specific test case according to the embodiment mode of the present invention. Among them, the rectangular test case abcd is the non-long side part in the circuit ABCD. The circuit ABCD can be divided into the long side part (A-a, B-b, C-c, D-d) and the non-long side part abcd. Then, set 4 resistance nodes a, b, c, d in the non-long side part of the rectangle, and solve the resistance values between each resistance node. First, calculate the resistance values of the long side part respectively, denoted as R Aa , R Bb , R Cc , R Dd . Use the "accurate resistance extraction" method to determine R AB , R AC , R AD , R BD , R BC , R CD (for example, use the RCExtlorer module ARC ("accurate resistance extraction") function to extract the parasitic resistance of the layout); calculate R ab , R ac , R ad , R bc , R bd , R cd , where

[0049] R ab = R AB - R Aa - R Bb ;

[0050] R ac=R AC -R Aa -R Cc ;

[0051] R ad =R AD -R Aa -R Dd ;

[0052] R bc =R BC -R Cc -R Bb ;

[0053] R bd =R BD -R Dd -R Bb ;

[0054] R cd =R CD- R Dd -R Cc 。

[0055] Then, according to different test cases, calculate different values of R ab 、R ac 、R ad 、R bc 、R bd 、R cd 。Obtain a set of values corresponding to R ab 、R ac 、R ad 、R bc 、R bd 、R cd and r respectively. The difference between test cases lies in the aspect ratio of the test cases. For example, but not limited to, the aspect ratios can be 1:1.1, 1:1.2, 1:1.3, 1:1.4, 1:1.5, 1:1.6, 1:1.7, 1:1.8, 1:1.9, 1:2.0, 1:3.0, 1:4.0, 1:5.0, 1:6.0, 1:7.0, 1:8.0, 1:9.0, 1:10.0, 1:20.0. Calculate the resistance R ab 、R ac 、R ad 、R bc 、R bd 、R cd 。

[0056] Taking the aspect ratio r as the fitting independent variable, and taking the resistances R ab 、R ac 、R ad 、R bc 、R bd, R cd The resistance value of is the strain, the fitting function, the resistor R ab , R ad , R bc , R cd The change in resistance value conforms to the function f1(r) = C1*r + C2; the resistor R ac , R bd The change in resistance value conforms to the function f2(r) = C3 / (r - 1.0) + C4*r 2 + C5*r + C6.

[0057] The least squares method is used to determine the coefficients of the fitting function.

[0058] The parasitic resistance of the non-long side part in the circuit is solved according to the aspect ratio of the non-long side part by using the obtained fitting functions f1(r) and f2(r).

[0059] In order to accurately and quickly extract the parasitic resistance of high-end process circuits, the present invention separates the "long side part" from the circuit according to geometric features, quickly obtains the parasitic resistance of the "long side" by using the "formula method", and uses a fast method that can replace the "accurate resistance extraction" method to extract the parasitic resistance of the rectangular "non-long side part". This method is simpler and faster than the "accurate resistance extraction" method, and this extraction method can be defined as the "function method".

[0060] The present invention uses the "function method" to accelerate the extraction of parasitic resistance for the rectangular "non-long side part" where the current flow direction cannot be determined, which has mathematical and physical bases, and it is fast, convenient and accurate to calculate the parasitic resistance using the "function method" of the present invention.

[0061] Example 3

[0062] The present invention also provides an electronic device, including a memory and a processor. A program is stored on the memory and runs on the processor. When the processor runs the program, it executes the steps of the above-mentioned method for extracting the parasitic resistance of the EDA circuit.

[0063] Example 4

[0064] The present invention also provides a computer-readable storage medium, on which computer instructions are stored. When the computer instructions run, they execute the steps of the above-mentioned method for extracting the parasitic resistance of an EDA circuit. For the method for extracting the parasitic resistance of the EDA circuit, refer to the introduction in the foregoing part and will not be elaborated here.

[0065] Those of ordinary skill in the art will understand that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for extracting parasitic resistance of an EDA circuit, characterized in that, Including the following steps: 1) Divide the circuit netlist into a long-side part and a non-long-side part; 2) Calculate the parasitic resistance of each long-side part; 3) Set resistance nodes on the four sides of the non-long-side part, and connect the resistance nodes in pairs to form six resistors. Among them, the resistance between two adjacent resistance nodes is denoted as the first type of resistor; the resistance between two resistance nodes located on the diagonal is the second type of resistor; 4) Calculate the resistance values of the first type of resistor and the second type of resistor according to the aspect ratio of the non-long-side part; The first type of resistor = C1*r + C2; The second type of resistance = C3 / (r - 1.0) + C 4* r 2 + C5*r + C6 Where r is the aspect ratio of the non-long-side part, and C1 - C5 are constants.

2. The method for extracting parasitic resistance of an EDA circuit according to claim 1, wherein In step 2), the parasitic resistance of the long-side part is calculated using the formula method.

3. The method for extracting parasitic resistance of an EDA circuit according to claim 1, wherein The number of the first type of resistor is 4, and the number of the second type of resistor is 2.

4. The method for extracting parasitic resistance of an EDA circuit according to claim 1, characterized in that, In step 4), it further includes the following steps: Make n test cases and record the aspect ratio r of each test case; Use the precise resistor extraction method to obtain the resistance values of each parasitic resistor under each test case; Use the least squares method to determine the coefficients of each term in the function expressions of the first type of resistor and the second type of resistor.

5. The method for extracting parasitic resistance of an EDA circuit according to claim 4, wherein It further includes using the function expressions of the first type of resistor and the second type of resistor and the aspect ratio of the non-long-side part to solve the total parasitic resistance of the non-long-side part, where the total parasitic resistance of the non-long-side part = resistance value of the first type of resistor * 4 + resistance value of the second type of resistor * 2.

6. An electronic device, characterized in that, Including a memory and a processor, the memory stores a program that runs on the processor, and when the processor runs the program, it executes the steps of the method for extracting the parasitic resistance of the EDA circuit according to any one of claims 1 - 5.

7. A computer-readable storage medium having computer instructions stored thereon, characterized in that, When the computer instructions run, they execute the steps of the method for extracting the parasitic resistance of the EDA circuit according to any one of claims 1 - 5.

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