A full-swing single-ended signal four-level pulse amplitude modulation IO circuit

Abstract

The present invention provides a full-swing single-ended signal four-level pulse amplitude modulation IO circuit, the decoder and the multiplexer are provided with a data signal terminal; the data signal terminal inputs two bits of data sent in the same signal cycle; the decoder and the multiplexer are provided with five potential input terminals and four signal output terminals, the output tubes include the first and second PMOS tubes and the first and second NMOS tubes; the drains of the first and second PMOS tubes and the first and second NMOS tubes are connected to each other; the source of the first PMOS tube and the source of the second PMOS tube are commonly connected to the potential VDDH; the source of the first NMOS tube and the source of the second NMOS tube are commonly connected to the potential VSSH; the gate of the first PMOS tube is connected to the signal PG0; the gate of the second PMOS tube is connected to the signal PG1; the gate of the first NMOS tube is connected to the signal NG0; the gate of the second NMOS tube is connected to the signal NG1. The present invention can realize the transmission of four levels of signals, each data signal transmits 2 bits of data information, and realizes a data transmission rate twice that of an ordinary single-ended signal digital IO circuit at the same signal frequency.

Description

Technical Field

[0001] The invention relates to the field of integrated circuits, and in particular to a full-swing single-ended signal four-level pulse amplitude modulation IO circuit. Background Art

[0002] IO circuit is a key module for signal transmission and reception, and data transmission rate is a key indicator of IO circuit performance. Traditional single-ended digital IO uses a signal line and a shared ground line to transmit signals. The power supply potential (VDDH) and ground potential (VSSH) on the signal line represent "1" and "0" signals respectively. Only 1 bit of data can be transmitted in each signal transmission cycle. Therefore, the data transmission rate of traditional IO circuits is limited by the signal transmission frequency.

[0003] Ordinary single-ended signal digital IO driver circuits can only transmit two level signals, "VDDH" and "VSSH", and the data transmission rate is limited by the signal transmission frequency.

[0004] Therefore, a new IO circuit needs to be proposed to solve the above problems. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a full-swing single-ended signal four-level pulse amplitude modulation IO circuit to solve the problem that the data transmission rate of the traditional IO circuit in the prior art is limited by the signal transmission frequency.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a full-swing single-ended signal four-level pulse amplitude modulation IO circuit, which at least includes:

[0007] Decoder and multiplexer, output tube;

[0008] The decoder and the multiplexer are provided with a data signal terminal; the data signal terminal inputs two bits of data A0 and A1 sent in the same signal cycle; the logic values ​​of the two bits of data A0 and A1 have two states of "0" and "1" respectively;

[0009] The decoder and multiplexer are further provided with five potential input terminals and four signal output terminals, wherein the five potential input terminals respectively input potentials VDDH, YA, Vcmn, Vcmp and VSSH; and the four signal output terminals respectively output signals PG0, PG1, NG0 and NG1;

[0010] The output tube includes a first and a second PMOS tube and a first and a second NMOS tube; the drains of the first and the second PMOS tubes are connected to the drains of the first and the second NMOS tubes;

[0011] The source of the first PMOS tube and the source of the second PMOS tube are connected to the potential VDDH; the source of the first NMOS tube and the source of the second NMOS tube are connected to the potential VSSH;

[0012] The gate of the first PMOS tube is connected to the signal PG0; the gate of the second PMOS tube is connected to the signal PG1; the gate of the first NMOS tube is connected to the signal NG0; and the gate of the second NMOS tube is connected to the signal NG1.

[0013] Preferably, the potential VDDH is a power supply potential, the potentials Vcmn and Vcmp are reference voltages, and the potential VSSH is a ground potential.

[0014] Preferably, it also includes a capacitor, the lower plate of the capacitor is connected to the source of the first NMOS tube and the second NMOS tube; the upper plate of the capacitor is connected to one end of a resistor; the other end of the resistor is connected to the potential YA.

[0015] Preferably, the drains of the first and second PMOS tubes, the drains of the first and second NMOS tubes, and the upper plate of the capacitor are connected and led out through a PAD, and the PAD serves as the output end of the circuit.

[0016] Preferably, when the combination of the logic values ​​of the two-bit data A0 and A1 is 00, the potentials output by the output signals PG0, PG1, NG0 and NG1 are all VDDH; and the voltage output by the PAD is VSSH.

[0017] Preferably, when the combination of the logic values ​​of the two-bit data A0 and A1 is 01, the potentials output by the output signals PG0, PG1, NG0 and NG1 are YA, VDDH, Vcmn and Vcmn respectively; and the voltage output by the PAD is 1 / 3 VDDH.

[0018] Preferably, when the combination of the logic values ​​of the two-bit data A0 and A1 is 01, the potential YA output by the output signal PG0 is connected to the PAD via a resistor.

[0019] Preferably, when the combination of the logic values ​​of the two-bit data A0 and A1 is 10, the potentials output by the output signals PG0, PG1, NG0 and NG1 are Vcmp, Vcmp, YA and VSSH respectively; and the voltage output by the PAD is 2 / 3VDDH.

[0020] Preferably, when the combination of the logic values ​​of the two-bit data A0 and A1 is 10, the potential YA output by the output signal NG0 is connected to the PAD via a resistor.

[0021] Preferably, when the combination of the logic values ​​of the two-bit data A0 and A1 is 11, the potentials output by the output signals PG0, PG1, NG0 and NG1 are all VSSH; and the voltage output by the PAD is VDDH.

[0022] As described above, the full-swing single-ended signal four-level pulse amplitude modulation IO circuit of the present invention has the following beneficial effects: the full-swing single-ended signal four-level pulse amplitude modulation IO driving circuit of the present invention can realize the sending of four level signals, can realize the transmission of 2 bits of data information for each data signal, and realize the data transmission rate twice that of the ordinary single-ended signal digital IO circuit at the same signal frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Shown is a schematic diagram of a full-swing single-ended signal four-level pulse amplitude modulation IO circuit of the present invention;

[0024] Figure 2 Shown is a circuit architecture diagram of a decoder and a multiplexer in the present invention;

[0025] Figure 3 The circuit structure diagram of the gate voltage of the output tube corresponding to the combination of the logic value of the two-bit data in the present invention is shown;

[0026] Figure 4 The circuit structure diagram of the gate voltage of the output tube corresponding to the combination of the logic value of the two-bit data is 01 in the present invention is shown;

[0027] Figure 5 The circuit structure diagram of the gate voltage of the output tube corresponding to the combination of the logic value of the two-bit data in the present invention is shown;

[0028] Figure 6 The circuit structure diagram of the gate voltage of the output tube corresponding to the combination of the logic value of the two-bit data in the present invention is shown;

[0029] Figure 7 Shown is a simulation result diagram of the voltage signal output to the PAD in the present invention. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0031] See also Figures 1 to 7It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0032] The present invention provides a full-swing single-ended signal four-level pulse amplitude modulation IO circuit, such as Figure 1 As shown, Figure 1 The schematic diagram of the full-swing single-ended signal four-level pulse amplitude modulation IO circuit of the present invention is shown. It at least includes:

[0033] Decoder and multiplexer, output tube;

[0034] The decoder and the multiplexer are provided with a data signal terminal; the data signal terminal inputs two bits of data A0 and A1 sent in the same signal cycle; the logic values ​​of the two bits of data A0 and A1 have two states of "0" and "1" respectively;

[0035] The decoder and multiplexer are further provided with five potential input terminals and four signal output terminals. The five potential input terminals respectively input potentials VDDH, YA, Vcmn, Vcmp and VSSH; the four signal output terminals respectively output signals PG0, PG1, NG0 and NG1; Figure 2 As shown, Figure 2 Shown is a circuit architecture diagram of a decoder and a multiplexer in the present invention.

[0036] The output tube includes a first and a second PMOS tube and a first and a second NMOS tube; the drains of the first and the second PMOS tubes are interconnected with the drains of the first and the second NMOS tubes; that is, the output tube includes a first PMOS tube 01, a second PMOS tube 03 and a first NMOS tube 02, a second NMOS tube 04; the drains of the first and the second PMOS tubes are interconnected with the drains of the first and the second NMOS tubes.

[0037] The source of the first PMOS tube and the source of the second PMOS tube are connected to the potential VDDH; the source of the first NMOS tube and the source of the second NMOS tube are connected to the potential VSSH;

[0038] The gate of the first PMOS tube is connected to the signal PG0; the gate of the second PMOS tube is connected to the signal PG1; the gate of the first NMOS tube is connected to the signal NG0; and the gate of the second NMOS tube is connected to the signal NG1.

[0039] Further, in the present invention, in this embodiment, the potential VDDH is a power supply potential, the potentials Vcmn and Vcmp are reference voltages, and the potential VSSH is a ground potential.

[0040] The present invention further includes a capacitor (Cload) in this embodiment, wherein the lower plate of the capacitor is connected to the source of the first NMOS tube and the second NMOS tube; the upper plate of the capacitor is connected to one end of a resistor 05; and the other end of the resistor 05 is connected to the potential YA.

[0041] Further, in this embodiment of the present invention, the drains of the first and second PMOS tubes, the drains of the first and second NMOS tubes, and the upper plate of the capacitor are connected and led out through a PAD (pad), and the PAD serves as the output end of the circuit.

[0042] Embodiment 1

[0043] The present invention further, in the first embodiment, when the combination of the logic values ​​of the two-bit data A0 and A1 is 00, the potentials of the output signals PG0, PG1, NG0, and NG1 are all VDDH; the voltage output by the PAD is VSSH. Figure 3 As shown, Figure 3 The circuit structure diagram of the gate voltage of the output tube corresponding to the combination of the logic value of the two-bit data is 00 in the present invention is shown.

[0044] Embodiment 2

[0045] The present invention further provides that in this embodiment, when the combination of the logic values ​​of the two-bit data A0 and A1 is 01, the potentials of the output signals PG0, PG1, NG0, and NG1 are YA, VDDH, Vcmn, and Vcmn, respectively; and the voltage output by the PAD is 1 / 3 VDDH. Figure 4 As shown, Figure 4 The circuit structure diagram of the gate voltage of the output tube corresponding to the combination of the logic value of the two-bit data is 01 in the present invention is shown.

[0046] Furthermore, when the combination of the logic values ​​of the two-bit data A0 and A1 is 01, the potential YA output by the output signal PG0 is connected to the PAD via a resistor.

[0047] Embodiment 3

[0048] The present invention further provides that, in this embodiment, when the combination of the logic values ​​of the two-bit data A0 and A1 is 10, the potentials of the output signals PG0, PG1, NG0, and NG1 are respectively Vcmp, Vcmp, YA, and VSSH; the voltage output by the PAD is 2 / 3 VDDH. Figure 5 As shown, Figure 5 The circuit structure diagram of the gate voltage of the output tube corresponding to the combination of the logic value of the two-bit data is 10 in the present invention is shown.

[0049] Furthermore, when the combination of the logic values ​​of the two-bit data A0 and A1 is 10, the potential YA output by the output signal NG0 is connected to the PAD via a resistor.

[0050] Embodiment 4

[0051] Further, in this embodiment of the present invention, when the combination of the logic values ​​of the two-bit data A0 and A1 is 11, the potentials output by the output signals PG0, PG1, NG0, and NG1 are all VSSH; and the voltage output by the PAD is VDDH.

[0052] like Figure 6 As shown, Figure 6 The circuit structure diagram of the gate voltage of the output tube corresponding to the combination of the logic value of the two-bit data is 11 in the present invention is shown.

[0053] like Figure 7 As shown, Figure 7 The simulation result of the voltage signal output to the PAD in the present invention is shown in FIG. From the simulation result, it can be seen that the method proposed in the present invention can realize the full swing four-level pulse amplitude modulation IO output.

[0054] In summary, the full-swing single-ended signal four-level pulse amplitude modulation IO driving circuit of the present invention can realize the transmission of four level signals, can realize the transmission of 2-bit data information for each data signal, and realize the data transmission rate twice that of the ordinary single-ended signal digital IO circuit at the same signal frequency. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A full-swing single-ended signal four-level pulse amplitude modulation IO circuit, characterized in that: At least: Decoder and multiplexer, output tube, capacitor; The decoder and the multiplexer are provided with a data signal terminal; the data signal terminal inputs two bits of data A0 and A1 sent in the same signal cycle; the logic values ​​of the two bits of data A0 and A1 have two states of "0" and "1" respectively; The decoder and multiplexer are further provided with five potential input terminals and four signal output terminals, wherein the five potential input terminals respectively input potentials VDDH, YA, Vcmn, Vcmp and VSSH; and the four signal output terminals respectively output signals PG0, PG1, NG0 and NG1; The output tube includes a first and a second PMOS tube and a first and a second NMOS tube; the drains of the first and the second PMOS tubes are connected to the drains of the first and the second NMOS tubes; The source of the first PMOS tube and the source of the second PMOS tube are connected to the potential VDDH; the source of the first NMOS tube and the source of the second NMOS tube are connected to the potential VSSH; The gate of the first PMOS tube is connected to the signal PG0; the gate of the second PMOS tube is connected to the signal PG1; the gate of the first NMOS tube is connected to the signal NG0; the gate of the second NMOS tube is connected to the signal NG1; The lower plate of the capacitor is connected to the source of the first NMOS tube and the second NMOS tube; the upper plate of the capacitor is connected to one end of a resistor; and the other end of the resistor is connected to the potential YA.

2. The full-swing single-ended signal four-level pulse amplitude modulation IO circuit according to claim 1, characterized in that: The potential VDDH is a power supply potential, the potentials Vcmn and Vcmp are reference voltages, and the potential VSSH is a ground potential.

3. The full-swing single-ended signal four-level pulse amplitude modulation IO circuit according to claim 1, characterized in that: The drains of the first and second PMOS tubes, the drains of the first and second NMOS tubes, and the upper plate of the capacitor are connected and led out through a PAD, and the PAD serves as the output end of the circuit.

4. The full-swing single-ended signal four-level pulse amplitude modulation IO circuit according to claim 3, characterized in that: When the combination of the logic values ​​of the two-bit data A0 and A1 is 00, the potentials of the output signals PG0, PG1, NG0, and NG1 are all VDDH; and the voltage output by the PAD is VSSH.

5. The full-swing single-ended signal four-level pulse amplitude modulation IO circuit according to claim 3, characterized in that: When the combination of the logic values ​​of the two-bit data A0 and A1 is 01, the potentials output by the output signals PG0, PG1, NG0, and NG1 are YA, VDDH, Vcmn, and Vcmn, respectively; and the voltage output by the PAD is 1 / 3 VDDH.

6. The full-swing single-ended signal four-level pulse amplitude modulation IO circuit according to claim 5, characterized in that: When the combination of the logic values ​​of the two-bit data A0 and A1 is 01, the potential YA output by the output signal PG0 is connected to the PAD via a resistor.

7. The full-swing single-ended signal four-level pulse amplitude modulation IO circuit according to claim 3, characterized in that: When the combination of the logic values ​​of the two-bit data A0 and A1 is 10, the potentials of the output signals PG0, PG1, NG0 and NG1 are Vcmp, Vcmp, YA and VSSH respectively; and the voltage output by the PAD is 2 / 3 VDDH.

8. The full-swing single-ended signal four-level pulse amplitude modulation IO circuit according to claim 7, characterized in that: When the combination of the logic values ​​of the two-bit data A0 and A1 is 10, the potential YA output by the output signal NG0 is connected to the PAD via a resistor.

9. The full-swing single-ended signal four-level pulse amplitude modulation IO circuit according to claim 3, characterized in that: When the combination of the logic values ​​of the two-bit data A0 and A1 is 11, the potentials of the output signals PG0, PG1, NG0, and NG1 are all VSSH; and the voltage output by the PAD is VDDH.

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